Resize the uboot to 1 MB, as that will be sufficient.
Increase the kernel size from 5MB to 8MB, as android kernel build images
are more than 5MB.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Resize the uboot to 1 MB, as that will be sufficient.
Increase the kernel size from 5MB to 8MB, as android kernel build images
are more than 5MB.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
NAND.u-boot-spl-os partition is sized for 2 x NAND_BLOCK_SIZE, so that
in future it can:
- split into redundant partitions "u-boot-spl-os" and "u-boot-spl-os.backup1"
- store large DTB(s)
Signed-off-by: Pekon Gupta <pekon@ti.com>
NAND.u-boot-spl-os partition is sized for 2 x NAND_BLOCK_SIZE, so that
in future it can:
- split into redundant partitions "u-boot-spl-os" and "u-boot-spl-os.backup1"
- store large DTB(s)
Signed-off-by: Pekon Gupta <pekon@ti.com>
A divider of 5 is required to get the right period value to be
set for a given sysclk frequency. This is a fixed-constant for
all sysclks.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Locking control_core_mmr_lock1 register results in regions 0x00000100
to 0x0000079F locked out(includes key registers for bandgap etc). This
means that any write accesses will fail to reflect results without a
clear notification.
So, leave the control module unlocked.
TODO: SPL should reflect consistent behavior for entire Control module
space which includes LOCK_1-5 regions left open -> if this is done,
this should be implemented in a generic location independent of the
current logic.
Reported-by: Yan Liu <yan-liu@ti.com>
Reported-by: Mugunthan V <mugunthanvnm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
build recalibrate_io_delay only for SPL logic - SHOULD NOT be used in
DDR execution context (example in u-boot).
Reported-by: Yan Liu <yan-liu@ti.com>
Reported-by: Mugunthan V <mugunthanvnm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
If changing to AVS0 voltage is required for development purpose,
there will be some IO timing error versus datasheet. The below
sequence is required to recalibrate the IOs after AVS is done.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The register secure_emif_sdram_config in control module is copied to
the EMIF sdram_config register when it is coming out of DeepSleep0 in
order to ensure that the EMIF comes up for the correct type of DDR.
Without this, resume can hang from within the kernel.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl
and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the
desired delay in cycles that the EMIF waits without an access to enter
self-refresh, in this case 8192 cycles. With this, code desiring to
enter self refresh only has to toggle one bit to enable it.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Depending on the number of partitions available (say if QSPI also has a
table, or not) '9' is not the correct spot for the UBI image. It is
however put on the "file-system" partition, so use that.
Signed-off-by: Tom Rini <trini@ti.com>
The following commit[1] defined CPSW for CONFIG_QSPI_BOOT, but for other
configs CPSW remains disabled. Hence, doing a undef of CPSW whereever
required rather than defining it for only QSPI_BOOT.
[1] c812c28 configs: am43x-evm: change uboot offset
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
commit ef236f2929
(DRA7: Add support for ES1.1 silicon ID code)
from upstream does not contain the TI internal changes necessary.
The missing change for emif is now incorporated
Reported-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Upon further inspection of relevant parts of the architecture, the
maximum SPL binary size is 220KiB.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
We do not support sub-page on NAND on any of these parts so we must
always provide the location of the VID header offset and this is always
our page size.
Signed-off-by: Tom Rini <trini@ti.com>
Raw image support is not currently supported as a valid
image type so remove the code until it is needed to not confuse
developers.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This patch enables dynamically powering down the
IO receiver when not performing a read.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
It has been observed that with default Kernel and dtd load address, if
dtb is not relocated on AM43x, Kernel doesn't boot - probably due to
Kernel image getting overwritten by dtb.
Fix it by relocating dtb as is done for other platforms so that defaults
will make AM43x boot.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When porting the NAND and MMC boot CMD it was developer
error not porting over the contents of the NAND and MMC
boot commands as they existed in the tree.
Therefore need to update the common boot commands to what
was already available for the platforms.
Also removed the NANDARGS from the platform files so that
they do not cause confusion.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
[trini: Add omap5_common.h change]
Signed-off-by: Tom Rini <trini@ti.com>
Commonize in the ti_armv7_common.h the boot scripts for
USB, MMC and NAND.
Each board file can then select which BOOT_TARGETS are applicable
for the target board.
And any parameters based on that.
Finally removed the findfdt from the common file and made this more board
specific as omap4_common should not reference panda.
This implemenation was adopted from the tegra-common-post.h file.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
All parts of the pinmux information must be in the first 4 KiB. In
order to avoid some rather ugly linker script changes to ensure a
specific data segment was early enough, go back to asm for these pinmux
changes.
Signed-off-by: Tom Rini <trini@ti.com>
Sourav Poddar
Tom Rini
Pekon Gupta
Sricharan R
Nishanth Menon
Dave Gerlach
Lokesh Vutla
Dan Murphy
Satyanarayana, Sandhya
Afzal Mohammed