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ARM: DRA7: be explicit that IO delay is in SPL only 

build recalibrate_io_delay only for SPL logic - SHOULD NOT be used in
DDR execution context (example in u-boot).

Reported-by: Yan Liu <yan-liu@ti.com>
Reported-by: Mugunthan V <mugunthanvnm@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Nishanth Menon 2014-02-03 15:45:02 -06:00 committed by Tom Rini
parent 85f3a4c6c3
commit fe19bcd47f
1 changed files with 4 additions and 0 deletions
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4
arch/arm/cpu/armv7/omap5/hw_data.c
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@ -300,6 +300,7 @@ struct pmic_data palmas = {
};
#ifdef CONFIG_SPL_BUILD
/**
* \brief scale_iodelay function implements IODelay Recalibration.
* IODelay calibration is required if changing to AVS0 voltage,
@ -364,6 +365,7 @@ void recalibrate_io_delay(void)
/* Lock the global lock to write to the MMRs */
writel(0x0000AAAB, (*ctrl)->iodelay_config_reg_8);
}
#endif /* CONFIG_SPL_BUILD */
struct pmic_data tps659038 = {
.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
@ -376,7 +378,9 @@ struct pmic_data tps659038 = {
.i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
.pmic_bus_init = gpi2c_init,
.pmic_write = palmas_i2c_write_u8,
#ifdef CONFIG_SPL_BUILD
.recalib = recalibrate_io_delay,
#endif
};
struct vcores_data omap5430_volts = {