commit ef236f2929
(DRA7: Add support for ES1.1 silicon ID code)
from upstream does not contain the TI internal changes necessary.
The missing change for emif is now incorporated
Reported-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Upon further inspection of relevant parts of the architecture, the
maximum SPL binary size is 220KiB.
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
We do not support sub-page on NAND on any of these parts so we must
always provide the location of the VID header offset and this is always
our page size.
Signed-off-by: Tom Rini <trini@ti.com>
Raw image support is not currently supported as a valid
image type so remove the code until it is needed to not confuse
developers.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
ES1.1 silicon is a very minor variant of ES1.0. Add priliminary support
for ES1.1 IDCODE change.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
A generic is_dra7xx cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This patch enables dynamically powering down the
IO receiver when not performing a read.
This optimizes both active and standby power consumption.
This bit is not set on EVM SK and EVM 1.5 and later boards.
Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
It has been observed that with default Kernel and dtd load address, if
dtb is not relocated on AM43x, Kernel doesn't boot - probably due to
Kernel image getting overwritten by dtb.
Fix it by relocating dtb as is done for other platforms so that defaults
will make AM43x boot.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
As per the latest 0.6 version of DM for OMAP5430 ES2.0,
MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU
should be locked at 2000MHz. Fixing the same and cleaning the
previously used dpll values.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When porting the NAND and MMC boot CMD it was developer
error not porting over the contents of the NAND and MMC
boot commands as they existed in the tree.
Therefore need to update the common boot commands to what
was already available for the platforms.
Also removed the NANDARGS from the platform files so that
they do not cause confusion.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
[trini: Add omap5_common.h change]
Signed-off-by: Tom Rini <trini@ti.com>
Commonize in the ti_armv7_common.h the boot scripts for
USB, MMC and NAND.
Each board file can then select which BOOT_TARGETS are applicable
for the target board.
And any parameters based on that.
Finally removed the findfdt from the common file and made this more board
specific as omap4_common should not reference panda.
This implemenation was adopted from the tegra-common-post.h file.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Bulk erase is not happening properly on dra7 due to erase timing constraints,
add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Tested-by: Yebio Mesfin <ymesfin@ti.com>
All parts of the pinmux information must be in the first 4 KiB. In
order to avoid some rather ugly linker script changes to ensure a
specific data segment was early enough, go back to asm for these pinmux
changes.
Signed-off-by: Tom Rini <trini@ti.com>
The fdt_high variable controls how high into memory the FDT can be moved
as part of booting the kernel. We had been disabling this feature as by
default we move to the very top of memory which can often be part of
highmem and so not visible to the kernel yet. However, in other cases
the kernel BSS can overwrite the FDT at the location we use, and we
wouldn't detect this case. The answer is to re-enable relocation, but
ensure it will be in kernel-visible memory still.
Signed-off-by: Tom Rini <trini@ti.com>
In EMIF4 blocks of AM335x/TI81XX there is a register at 0x54 called
INT_CONFIG/PBBPR that has a field called PR_OLD_CONFIG that can be
changed depending on workloads of the system to ensure that accesses to
some areas don't cause accesses to other areas to be "stalled". This
can be seen for example as screen jitter when playing videos.
Signed-off-by: Tom Rini <trini@ti.com>
As per OMAP3530 TRM referenced below [1]
For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
- OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
- OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
*for x8 NAND Device*
+--------+---------+---------+---------+---------+---------+---------+
| xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
+--------+---------+---------+---------+---------+---------+---------+
*for x16 NAND Device*
+--------+--------+---------+---------+---------+---------+---------+---------+
| xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
+--------+--------+---------+---------+---------+---------+---------+---------+
This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
[1] OMAP3530: http://www.ti.com/product/omap3530
TRM: http://www.ti.com/litv/pdf/spruf98x
Chapter-25: Initialization Sub-topic: Memory Booting
Section: 25.4.7.4 NAND
Figure 25-19. ECC Locations in NAND Spare Areas
Reported-by: Stefan Roese <sr@denx.de>
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch fixes 'data-abort' while correcting bit-flips in BCH16 ecc-scheme,
when number of bit-flip counts was greater than 8.
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch adds CONFIG_SPL_NAND_DEVICE_WIDTH to specify bus-width of NAND device
CONFIG_SPL_NAND_DEVICE_WIDTH == 16: NAND device with x16 bus-width
CONFIG_SPL_NAND_DEVICE_WIDTH == 8: NAND device with x8 bus-width
Need for a separate CONFIG_xx arise from following situations.
(1) SPL NAND drivers does not have framework to parse ONFI parameter page.
(2) if !defined(CONFIG_SYS_NAND_SELF_INIT)
|- board_nand_init()
|- nand_scan()
|- nand_scan_ident()
|- nand_scan_tail()
This means board_nand_init() is called before nand_scan_ident(). So NAND
controller is initialized before the actual probing of NAND device.
However some controller (like GPMC) need to be specifically configured for
bus-width of NAND device.
In such cases, bus-width of the NAND device should be known in advance
of actual device probing. Hence, CONFIG_SPL_NAND_DEVICE_WIDTH is useful.
(3) Non-ONFI compliant devices need some mechanism to specify device bus-width
to driver.
Signed-off-by: Pekon Gupta <pekon@ti.com>
In 48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.
Signed-off-by: Vladimir Koutny <vladimir.koutny@streamunlimited.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Tom Rini <trini@ti.com>
This patch
- Adds pin-mux for x8 parallel NAND device (MT29F4G08AB) present on AM43xx_EVM
- As above NAND device has blocksize=256k, pagesize=4k, oobsize=224, so by
design ROM code expects SPL to be flashed using BCH16 ECC scheme. Hence
CONFIG_NAND_OMAP_ECCSCHEME = OMAP_ECC_BCH16_CODE_HW is enabled.
- Specifies MTD partition table which needs same as kernel DTS for AM43xx_EVM.
- Populates other CONFIG_xx parameters required for NAND Boot on AM43xx
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch
- Groups all CONFIG_xx required for enabling parallel NAND on AM335x_EVM
into single file include/configs/am335x_evm.h
- Updates MTD partition table to include backup partitions for
u-boot, environment and u-boot-spl-os.
- Aligns MTD partitions (except for SPL partitions) such that partition offsets
and sizes remain constant for all NAND devices with blocksize=128k or 256k.
(because MTD partitions need to be aligned with blocksize boundary)
Signed-off-by: Pekon Gupta <pekon@ti.com>
Most of TI's SoC platform have in-buit GPMC (General Purpose Memory Controller)
which can be used to interface different types of external memories like:
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
This patch:
- As the GPMC hardware engine is common across all OMAPx and AMxxxx platforms,
so GPMC initialization code from all platforms is merged into single file:
arch/arm/cpu/armv7/omap-common/mem-common.c
- But as different platforms support different operating clock frequencies,
So, same memory device can have different GPMC configuration values on
different platforms (like memory signal timing values of same device may
differ on different platforms). Hence actual GPMC configuration parameters
are still kept separately in following platform specific header files:
AM33xx: [unchanged] arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: [modified] arch/arm/include/asm/arch-omap3/mem.h
OMAP4: [new] arch/arm/include/asm/arch-omap4/mem.h
OMAP5: [new] arch/arm/include/asm/arch-omap5/mem.h
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch adds OMAP5 platform specific information to enable GPMC controller,
which can interface different types of external memories like:
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
Signed-off-by: Pekon Gupta <pekon@ti.com>
This patch adds OMAP4 platform specific information to enable in-built GPMC and
ELM controller, which can interface following types of external memories:
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
Signed-off-by: Pekon Gupta <pekon@ti.com>
With increase in NAND flash densities occurence of bit-flips has increased.
Thus stronger ECC schemes are required for detecting and correcting multiple
simultaneous bit-flips in same NAND page. But stronger ECC schemes have large
ECC syndrome which require more space in OOB/Spare.
This patch add support for BCH16_ECC:
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: Pekon Gupta <pekon@ti.com>
With increase in NAND flash densities occurence of bit-flips has increased.
Thus stronger ECC schemes are required for detecting and correcting multiple
simultaneous bit-flips in same NAND page. But stronger ECC schemes have large
ECC syndrome which require more space in OOB/Spare.
This patch add support for BCH16_ECC:
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: Pekon Gupta <pekon@ti.com>
Increase read only segment size so that more peheripheral support can be
added to SPL like Ethernet or USB. The OCMC ram size is 256K, so allocating
~220K for read only segment.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.
Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the
read latency expected will be CL+3 as per tests from HW folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team to
come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit "ARM: DRA7/OMAP5: EMIF: Add workaround for bug 0039"
introduces the following build error.
arch/arm/cpu/armv7/omap-common/libomap-common.o: In function `do_bug0039_workaround':
/home/lokesh/exp/mainline/u-boot/arch/arm/cpu/armv7/omap-common/emif-common.c:1284: undefined reference to `get_bug_regs'
This is because of missing function call in OMAP4. Adding a weak function
for this.
Reported-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Commit "ARM: OMAP5: DRA7xx: Add workaround for ARM errata 798870"
introduces the follwoing build warning for OMAP5 and build break for OMAP4.
hwinit-common.c: In function 's_init':
hwinit-common.c:132:2: warning: implicit declaration of function 'arm_errata_798870' [-Wimplicit-function-declaration]
As this function is called for both OMAP5 and OMAP4 and defined only for OMAP5
causing a build error for OMAP4
Fixing by moving this function common to OMAP4/5.
This will not break any functionality on OMAP4 as it checks for A15.
Reported-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sourav Poddar
Tom Rini
Nishanth Menon
Dan Murphy
SRICHARAN R
Dave Gerlach
Satyanarayana, Sandhya
Lokesh Vutla
Afzal Mohammed
Pekon Gupta
Vladimir Koutny
Mugunthan V N