ARM: omap: merge GPMC initialization code for all platform
Most of TI's SoC platform have in-buit GPMC (General Purpose Memory Controller)
which can be used to interface different types of external memories like:
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
This patch:
- As the GPMC hardware engine is common across all OMAPx and AMxxxx platforms,
so GPMC initialization code from all platforms is merged into single file:
arch/arm/cpu/armv7/omap-common/mem-common.c
- But as different platforms support different operating clock frequencies,
So, same memory device can have different GPMC configuration values on
different platforms (like memory signal timing values of same device may
differ on different platforms). Hence actual GPMC configuration parameters
are still kept separately in following platform specific header files:
AM33xx: [unchanged] arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: [modified] arch/arm/include/asm/arch-omap3/mem.h
OMAP4: [new] arch/arm/include/asm/arch-omap4/mem.h
OMAP5: [new] arch/arm/include/asm/arch-omap5/mem.h
Signed-off-by: Pekon Gupta <pekon@ti.com>
This commit is contained in:
Pekon Gupta
parent
35a50ea51c
commit
f9519b4a1b
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@ -18,7 +18,6 @@ endif
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COBJS-$(CONFIG_TI816X) += clock_ti816x.o
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COBJS += sys_info.o
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COBJS += mem.o
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COBJS += board.o
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COBJS += mux.o
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@ -1,98 +0,0 @@
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/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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struct gpmc *gpmc_cfg;
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_NOR)
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/* configure GPMC for NOR */
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const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
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STNOR_GPMC_CONFIG2,
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STNOR_GPMC_CONFIG3,
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STNOR_GPMC_CONFIG4,
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STNOR_GPMC_CONFIG5,
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STNOR_GPMC_CONFIG6,
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STNOR_GPMC_CONFIG7
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};
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u32 size = GPMC_SIZE_16M;
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u32 base = CONFIG_SYS_FLASH_BASE;
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#elif defined(CONFIG_NAND)
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/* configure GPMC for NAND */
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const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6,
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0
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};
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u32 size = GPMC_SIZE_256M;
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u32 base = CONFIG_SYS_NAND_BASE;
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#else
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const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
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u32 size = 0;
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u32 base = 0;
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#endif
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/* global settings */
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writel(0x00000008, &gpmc_cfg->sysconfig);
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writel(0x00000000, &gpmc_cfg->irqstatus);
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writel(0x00000000, &gpmc_cfg->irqenable);
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#ifdef CONFIG_NOR
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writel(0x00000200, &gpmc_cfg->config);
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#else
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writel(0x00000012, &gpmc_cfg->config);
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#endif
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/*
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* Disable the GPMC0 config set by ROM code
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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/* enable chip-select specific configurations */
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enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
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}
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@ -33,11 +33,7 @@ COBJS += boot-common.o
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SOBJS += lowlevel_init.o
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endif
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ifndef CONFIG_SPL_BUILD
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ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
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COBJS += mem-common.o
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endif
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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@ -2,31 +2,124 @@
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Steve Sakoman <steve@sakoman.com>
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* Author :
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Manikandan Pillai <mani.pillai@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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#include <linux/mtd/omap_gpmc.h>
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_OMAP34XX)
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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#endif
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/* Enable the config */
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writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
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(1 << 6)), &cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_NOR)
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/* configure GPMC for NOR */
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const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
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STNOR_GPMC_CONFIG2,
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STNOR_GPMC_CONFIG3,
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STNOR_GPMC_CONFIG4,
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STNOR_GPMC_CONFIG5,
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STNOR_GPMC_CONFIG6,
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STNOR_GPMC_CONFIG7
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};
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u32 size = GPMC_SIZE_16M;
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u32 base = CONFIG_SYS_FLASH_BASE;
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#elif defined(CONFIG_NAND)
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/* configure GPMC for NAND */
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const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6,
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0
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};
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u32 size = GPMC_SIZE_256M;
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u32 base = CONFIG_SYS_NAND_BASE;
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#else
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const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
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u32 size = 0;
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u32 base = 0;
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#endif
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/* global settings */
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
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writel(0x00000008, &gpmc_cfg->sysconfig);
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writel(0x00000000, &gpmc_cfg->irqstatus);
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writel(0x00000000, &gpmc_cfg->irqenable);
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#ifdef CONFIG_NOR
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writel(0x00000200, &gpmc_cfg->config);
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#else
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writel(0x00000012, &gpmc_cfg->config);
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#endif
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/*
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* Disable the GPMC0 config set by ROM code
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* It conflicts with our MPDB (both at 0x08000000)
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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/* enable chip-select specific configurations */
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enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
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}
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@ -13,7 +13,6 @@ SOBJS := lowlevel_init.o
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COBJS += board.o
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COBJS += clock.o
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COBJS += mem.o
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COBJS += sys_info.o
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ifdef CONFIG_SPL_BUILD
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COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
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@ -1,151 +0,0 @@
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <command.h>
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_CMD_NAND)
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#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
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static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
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SMNAND_GPMC_CONFIG1,
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SMNAND_GPMC_CONFIG2,
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SMNAND_GPMC_CONFIG3,
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SMNAND_GPMC_CONFIG4,
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SMNAND_GPMC_CONFIG5,
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SMNAND_GPMC_CONFIG6,
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0,
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};
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#else
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static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
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M_NAND_GPMC_CONFIG1,
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M_NAND_GPMC_CONFIG2,
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M_NAND_GPMC_CONFIG3,
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M_NAND_GPMC_CONFIG4,
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M_NAND_GPMC_CONFIG5,
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M_NAND_GPMC_CONFIG6, 0
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};
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#endif
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#endif /* CONFIG_CMD_NAND */
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#if defined(CONFIG_CMD_ONENAND)
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static const u32 gpmc_onenand[GPMC_MAX_REG] = {
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ONENAND_GPMC_CONFIG1,
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ONENAND_GPMC_CONFIG2,
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ONENAND_GPMC_CONFIG3,
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ONENAND_GPMC_CONFIG4,
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ONENAND_GPMC_CONFIG5,
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ONENAND_GPMC_CONFIG6, 0
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};
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#endif /* CONFIG_CMD_ONENAND */
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in guessing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(u32 cs)
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{
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u32 val1, val2, addr;
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u32 pattern = 0x12345678;
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addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
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writel(0x0, addr + 0x400); /* clear pos A */
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writel(pattern, addr); /* pattern to pos B */
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writel(0x0, addr + 4); /* remove pattern off the bus */
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val1 = readl(addr + 0x400); /* get pos A value */
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val2 = readl(addr); /* get val2 */
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writel(0x0, addr + 0x400); /* clear pos A */
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if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
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return 0;
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else
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return 1;
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}
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void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
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u32 size)
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{
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writel(0, &cs->config7);
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sdelay(1000);
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/* Delay for settling */
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writel(gpmc_config[0], &cs->config1);
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writel(gpmc_config[1], &cs->config2);
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writel(gpmc_config[2], &cs->config3);
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writel(gpmc_config[3], &cs->config4);
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writel(gpmc_config[4], &cs->config5);
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writel(gpmc_config[5], &cs->config6);
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/*
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* Enable the config. size is the CS size and goes in
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* bits 11:8. We set bit 6 to enable this CS and the base
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* address goes into bits 5:0.
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*/
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writel((size << 8) | (GPMC_CS_ENABLE << 6) |
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((base >> 24) & GPMC_BASEADDR_MASK),
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&cs->config7);
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sdelay(2000);
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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gpmc_cfg = (struct gpmc *)GPMC_BASE;
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#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
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const u32 *gpmc_config = NULL;
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u32 base = 0;
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u32 size = 0;
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#endif
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u32 config = 0;
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/* global settings */
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writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
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writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
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config = readl(&gpmc_cfg->config);
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config &= (~0xf00);
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writel(config, &gpmc_cfg->config);
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/*
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* Disable the GPMC0 config set by ROM code
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* It conflicts with our MPDB (both at 0x08000000)
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*/
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writel(0, &gpmc_cfg->cs[0].config7);
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sdelay(1000);
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#if defined(CONFIG_CMD_NAND) /* CS 0 */
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gpmc_config = gpmc_m_nand;
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base = PISMO1_NAND_BASE;
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size = PISMO1_NAND_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#endif
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#if defined(CONFIG_CMD_ONENAND)
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gpmc_config = gpmc_onenand;
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base = PISMO1_ONEN_BASE;
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size = PISMO1_ONEN_SIZE;
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enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
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#endif
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}
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@ -0,0 +1,62 @@
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/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00000800
|
||||
#define M_NAND_GPMC_CONFIG2 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG3 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG4 0x16051807
|
||||
#define M_NAND_GPMC_CONFIG5 0x00151e1e
|
||||
#define M_NAND_GPMC_CONFIG6 0x16000f80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000008
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x00001200
|
||||
#define STNOR_GPMC_CONFIG2 0x00101000
|
||||
#define STNOR_GPMC_CONFIG3 0x00030301
|
||||
#define STNOR_GPMC_CONFIG4 0x10041004
|
||||
#define STNOR_GPMC_CONFIG5 0x000C1010
|
||||
#define STNOR_GPMC_CONFIG6 0x08070280
|
||||
#define STNOR_GPMC_CONFIG7 0x00000F48
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* (C) Copyright 2006-2008
|
||||
* Texas Instruments, <www.ti.com>
|
||||
*
|
||||
* Author
|
||||
* Mansoor Ahamed <mansoor.ahamed@ti.com>
|
||||
*
|
||||
* Initial Code from:
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _MEM_H_
|
||||
#define _MEM_H_
|
||||
|
||||
/*
|
||||
* GPMC settings -
|
||||
* Definitions is as per the following format
|
||||
* #define <PART>_GPMC_CONFIG<x> <value>
|
||||
* Where:
|
||||
* PART is the part name e.g. STNOR - Intel Strata Flash
|
||||
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
|
||||
* Value is corresponding value
|
||||
*
|
||||
* For every valid PRCM configuration there should be only one definition of
|
||||
* the same. if values are independent of the board, this definition will be
|
||||
* present in this file if values are dependent on the board, then this should
|
||||
* go into corresponding mem-boardName.h file
|
||||
*
|
||||
* Currently valid part Names are (PART):
|
||||
* M_NAND - Micron NAND
|
||||
* STNOR - STMicrolelctronics M29W128GL
|
||||
*/
|
||||
#define GPMC_SIZE_256M 0x0
|
||||
#define GPMC_SIZE_128M 0x8
|
||||
#define GPMC_SIZE_64M 0xC
|
||||
#define GPMC_SIZE_32M 0xE
|
||||
#define GPMC_SIZE_16M 0xF
|
||||
|
||||
#define M_NAND_GPMC_CONFIG1 0x00000800
|
||||
#define M_NAND_GPMC_CONFIG2 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG3 0x001e1e00
|
||||
#define M_NAND_GPMC_CONFIG4 0x16051807
|
||||
#define M_NAND_GPMC_CONFIG5 0x00151e1e
|
||||
#define M_NAND_GPMC_CONFIG6 0x16000f80
|
||||
#define M_NAND_GPMC_CONFIG7 0x00000008
|
||||
|
||||
#define STNOR_GPMC_CONFIG1 0x00001200
|
||||
#define STNOR_GPMC_CONFIG2 0x00101000
|
||||
#define STNOR_GPMC_CONFIG3 0x00030301
|
||||
#define STNOR_GPMC_CONFIG4 0x10041004
|
||||
#define STNOR_GPMC_CONFIG5 0x000C1010
|
||||
#define STNOR_GPMC_CONFIG6 0x08070280
|
||||
#define STNOR_GPMC_CONFIG7 0x00000F48
|
||||
|
||||
/* max number of GPMC Chip Selects */
|
||||
#define GPMC_MAX_CS 8
|
||||
/* max number of GPMC regs */
|
||||
#define GPMC_MAX_REG 7
|
||||
|
||||
#endif /* endif _MEM_H_ */
|
||||
Loading…
Reference in New Issue