Kever Yang 41793000d7 rockchip: rk3328: add clock driver ... Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>		2017-03-16 16:03:46 -06:00
..
aspeed	aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation	2017-02-08 15:56:30 -05:00
at91	dm: allow limiting pre-reloc markings to spl or tpl	2017-03-16 16:03:44 -06:00
exynos	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
rockchip	rockchip: rk3328: add clock driver	2017-03-16 16:03:46 -06:00
tegra	clock: implement a driver for the Tegra CAR	2016-09-27 09:11:02 -07:00
uniphier	clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock	2017-01-29 20:59:08 +09:00
Kconfig	clk: zynqmp: Add clock driver support for zynqmp	2017-01-10 10:18:12 +01:00
Makefile	aspeed: Add basic ast2500-specific drivers and configuration	2017-01-28 14:04:29 -05:00
clk-uclass.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
clk_boston.c	clk: boston: Providea simple driver for Boston board clocks	2016-09-21 15:04:32 +02:00
clk_fixed_rate.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
clk_pic32.c	dm: core: Replace of_offset with accessor	2017-02-08 06:12:14 -07:00
clk_sandbox.c	clk: sandbox: don't check clk ID against 0	2016-06-24 17:24:35 -04:00
clk_sandbox_test.c	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
clk_zynqmp.c	clk: zynqmp: Add clock driver support for zynqmp	2017-01-10 10:18:12 +01:00