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aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation 

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
maxims@google.com 2017-01-30 11:35:04 -08:00 committed by Tom Rini
parent e163a931af
commit d5ce357461
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/aspeed/clk_ast2500.c
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@ -35,7 +35,7 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
& SCU_MPLL_POST_MASK;
return (clkin * ((num + 1) / (denum + 1))) / post_div;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
/*
@ -50,7 +50,7 @@ static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
& SCU_HPLL_POST_MASK;
return (clkin * ((num + 1) / (denum + 1))) / post_div;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
static ulong ast2500_get_clkin(struct ast2500_scu *scu)