Add some sata_mv fixes for Kirkwood from Marvell
svn path=/dists/sid/linux-2.6/; revision=13391
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@ -9,6 +9,11 @@ linux-2.6 (2.6.29-3) UNRELEASED; urgency=low
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[ Bastian Blank ]
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* [alpha] Fix location of kernel image.
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[ Martin Michlmayr ]
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* Add some sata_mv fixes for Kirkwood from Marvell:
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- use new sata phy register settings for new devices
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- increate the IORDY timeout for the soc controllers
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-- maximilian attems <maks@debian.org> Mon, 06 Apr 2009 11:19:29 +0200
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linux-2.6 (2.6.29-2) unstable; urgency=low
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@ -0,0 +1,123 @@
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From: Saeed Bishara <saeed@marvell.com>
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Date: Mon, 10 Nov 2008 21:21:21 -1100
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Subject: [PATCH] sata_mv: use new sata phy register settings for new devices
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Marvell's new SoC (65 nano) needs different modification for its SATA
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PHY registers.
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Signed-off-by: Saeed Bishara <saeed@marvell.com>
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--- a/drivers/ata/sata_mv.c 2009-04-11 15:38:53.000000000 +0000
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+++ b/drivers/ata/sata_mv.c 2009-04-11 15:39:09.000000000 +0000
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@@ -235,6 +235,10 @@
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FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
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FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
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+ PHY_MODE9_GEN2 = 0x398,
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+ PHY_MODE9_GEN1 = 0x39c,
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+ PHYCFG_OFS = 0x3a0, /* only in 65n devices */
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+
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MV5_PHY_MODE = 0x74,
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MV5_LTMODE_OFS = 0x30,
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MV5_PHY_CTL_OFS = 0x0C,
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@@ -530,6 +534,8 @@
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static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
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void __iomem *mmio);
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static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
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+static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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+ void __iomem *mmio, unsigned int port);
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static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
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static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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unsigned int port_no);
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@@ -714,6 +720,14 @@
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.reset_bus = mv_soc_reset_bus,
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};
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+static const struct mv_hw_ops mv_soc_65n_ops = {
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+ .phy_errata = mv_soc_65n_phy_errata,
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+ .enable_leds = mv_soc_enable_leds,
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+ .reset_hc = mv_soc_reset_hc,
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+ .reset_flash = mv_soc_reset_flash,
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+ .reset_bus = mv_soc_reset_bus,
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+};
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+
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/*
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* Functions
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*/
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@@ -2691,6 +2705,53 @@
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return;
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}
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+static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
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+ void __iomem *mmio, unsigned int port)
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+{
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+ void __iomem *port_mmio = mv_port_base(mmio, port);
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+ u32 reg;
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+
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+ reg = readl(port_mmio + PHY_MODE3);
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+ reg &= ~(0x3 << 27); /* bits 28:27 to 0x1*/
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+ reg |= (0x1 << 27);
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+ reg &= ~(0x3 << 29); /* bits 30:29 to 0x1*/
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+ reg |= (0x1 << 29);
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+ writel(reg, port_mmio + PHY_MODE3);
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+
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+ reg = readl(port_mmio + PHY_MODE4);
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+ reg &= ~0x1; /* bit 0 to 0x1, bit 16 must be set*/
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+ reg |= (0x1 << 16);
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+ writel(reg, port_mmio + PHY_MODE4);
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+
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+ reg = readl(port_mmio + PHY_MODE9_GEN2);
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+ reg &= ~0xf; /* bits 3:0 to 0x8*/
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+ reg |= 0x8;
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+ reg &= ~(0x1 << 14); /* bit 14 to 0 */
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+ writel(reg, port_mmio + PHY_MODE9_GEN2);
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+
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+ reg = readl(port_mmio + PHY_MODE9_GEN1);
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+ reg &= ~0xf; /* bits 3:0 to 0x8*/
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+ reg |= 0x8;
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+ reg &= ~(0x1 << 14); /* bit 14 to 0 */
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+ writel(reg, port_mmio + PHY_MODE9_GEN1);
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+}
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+
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+/**
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+ * soc_is_65 - check if the soc is 65 nano device
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+ *
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+ * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
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+ * register, this register should contain non-zero value and it exists only
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+ * in the 65 nano devices, when reading it from older devices we get 0.
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+ */
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+static bool soc_is_65n(struct mv_host_priv *hpriv)
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+{
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+ void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
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+
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+ if(readl(port0_mmio + PHYCFG_OFS))
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+ return true;
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+ return false;
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+}
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+
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static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
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{
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u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
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@@ -3015,7 +3076,10 @@
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}
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break;
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case chip_soc:
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- hpriv->ops = &mv_soc_ops;
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+ if(soc_is_65n(hpriv))
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+ hpriv->ops = &mv_soc_65n_ops;
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+ else
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+ hpriv->ops = &mv_soc_ops;
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hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
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MV_HP_ERRATA_60X1C0;
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break;
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@@ -3078,7 +3142,8 @@
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n_hc = mv_get_hc_count(host->ports[0]->flags);
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for (port = 0; port < host->n_ports; port++)
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- hpriv->ops->read_preamp(hpriv, port, mmio);
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+ if(hpriv->ops->read_preamp)
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+ hpriv->ops->read_preamp(hpriv, port, mmio);
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rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
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if (rc)
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@ -0,0 +1,21 @@
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From: Saeed Bishara <saeed@marvell.com>
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Date: Tue, 27 Jan 2009 18:15:59 +0200
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Subject: [PATCH] sata: increate the IORDY timeout for the soc controllers
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the old value (in clock cycles) is not suitable for soc devices that has
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internal clock more that 150MHz.
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Signed-off-by: Saeed Bishara <saeed@marvell.com>
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--- drivers/ata/sata_mv.c~ 2009-04-11 15:40:49.000000000 +0000
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+++ drivers/ata/sata_mv.c 2009-04-11 15:40:54.000000000 +0000
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@@ -2662,7 +2662,7 @@
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ZERO(0x024); /* respq outp */
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ZERO(0x020); /* respq inp */
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ZERO(0x02c); /* test control */
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- writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
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+ writel(0x800, port_mmio + EDMA_IORDY_TMOUT_OFS);
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}
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#undef ZERO
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@ -0,0 +1,2 @@
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+ bugfix/arm/sata_mv_65n.patch
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+ bugfix/arm/sata_mv_increase_timeout.patch
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