From 3c0ad1d41864f978168a1fa44c89a52b2f155c3d Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Sat, 11 Apr 2009 15:43:08 +0000 Subject: [PATCH] Add some sata_mv fixes for Kirkwood from Marvell svn path=/dists/sid/linux-2.6/; revision=13391 --- debian/changelog | 5 + debian/patches/bugfix/arm/sata_mv_65n.patch | 123 ++++++++++++++++++ .../bugfix/arm/sata_mv_increase_timeout.patch | 21 +++ debian/patches/series/3 | 2 + 4 files changed, 151 insertions(+) create mode 100644 debian/patches/bugfix/arm/sata_mv_65n.patch create mode 100644 debian/patches/bugfix/arm/sata_mv_increase_timeout.patch create mode 100644 debian/patches/series/3 diff --git a/debian/changelog b/debian/changelog index 012164a2e..0dd89f86c 100644 --- a/debian/changelog +++ b/debian/changelog @@ -9,6 +9,11 @@ linux-2.6 (2.6.29-3) UNRELEASED; urgency=low [ Bastian Blank ] * [alpha] Fix location of kernel image. + [ Martin Michlmayr ] + * Add some sata_mv fixes for Kirkwood from Marvell: + - use new sata phy register settings for new devices + - increate the IORDY timeout for the soc controllers + -- maximilian attems Mon, 06 Apr 2009 11:19:29 +0200 linux-2.6 (2.6.29-2) unstable; urgency=low diff --git a/debian/patches/bugfix/arm/sata_mv_65n.patch b/debian/patches/bugfix/arm/sata_mv_65n.patch new file mode 100644 index 000000000..a8cc0e30b --- /dev/null +++ b/debian/patches/bugfix/arm/sata_mv_65n.patch @@ -0,0 +1,123 @@ +From: Saeed Bishara +Date: Mon, 10 Nov 2008 21:21:21 -1100 +Subject: [PATCH] sata_mv: use new sata phy register settings for new devices + +Marvell's new SoC (65 nano) needs different modification for its SATA +PHY registers. + +Signed-off-by: Saeed Bishara + + +--- a/drivers/ata/sata_mv.c 2009-04-11 15:38:53.000000000 +0000 ++++ b/drivers/ata/sata_mv.c 2009-04-11 15:39:09.000000000 +0000 +@@ -235,6 +235,10 @@ + FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ + FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ + ++ PHY_MODE9_GEN2 = 0x398, ++ PHY_MODE9_GEN1 = 0x39c, ++ PHYCFG_OFS = 0x3a0, /* only in 65n devices */ ++ + MV5_PHY_MODE = 0x74, + MV5_LTMODE_OFS = 0x30, + MV5_PHY_CTL_OFS = 0x0C, +@@ -530,6 +534,8 @@ + static void mv_soc_reset_flash(struct mv_host_priv *hpriv, + void __iomem *mmio); + static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); ++static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, ++ void __iomem *mmio, unsigned int port); + static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); + static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, + unsigned int port_no); +@@ -714,6 +720,14 @@ + .reset_bus = mv_soc_reset_bus, + }; + ++static const struct mv_hw_ops mv_soc_65n_ops = { ++ .phy_errata = mv_soc_65n_phy_errata, ++ .enable_leds = mv_soc_enable_leds, ++ .reset_hc = mv_soc_reset_hc, ++ .reset_flash = mv_soc_reset_flash, ++ .reset_bus = mv_soc_reset_bus, ++}; ++ + /* + * Functions + */ +@@ -2691,6 +2705,53 @@ + return; + } + ++static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, ++ void __iomem *mmio, unsigned int port) ++{ ++ void __iomem *port_mmio = mv_port_base(mmio, port); ++ u32 reg; ++ ++ reg = readl(port_mmio + PHY_MODE3); ++ reg &= ~(0x3 << 27); /* bits 28:27 to 0x1*/ ++ reg |= (0x1 << 27); ++ reg &= ~(0x3 << 29); /* bits 30:29 to 0x1*/ ++ reg |= (0x1 << 29); ++ writel(reg, port_mmio + PHY_MODE3); ++ ++ reg = readl(port_mmio + PHY_MODE4); ++ reg &= ~0x1; /* bit 0 to 0x1, bit 16 must be set*/ ++ reg |= (0x1 << 16); ++ writel(reg, port_mmio + PHY_MODE4); ++ ++ reg = readl(port_mmio + PHY_MODE9_GEN2); ++ reg &= ~0xf; /* bits 3:0 to 0x8*/ ++ reg |= 0x8; ++ reg &= ~(0x1 << 14); /* bit 14 to 0 */ ++ writel(reg, port_mmio + PHY_MODE9_GEN2); ++ ++ reg = readl(port_mmio + PHY_MODE9_GEN1); ++ reg &= ~0xf; /* bits 3:0 to 0x8*/ ++ reg |= 0x8; ++ reg &= ~(0x1 << 14); /* bit 14 to 0 */ ++ writel(reg, port_mmio + PHY_MODE9_GEN1); ++} ++ ++/** ++ * soc_is_65 - check if the soc is 65 nano device ++ * ++ * Detect the type of the SoC, this is done by reading the PHYCFG_OFS ++ * register, this register should contain non-zero value and it exists only ++ * in the 65 nano devices, when reading it from older devices we get 0. ++ */ ++static bool soc_is_65n(struct mv_host_priv *hpriv) ++{ ++ void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); ++ ++ if(readl(port0_mmio + PHYCFG_OFS)) ++ return true; ++ return false; ++} ++ + static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) + { + u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); +@@ -3015,7 +3076,10 @@ + } + break; + case chip_soc: +- hpriv->ops = &mv_soc_ops; ++ if(soc_is_65n(hpriv)) ++ hpriv->ops = &mv_soc_65n_ops; ++ else ++ hpriv->ops = &mv_soc_ops; + hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | + MV_HP_ERRATA_60X1C0; + break; +@@ -3078,7 +3142,8 @@ + n_hc = mv_get_hc_count(host->ports[0]->flags); + + for (port = 0; port < host->n_ports; port++) +- hpriv->ops->read_preamp(hpriv, port, mmio); ++ if(hpriv->ops->read_preamp) ++ hpriv->ops->read_preamp(hpriv, port, mmio); + + rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); + if (rc) diff --git a/debian/patches/bugfix/arm/sata_mv_increase_timeout.patch b/debian/patches/bugfix/arm/sata_mv_increase_timeout.patch new file mode 100644 index 000000000..2c87987d1 --- /dev/null +++ b/debian/patches/bugfix/arm/sata_mv_increase_timeout.patch @@ -0,0 +1,21 @@ +From: Saeed Bishara +Date: Tue, 27 Jan 2009 18:15:59 +0200 +Subject: [PATCH] sata: increate the IORDY timeout for the soc controllers + +the old value (in clock cycles) is not suitable for soc devices that has +internal clock more that 150MHz. + +Signed-off-by: Saeed Bishara + + +--- drivers/ata/sata_mv.c~ 2009-04-11 15:40:49.000000000 +0000 ++++ drivers/ata/sata_mv.c 2009-04-11 15:40:54.000000000 +0000 +@@ -2662,7 +2662,7 @@ + ZERO(0x024); /* respq outp */ + ZERO(0x020); /* respq inp */ + ZERO(0x02c); /* test control */ +- writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); ++ writel(0x800, port_mmio + EDMA_IORDY_TMOUT_OFS); + } + + #undef ZERO diff --git a/debian/patches/series/3 b/debian/patches/series/3 new file mode 100644 index 000000000..4d67e5e3f --- /dev/null +++ b/debian/patches/series/3 @@ -0,0 +1,2 @@ ++ bugfix/arm/sata_mv_65n.patch ++ bugfix/arm/sata_mv_increase_timeout.patch