420 lines
10 KiB
C
420 lines
10 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3328.h>
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#include <asm/arch/periph.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rk3328_pinctrl_priv {
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struct rk3328_grf_regs *grf;
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};
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enum {
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/* GRF_GPIO0A_IOMUX */
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GRF_GPIO0A5_SEL_SHIFT = 10,
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GRF_GPIO0A5_SEL_MASK = 3 << GRF_GPIO0A5_SEL_SHIFT,
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GRF_I2C3_SCL = 2,
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GRF_GPIO0A6_SEL_SHIFT = 12,
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GRF_GPIO0A6_SEL_MASK = 3 << GRF_GPIO0A6_SEL_SHIFT,
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GRF_I2C3_SDA = 2,
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GRF_GPIO0A7_SEL_SHIFT = 14,
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GRF_GPIO0A7_SEL_MASK = 3 << GRF_GPIO0A7_SEL_SHIFT,
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GRF_EMMC_DATA0 = 2,
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/* GRF_GPIO1A_IOMUX */
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GRF_GPIO1A0_SEL_SHIFT = 0,
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GRF_GPIO1A0_SEL_MASK = 0x3fff << GRF_GPIO1A0_SEL_SHIFT,
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GRF_CARD_DATA_CLK_CMD_DETN = 0x1555,
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/* GRF_GPIO2A_IOMUX */
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GRF_GPIO2A0_SEL_SHIFT = 0,
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GRF_GPIO2A0_SEL_MASK = 3 << GRF_GPIO2A0_SEL_SHIFT,
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GRF_UART2_TX_M1 = 1,
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GRF_GPIO2A1_SEL_SHIFT = 2,
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GRF_GPIO2A1_SEL_MASK = 3 << GRF_GPIO2A1_SEL_SHIFT,
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GRF_UART2_RX_M1 = 1,
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GRF_GPIO2A2_SEL_SHIFT = 4,
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GRF_GPIO2A2_SEL_MASK = 3 << GRF_GPIO2A2_SEL_SHIFT,
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GRF_PWM_IR = 1,
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GRF_GPIO2A4_SEL_SHIFT = 8,
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GRF_GPIO2A4_SEL_MASK = 3 << GRF_GPIO2A4_SEL_SHIFT,
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GRF_PWM_0 = 1,
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GRF_I2C1_SDA,
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GRF_GPIO2A5_SEL_SHIFT = 10,
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GRF_GPIO2A5_SEL_MASK = 3 << GRF_GPIO2A5_SEL_SHIFT,
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GRF_PWM_1 = 1,
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GRF_I2C1_SCL,
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GRF_GPIO2A6_SEL_SHIFT = 12,
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GRF_GPIO2A6_SEL_MASK = 3 << GRF_GPIO2A6_SEL_SHIFT,
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GRF_PWM_2 = 1,
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GRF_GPIO2A7_SEL_SHIFT = 14,
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GRF_GPIO2A7_SEL_MASK = 3 << GRF_GPIO2A7_SEL_SHIFT,
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GRF_CARD_PWR_EN_M0 = 1,
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/* GRF_GPIO2BL_IOMUX */
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GRF_GPIO2BL0_SEL_SHIFT = 0,
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GRF_GPIO2BL0_SEL_MASK = 0x3f << GRF_GPIO2BL0_SEL_SHIFT,
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GRF_SPI_CLK_TX_RX_M0 = 0x15,
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GRF_GPIO2BL3_SEL_SHIFT = 6,
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GRF_GPIO2BL3_SEL_MASK = 3 << GRF_GPIO2BL3_SEL_SHIFT,
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GRF_SPI_CSN0_M0 = 1,
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GRF_GPIO2BL4_SEL_SHIFT = 8,
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GRF_GPIO2BL4_SEL_MASK = 3 << GRF_GPIO2BL4_SEL_SHIFT,
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GRF_SPI_CSN1_M0 = 1,
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GRF_GPIO2BL5_SEL_SHIFT = 10,
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GRF_GPIO2BL5_SEL_MASK = 3 << GRF_GPIO2BL5_SEL_SHIFT,
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GRF_I2C2_SDA = 1,
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GRF_GPIO2BL6_SEL_SHIFT = 12,
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GRF_GPIO2BL6_SEL_MASK = 3 << GRF_GPIO2BL6_SEL_SHIFT,
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GRF_I2C2_SCL = 1,
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/* GRF_GPIO2D_IOMUX */
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GRF_GPIO2D0_SEL_SHIFT = 0,
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GRF_GPIO2D0_SEL_MASK = 3 << GRF_GPIO2D0_SEL_SHIFT,
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GRF_I2C0_SCL = 1,
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GRF_GPIO2D1_SEL_SHIFT = 2,
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GRF_GPIO2D1_SEL_MASK = 3 << GRF_GPIO2D1_SEL_SHIFT,
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GRF_I2C0_SDA = 1,
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GRF_GPIO2D4_SEL_SHIFT = 8,
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GRF_GPIO2D4_SEL_MASK = 0xff << GRF_GPIO2D4_SEL_SHIFT,
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GRF_EMMC_DATA123 = 0xaa,
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/* GRF_GPIO3C_IOMUX */
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GRF_GPIO3C0_SEL_SHIFT = 0,
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GRF_GPIO3C0_SEL_MASK = 0x3fff << GRF_GPIO3C0_SEL_SHIFT,
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GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
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/* GRF_COM_IOMUX */
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GRF_UART2_IOMUX_SEL_SHIFT = 0,
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GRF_UART2_IOMUX_SEL_MASK = 3 << GRF_UART2_IOMUX_SEL_SHIFT,
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GRF_UART2_IOMUX_SEL_M0 = 0,
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GRF_UART2_IOMUX_SEL_M1,
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GRF_SPI_IOMUX_SEL_SHIFT = 4,
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GRF_SPI_IOMUX_SEL_MASK = 3 << GRF_SPI_IOMUX_SEL_SHIFT,
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GRF_SPI_IOMUX_SEL_M0 = 0,
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GRF_SPI_IOMUX_SEL_M1,
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GRF_SPI_IOMUX_SEL_M2,
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GRF_CARD_IOMUX_SEL_SHIFT = 7,
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GRF_CARD_IOMUX_SEL_MASK = 1 << GRF_CARD_IOMUX_SEL_SHIFT,
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GRF_CARD_IOMUX_SEL_M0 = 0,
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GRF_CARD_IOMUX_SEL_M1,
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};
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static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
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{
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switch (pwm_id) {
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case PERIPH_ID_PWM0:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A4_SEL_MASK,
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GRF_PWM_0 << GRF_GPIO2A4_SEL_SHIFT);
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break;
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case PERIPH_ID_PWM1:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A5_SEL_MASK,
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GRF_PWM_1 << GRF_GPIO2A5_SEL_SHIFT);
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break;
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case PERIPH_ID_PWM2:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A6_SEL_MASK,
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GRF_PWM_2 << GRF_GPIO2A6_SEL_SHIFT);
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break;
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case PERIPH_ID_PWM3:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A2_SEL_MASK,
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GRF_PWM_IR << GRF_GPIO2A2_SEL_SHIFT);
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break;
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default:
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debug("pwm id = %d iomux error!\n", pwm_id);
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break;
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}
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}
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static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
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{
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switch (i2c_id) {
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case PERIPH_ID_I2C0:
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rk_clrsetreg(&grf->gpio2d_iomux,
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GRF_GPIO2D0_SEL_MASK | GRF_GPIO2D1_SEL_MASK,
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GRF_I2C0_SCL << GRF_GPIO2D0_SEL_SHIFT
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| GRF_I2C0_SDA << GRF_GPIO2D1_SEL_SHIFT);
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break;
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case PERIPH_ID_I2C1:
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A4_SEL_MASK | GRF_GPIO2A5_SEL_MASK,
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GRF_I2C1_SCL << GRF_GPIO2A5_SEL_SHIFT
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| GRF_I2C1_SDA << GRF_GPIO2A4_SEL_SHIFT);
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break;
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case PERIPH_ID_I2C2:
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rk_clrsetreg(&grf->gpio2bl_iomux,
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GRF_GPIO2BL5_SEL_MASK | GRF_GPIO2BL6_SEL_MASK,
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GRF_I2C2_SCL << GRF_GPIO2BL6_SEL_SHIFT
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| GRF_I2C2_SDA << GRF_GPIO2BL6_SEL_SHIFT);
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break;
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case PERIPH_ID_I2C3:
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rk_clrsetreg(&grf->gpio0a_iomux,
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GRF_GPIO0A5_SEL_MASK | GRF_GPIO0A6_SEL_MASK,
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GRF_I2C3_SCL << GRF_GPIO0A5_SEL_SHIFT
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| GRF_I2C3_SDA << GRF_GPIO0A6_SEL_SHIFT);
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break;
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default:
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debug("i2c id = %d iomux error!\n", i2c_id);
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break;
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}
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}
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static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
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{
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switch (lcd_id) {
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case PERIPH_ID_LCDC0:
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break;
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default:
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debug("lcdc id = %d iomux error!\n", lcd_id);
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break;
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}
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}
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static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
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enum periph_id spi_id, int cs)
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{
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rk_clrsetreg(&grf->com_iomux,
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GRF_SPI_IOMUX_SEL_MASK,
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GRF_SPI_IOMUX_SEL_M0 << GRF_SPI_IOMUX_SEL_SHIFT);
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switch (spi_id) {
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case PERIPH_ID_SPI0:
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switch (cs) {
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case 0:
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rk_clrsetreg(&grf->gpio2bl_iomux,
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GRF_GPIO2BL3_SEL_MASK,
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GRF_SPI_CSN0_M0 << GRF_GPIO2BL3_SEL_SHIFT);
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break;
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case 1:
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rk_clrsetreg(&grf->gpio2bl_iomux,
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GRF_GPIO2BL4_SEL_MASK,
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GRF_SPI_CSN1_M0 << GRF_GPIO2BL4_SEL_SHIFT);
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break;
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default:
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goto err;
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}
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rk_clrsetreg(&grf->gpio2bl_iomux,
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GRF_GPIO2BL0_SEL_MASK,
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GRF_SPI_CLK_TX_RX_M0 << GRF_GPIO2BL0_SEL_SHIFT);
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break;
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default:
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goto err;
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}
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return 0;
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err:
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debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
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return -ENOENT;
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}
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static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
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{
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switch (uart_id) {
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case PERIPH_ID_UART2:
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break;
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/* uart2 iomux select m1 */
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rk_clrsetreg(&grf->com_iomux,
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GRF_UART2_IOMUX_SEL_MASK,
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GRF_UART2_IOMUX_SEL_M1
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<< GRF_UART2_IOMUX_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A0_SEL_MASK | GRF_GPIO2A1_SEL_MASK,
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GRF_UART2_TX_M1 << GRF_GPIO2A0_SEL_SHIFT |
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GRF_UART2_RX_M1 << GRF_GPIO2A1_SEL_SHIFT);
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break;
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART3:
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case PERIPH_ID_UART4:
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default:
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debug("uart id = %d iomux error!\n", uart_id);
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break;
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}
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}
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static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
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int mmc_id)
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{
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switch (mmc_id) {
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case PERIPH_ID_EMMC:
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rk_clrsetreg(&grf->gpio0a_iomux,
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GRF_GPIO0A7_SEL_MASK,
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GRF_EMMC_DATA0 << GRF_GPIO0A7_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2d_iomux,
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GRF_GPIO2D4_SEL_MASK,
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GRF_EMMC_DATA123 << GRF_GPIO2D4_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio3c_iomux,
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GRF_GPIO3C0_SEL_MASK,
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GRF_EMMC_DATA567_PWR_CLK_RSTN_CMD
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<< GRF_GPIO3C0_SEL_SHIFT);
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break;
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case PERIPH_ID_SDCARD:
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/* sdcard iomux select m0 */
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rk_clrsetreg(&grf->com_iomux,
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GRF_CARD_IOMUX_SEL_MASK,
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GRF_CARD_IOMUX_SEL_M0 << GRF_CARD_IOMUX_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio2a_iomux,
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GRF_GPIO2A7_SEL_MASK,
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GRF_CARD_PWR_EN_M0 << GRF_GPIO2A7_SEL_SHIFT);
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rk_clrsetreg(&grf->gpio1a_iomux,
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GRF_GPIO1A0_SEL_MASK,
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GRF_CARD_DATA_CLK_CMD_DETN
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<< GRF_GPIO1A0_SEL_SHIFT);
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break;
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default:
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debug("mmc id = %d iomux error!\n", mmc_id);
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break;
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}
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}
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static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
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debug("%s: func=%x, flags=%x\n", __func__, func, flags);
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switch (func) {
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case PERIPH_ID_PWM0:
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case PERIPH_ID_PWM1:
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case PERIPH_ID_PWM2:
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case PERIPH_ID_PWM3:
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pinctrl_rk3328_pwm_config(priv->grf, func);
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break;
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case PERIPH_ID_I2C0:
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case PERIPH_ID_I2C1:
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case PERIPH_ID_I2C2:
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case PERIPH_ID_I2C3:
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pinctrl_rk3328_i2c_config(priv->grf, func);
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break;
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case PERIPH_ID_SPI0:
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pinctrl_rk3328_spi_config(priv->grf, func, flags);
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break;
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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case PERIPH_ID_UART3:
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case PERIPH_ID_UART4:
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pinctrl_rk3328_uart_config(priv->grf, func);
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break;
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case PERIPH_ID_LCDC0:
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case PERIPH_ID_LCDC1:
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pinctrl_rk3328_lcdc_config(priv->grf, func);
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break;
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case PERIPH_ID_SDMMC0:
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case PERIPH_ID_SDMMC1:
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pinctrl_rk3328_sdmmc_config(priv->grf, func);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
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struct udevice *periph)
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{
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u32 cell[3];
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int ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
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"interrupts", cell, ARRAY_SIZE(cell));
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if (ret < 0)
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return -EINVAL;
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switch (cell[1]) {
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case 49:
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return PERIPH_ID_SPI0;
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case 50:
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return PERIPH_ID_PWM0;
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case 36:
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return PERIPH_ID_I2C0;
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case 37: /* Note strange order */
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return PERIPH_ID_I2C1;
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case 38:
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return PERIPH_ID_I2C2;
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case 39:
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return PERIPH_ID_I2C3;
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case 12:
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return PERIPH_ID_SDCARD;
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case 14:
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return PERIPH_ID_EMMC;
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}
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return -ENOENT;
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}
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static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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int func;
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func = rk3328_pinctrl_get_periph_id(dev, periph);
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if (func < 0)
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return func;
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return rk3328_pinctrl_request(dev, func, 0);
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}
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static struct pinctrl_ops rk3328_pinctrl_ops = {
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.set_state_simple = rk3328_pinctrl_set_state_simple,
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.request = rk3328_pinctrl_request,
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.get_periph_id = rk3328_pinctrl_get_periph_id,
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};
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static int rk3328_pinctrl_probe(struct udevice *dev)
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{
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struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
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int ret = 0;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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debug("%s: grf=%p\n", __func__, priv->grf);
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return ret;
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}
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static const struct udevice_id rk3328_pinctrl_ids[] = {
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{ .compatible = "rockchip,rk3328-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3328) = {
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.name = "rockchip_rk3328_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3328_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
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.ops = &rk3328_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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.probe = rk3328_pinctrl_probe,
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};
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