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u-boot/arch/arm/mach-socfpga
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Dinh Nguyen a45526aaa0 arm: socfpga: set the mpuclk divider in the Altera group register 
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.

Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
 		2017-02-08 02:19:11 +01:00
..
include/mach arm: socfpga: set the mpuclk divider in the Altera group register 2017-02-08 02:19:11 +01:00
Kconfig Kconfig: Migrate BOARD_LATE_INIT to a select 2017-01-24 10:35:54 -05:00
Makefile arm: socfpga: remove building scan manager 2015-12-20 03:44:56 +01:00
board.c arm: socfpga: Introduce common board code 2015-12-20 03:36:51 +01:00
clock_manager.c arm: socfpga: set the mpuclk divider in the Altera group register 2017-02-08 02:19:11 +01:00
fpga_manager.c treewide: replace #include <asm/errno.h> with <linux/errno.h> 2016-09-23 17:55:42 -04:00
freeze_controller.c treewide: replace #include <asm/errno.h> with <linux/errno.h> 2016-09-23 17:55:42 -04:00
misc.c Fix spelling of "resetting". 2016-10-31 10:13:17 -04:00
qts-filter.sh qts-filter.sh: strip DOS line endings and handle continuation lines 2016-12-06 01:45:57 +01:00
reset_manager.c arm: socfpga: Assure ISWGRP 0 and 1 are inited 2015-09-04 11:54:20 +02:00
scan_manager.c arm: socfpga: scan: Add code to get FPGA ID 2015-08-08 14:14:30 +02:00
spl.c common: Pass the boot device into spl_boot_mode() 2016-06-26 20:17:22 +02:00
system_manager.c arm: socfpga: Make the pinmux table const u8 2015-08-23 11:56:20 +02:00
timer.c ARM: socfpga: move SoC sources to mach-socfpga 2015-05-07 05:21:12 +02:00
wrap_iocsr_config.c arm: socfpga: Switch to filtered QTS files 2015-08-23 11:56:20 +02:00
wrap_pinmux_config.c arm: socfpga: Make the pinmux table const u8 2015-08-23 11:56:20 +02:00
wrap_pll_config.c arm: socfpga: set the mpuclk divider in the Altera group register 2017-02-08 02:19:11 +01:00
wrap_sdram_config.c ddr: altera: Configuring SDRAM extra cycles timing parameters 2016-10-27 08:03:07 +02:00