415 lines
9.5 KiB
C
415 lines
9.5 KiB
C
/*
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* board.c
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*
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* Board functions for TI AM43XX based boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/errno.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/emif.h>
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#include "board.h"
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#include <miiphy.h>
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#include <cpsw.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_DRIVER_TI_CPSW
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#endif
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(struct am43xx_board_id *header)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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printf("Could not probe the EEPROM at 0x%x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
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sizeof(struct am43xx_board_id))) {
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printf("Could not read the EEPROM\n");
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return -EIO;
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}
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if (header->magic != 0xEE3355AA) {
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/*
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* read the eeprom using i2c again,
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* but use only a 1 byte address
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*/
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(struct am43xx_board_id))) {
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printf("Could not read the EEPROM at 0x%x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return -EIO;
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}
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if (header->magic != 0xEE3355AA) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header->magic);
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return -EINVAL;
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}
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}
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strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
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am43xx_board_name[sizeof(header->name)] = 0;
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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const struct dpll_params epos_evm_dpll_ddr = {
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266, 24, 1, -1, 1, -1, -1};
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const struct dpll_params epos_evm_dpll_mpu = {
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600, 24, 1, -1, -1, -1, -1};
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const struct dpll_params epos_evm_dpll_core = {
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1000, 24, -1, -1, 10, 8, 4};
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const struct dpll_params epos_evm_dpll_per = {
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960, 24, 5, -1, -1, -1, -1};
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const struct dpll_params gp_evm_dpll_ddr = {
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400, 23, 1, -1, 1, -1, -1};
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const struct dpll_params gp_evm_dpll_mpu = {
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600, 23, 1, -1, -1, -1, -1};
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const struct dpll_params gp_evm_dpll_core = {
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1000, 23, -1, -1, 10, 8, 4};
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const struct dpll_params gp_evm_dpll_per = {
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960, 23, 5, -1, -1, -1, -1};
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const struct ctrl_ioregs ioregs_lpddr2 = {
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.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x1,
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};
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const struct emif_regs emif_regs_lpddr2 = {
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.sdram_config = 0x808012BA,
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.ref_ctrl = 0x0000040D,
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.sdram_tim1 = 0xEA86B411,
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.sdram_tim2 = 0x103A094A,
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.sdram_tim3 = 0x0F6BA37F,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_rd_wr_lvl_rmp_win = 0x0,
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.emif_rd_wr_lvl_rmp_ctl = 0x0,
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.emif_rd_wr_lvl_ctl = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E084006,
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.emif_rd_wr_exec_thresh = 0x00000405,
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.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
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.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_3 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_4 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_5 = 0x00500050
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};
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/* TODO: Reconcile with OMAP5/DRA7xx changes */
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#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
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const u32 ext_phy_ctrl_const_base_lpddr2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x00500050,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x40001000,
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0x08102040
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};
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x0143,
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};
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const struct emif_regs ddr3_emif_regs_400Mhz = {
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.sdram_config = 0x638413B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0xEAAAD4DB,
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.sdram_tim2 = 0x266B7FDA,
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.sdram_tim3 = 0x107F8678,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E004008,
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_4 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_5 = 0x00400040,
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.emif_rd_wr_exec_thresh = 0x00000405
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};
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const u32 ext_phy_ctrl_const_base_ddr3[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x00400040,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x0,
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0x0,
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0x40000000,
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0x08102040
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};
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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if (board_is_eposevm())
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return &epos_evm_dpll_ddr;
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else
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return &gp_evm_dpll_ddr;
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}
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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if (board_is_eposevm())
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return &epos_evm_dpll_mpu;
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else
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return &gp_evm_dpll_mpu;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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struct am43xx_board_id header;
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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if (board_is_eposevm())
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return &epos_evm_dpll_core;
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else
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return &gp_evm_dpll_core;
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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if (board_is_eposevm())
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return &epos_evm_dpll_per;
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else
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return &gp_evm_dpll_per;
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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static void enable_vtt_regulator(void)
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{
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u32 temp;
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/*GPIO_VTTEN - GPIO5_7 PINMUX Setup*/
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writel(0x7, CTRL_BASE + 0x0A5C);
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writel(0x102, PRCM_BASE + 0x8C98);
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/* Poll if module is functional */
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while ((readl(PRCM_BASE + 0x8C98) & 0x30000) != 0x0)
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;
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/* enable module */
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writel(0x0, GPIO5_BASE + 0x0130);
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/*enable output for GPIO5_7*/
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writel((1 << 7), GPIO5_BASE + 0x0194);
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temp = readl(GPIO5_BASE + 0x0134);
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temp = temp & ~(1 << 7);
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writel(temp, GPIO5_BASE + 0x0134);
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}
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void sdram_init(void)
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{
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if (board_is_eposevm()) {
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do_sdram_init(&ioregs_lpddr2, &emif_regs_lpddr2,
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ext_phy_ctrl_const_base_lpddr2,
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EMIF_SDRAM_TYPE_LPDDR2);
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} else {
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enable_vtt_regulator();
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do_sdram_init(&ioregs_ddr3, &ddr3_emif_regs_400Mhz,
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ext_phy_ctrl_const_base_ddr3,
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EMIF_SDRAM_TYPE_DDR3);
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}
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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char safe_string[HDR_NAME_LEN + 1];
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struct am43xx_board_id header;
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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/* Now set variables based on the header. */
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strncpy(safe_string, (char *)header.name, sizeof(header.name));
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safe_string[sizeof(header.name)] = 0;
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setenv("board_name", safe_string);
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strncpy(safe_string, (char *)header.version, sizeof(header.version));
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safe_string[sizeof(header.version)] = 0;
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setenv("board_rev", safe_string);
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* Additional controls can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 16,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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int rv;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (!getenv("ethaddr")) {
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puts("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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}
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mac_lo = readl(&cdev->macid1l);
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mac_hi = readl(&cdev->macid1h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (!getenv("eth1addr")) {
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("eth1addr", mac_addr);
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}
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if (board_is_eposevm()) {
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writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
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cpsw_slaves[0].phy_addr = 16;
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} else {
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writel(RGMII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII;
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cpsw_slaves[0].phy_addr = 0;
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}
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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return rv;
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}
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#endif
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