Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This patch
- Adds pin-mux for x8 parallel NAND device (MT29F4G08AB) present on AM43xx_EVM
- As above NAND device has blocksize=256k, pagesize=4k, oobsize=224, so by
design ROM code expects SPL to be flashed using BCH16 ECC scheme. Hence
CONFIG_NAND_OMAP_ECCSCHEME = OMAP_ECC_BCH16_CODE_HW is enabled.
- Specifies MTD partition table which needs same as kernel DTS for AM43xx_EVM.
- Populates other CONFIG_xx parameters required for NAND Boot on AM43xx
Signed-off-by: Pekon Gupta <pekon@ti.com>
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the
read latency expected will be CL+3 as per tests from HW folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team to
come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adding support for CPSW to AM43xx EPOS nad GP EVM which is connected
to RMII and RGMII phy respectively and enable cpsw in config.
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adding DPLLs Multiplier and DIvider values for GP EVM
Following are the DPLL locking frequencies at OPP NOM
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 400MHz
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
Following are the DPLL locking frequencies at OPP NOM:
MPU locks at 600MHz
Core locks at 1000MHz
Per locks at 960MHz
DDR locks at 266MHz
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support for reading onboard EEPROM to enable
board detection.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Sourav Poddar
Dave Gerlach
Lokesh Vutla
Pekon Gupta
Mugunthan V N
Tom Rini
Sekhar Nori