Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	configs/ls1046aqds_defconfig
	configs/ls1046aqds_nand_defconfig
	configs/ls1046aqds_qspi_defconfig
	configs/ls1046aqds_sdcard_ifc_defconfig
	configs/ls1046aqds_sdcard_qspi_defconfig
	configs/ls1046ardb_emmc_defconfig
	configs/ls1046ardb_qspi_defconfig
	configs/ls1046ardb_sdcard_defconfig

README

@@ -504,6 +504,12 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_IFC_LE
 		Defines the IFC controller register space as Little Endian
 
+		CONFIG_SYS_FSL_IFC_CLK_DIV
+		Defines divider of platform clock(clock input to IFC controller).
+
+		CONFIG_SYS_FSL_LBC_CLK_DIV
+		Defines divider of platform clock(clock input to eLBC controller).
+
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details

arch/arm/cpu/armv7/ls102xa/clock.c

@@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-	u32 ccr;
-#endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[6] = {
@@ -74,10 +70,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
-	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus;
 #endif
 }
 

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -34,6 +34,7 @@ config ARCH_LS1046A
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A009801
 	select SYS_FSL_ERRATUM_A009803

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -22,10 +22,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-	u32 ccr;
-#endif
 #if (defined(CONFIG_FSL_ESDHC) &&\
 	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
 	defined(CONFIG_SYS_DPAA_FMAN)
@@ -156,10 +152,8 @@ void get_sys_info(struct sys_info *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

@@ -26,10 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-	u32 ccr;
-#endif
 	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
 		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
 		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
@@ -128,10 +124,8 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 

arch/arm/dts/fsl-ls1046a.dtsi

@@ -217,6 +217,27 @@
 			status = "disabled";
 		};
 
+		usb0: usb@2f00000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x2f00000 0x0 0x10000>;
+			interrupts = <0 60 4>;
+			dr_mode = "host";
+		};
+
+		usb1: usb@3000000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3000000 0x0 0x10000>;
+			interrupts = <0 61 4>;
+			dr_mode = "host";
+		};
+
+		usb2: usb@3100000 {
+			compatible = "fsl,layerscape-dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 63 4>;
+			dr_mode = "host";
+		};
+
 		pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -192,6 +192,9 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -374,6 +374,7 @@ config ARCH_B4420
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config ARCH_B4860
 	bool
@@ -398,6 +399,7 @@ config ARCH_B4860
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config ARCH_BSC9131
 	bool
@@ -410,6 +412,7 @@ config ARCH_BSC9131
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select FSL_IFC
 
 config ARCH_BSC9132
 	bool
@@ -426,6 +429,7 @@ config ARCH_BSC9132
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_IFC
 
 config ARCH_C29X
 	bool
@@ -438,6 +442,7 @@ config ARCH_C29X
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_6
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_IFC
 
 config ARCH_MPC8536
 	bool
@@ -450,6 +455,7 @@ config ARCH_MPC8536
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_MPC8540
 	bool
@@ -473,6 +479,7 @@ config ARCH_MPC8544
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_MPC8548
 	bool
@@ -519,6 +526,7 @@ config ARCH_MPC8569
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
+	select FSL_ELBC
 
 config ARCH_MPC8572
 	bool
@@ -533,6 +541,7 @@ config ARCH_MPC8572
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1010
 	bool
@@ -553,6 +562,7 @@ config ARCH_P1010
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_IFC
 
 config ARCH_P1011
 	bool
@@ -566,6 +576,7 @@ config ARCH_P1011
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1020
 	bool
@@ -579,6 +590,7 @@ config ARCH_P1020
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1021
 	bool
@@ -592,6 +604,7 @@ config ARCH_P1021
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1022
 	bool
@@ -607,6 +620,7 @@ config ARCH_P1022
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1023
 	bool
@@ -618,6 +632,7 @@ config ARCH_P1023
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select FSL_ELBC
 
 config ARCH_P1024
 	bool
@@ -631,6 +646,7 @@ config ARCH_P1024
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P1025
 	bool
@@ -644,6 +660,7 @@ config ARCH_P1025
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P2020
 	bool
@@ -658,6 +675,7 @@ config ARCH_P2020
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
 	select SYS_PPC_E500_USE_DEBUG_TLB
+	select FSL_ELBC
 
 config ARCH_P2041
 	bool
@@ -679,6 +697,7 @@ config ARCH_P2041
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select FSL_ELBC
 
 config ARCH_P3041
 	bool
@@ -702,6 +721,7 @@ config ARCH_P3041
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select FSL_ELBC
 
 config ARCH_P4080
 	bool
@@ -736,6 +756,7 @@ config ARCH_P4080
 	select SYS_FSL_QORIQ_CHASSIS1
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
+	select FSL_ELBC
 
 config ARCH_P5020
 	bool
@@ -756,6 +777,7 @@ config ARCH_P5020
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_ELBC
 
 config ARCH_P5040
 	bool
@@ -776,6 +798,7 @@ config ARCH_P5040
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_ELBC
 
 config ARCH_QEMU_E500
 	bool
@@ -795,6 +818,7 @@ config ARCH_T1023
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select FSL_IFC
 
 config ARCH_T1024
 	bool
@@ -811,6 +835,7 @@ config ARCH_T1024
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select FSL_IFC
 
 config ARCH_T1040
 	bool
@@ -828,6 +853,7 @@ config ARCH_T1040
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select FSL_IFC
 
 config ARCH_T1042
 	bool
@@ -845,6 +871,7 @@ config ARCH_T1042
 	select SYS_FSL_QORIQ_CHASSIS2
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
+	select FSL_IFC
 
 config ARCH_T2080
 	bool
@@ -866,6 +893,7 @@ config ARCH_T2080
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config ARCH_T2081
 	bool
@@ -885,6 +913,7 @@ config ARCH_T2081
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config ARCH_T4160
 	bool
@@ -905,6 +934,7 @@ config ARCH_T4160
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config ARCH_T4240
 	bool
@@ -928,6 +958,7 @@ config ARCH_T4240
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_PPC64
+	select FSL_IFC
 
 config BOOKE
 	bool
@@ -1260,6 +1291,12 @@ config SYS_PPC64
 config SYS_PPC_E500_USE_DEBUG_TLB
 	bool
 
+config FSL_IFC
+	bool
+
+config FSL_ELBC
+	bool
+
 config SYS_PPC_E500_DEBUG_TLB
 	int "Temporary TLB entry for external debugger"
 	depends on SYS_PPC_E500_USE_DEBUG_TLB
@@ -1284,6 +1321,40 @@ config SYS_PPC_E500_DEBUG_TLB
                 symbol should be set to the TLB1 entry to be used for this
                 purpose. If unsure, do not change.
 
+config SYS_FSL_IFC_CLK_DIV
+	int "Divider of platform clock"
+	depends on FSL_IFC
+	default 2 if	ARCH_B4420	|| \
+			ARCH_B4860	|| \
+			ARCH_T1024	|| \
+			ARCH_T1023	|| \
+			ARCH_T1040	|| \
+			ARCH_T1042	|| \
+			ARCH_T4160	|| \
+			ARCH_T4240
+	default 1
+	help
+		Defines divider of platform clock(clock input to
+		IFC controller).
+
+config SYS_FSL_LBC_CLK_DIV
+	int "Divider of platform clock"
+	depends on FSL_ELBC || ARCH_MPC8540 || \
+		ARCH_MPC8548 || ARCH_MPC8541 || \
+		ARCH_MPC8555 || ARCH_MPC8560 || \
+		ARCH_MPC8568
+
+	default 2 if	ARCH_P2041	|| \
+			ARCH_P3041	|| \
+			ARCH_P4080	|| \
+			ARCH_P5020	|| \
+			ARCH_P5040
+	default 1
+
+	help
+		Defines divider of platform clock(clock input to
+		eLBC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"

arch/powerpc/cpu/mpc85xx/speed.c

@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-	u32 ccr;
-#endif
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -611,39 +607,13 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-	/* We will program LCRR to this value later */
-	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-		/* If this is corenet based SoC, bit-representation
-		 * for four times the clock divider values.
-		 */
-		lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-	!defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
-		/*
-		 * Yes, the entire PQ38 family use the same
-		 * bit-representation for twice the clock divider values.
-		 */
-		lcrr_div *= 2;
-#endif
-		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-	} else {
-		/* In case anyone cares what the unknown value is */
-		sys_info->freq_localbus = lcrr_div;
-	}
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }
 

arch/powerpc/cpu/mpc86xx/speed.c

@@ -24,7 +24,6 @@ void get_sys_info(sys_info_t *sys_info)
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint plat_ratio, e600_ratio;
-	uint lcrr_div;
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
@@ -78,19 +77,7 @@ void get_sys_info(sys_info_t *sys_info)
 		break;
 	}
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-	/* We will program LCRR to this value later */
-	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-	lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
-#endif
-	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-		sys_info->freq_localbus = sys_info->freq_systembus
-							/ (lcrr_div * 2);
-	} else {
-		/* In case anyone cares what the unknown value is */
-		sys_info->freq_localbus = lcrr_div;
-	}
+	sys_info->freq_localbus = sys_info->freq_systembus;
 }
 
 

board/freescale/ls1012afrdm/ls1012afrdm.c

@@ -9,6 +9,9 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <environment.h>
@@ -74,6 +77,9 @@ int board_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 	return 0;
 }
 
@@ -85,3 +91,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
+
+void dram_init_banksize(void)
+{
+	/*
+	 * gd->arch.secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+			gd->arch.secure_ram -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+			gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	}
+}

board/freescale/ls1012aqds/ls1012aqds.c

@@ -10,6 +10,9 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
 #include <asm/arch/fdt.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
@@ -113,6 +116,10 @@ int board_init(void)
 #ifdef CONFIG_ENV_IS_NOWHERE
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
+
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 	return 0;
 }
 
@@ -159,3 +166,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 	return 0;
 }
 #endif
+
+void dram_init_banksize(void)
+{
+	/*
+	 * gd->arch.secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+			gd->arch.secure_ram -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+			gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	}
+}

board/freescale/ls1012ardb/ls1012ardb.c

@@ -9,6 +9,9 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_LS_PPA
+#include <asm/arch/ppa.h>
+#endif
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <ahci.h>
@@ -110,6 +113,9 @@ int board_init(void)
 	gd->env_addr = (ulong)&default_environment[0];
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init();
+#endif
 	return 0;
 }
 
@@ -159,3 +165,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
+
+void dram_init_banksize(void)
+{
+	/*
+	 * gd->secure_ram tracks the location of secure memory.
+	 * It was set as if the memory starts from 0.
+	 * The address needs to add the offset of its bank.
+	 */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+			gd->arch.secure_ram -
+			CONFIG_SYS_DDR_BLOCK1_SIZE;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+			gd->arch.secure_ram;
+		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+	}
+}

board/freescale/ls1021aqds/ddr.c

@@ -96,6 +96,9 @@ found:
 #else
 	popts->cswl_override = DDR_CSWL_CS0;
 
+	/* optimize cpo for erratum A-009942 */
+	popts->cpo_sample = 0x58;
+
 	/* DHC_EN =1, ODT = 75 Ohm */
 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);

configs/ls1012afrdm_qspi_defconfig

@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"

configs/ls1012aqds_qspi_defconfig

@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"

configs/ls1012ardb_qspi_defconfig

@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"

configs/ls1046aqds_defconfig

@@ -32,3 +32,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046aqds_lpuart_defconfig

@@ -28,3 +28,5 @@ CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046aqds_nand_defconfig

@@ -37,3 +37,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046aqds_qspi_defconfig

@@ -35,3 +35,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046aqds_sdcard_ifc_defconfig

@@ -38,3 +38,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046aqds_sdcard_qspi_defconfig

@@ -40,3 +40,5 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046ardb_emmc_defconfig

@@ -35,3 +35,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046ardb_qspi_defconfig

@@ -31,3 +31,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

configs/ls1046ardb_sdcard_defconfig

@@ -35,3 +35,5 @@ CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y

drivers/net/fsl-mc/mc.c

@@ -8,6 +8,7 @@
 #include <linux/bug.h>
 #include <asm/io.h>
 #include <libfdt.h>
+#include <net.h>
 #include <fdt_support.h>
 #include <fsl-mc/fsl_mc.h>
 #include <fsl-mc/fsl_mc_sys.h>
@@ -195,10 +196,81 @@ static int calculate_mc_private_ram_params(u64 mc_private_ram_start_addr,
 	return 0;
 }
 
+static int mc_fixup_dpc_mac_addr(void *blob, int noff, int dpmac_id,
+		struct eth_device *eth_dev)
+{
+	int nodeoffset, err = 0;
+	char mac_name[10];
+	const char link_type_mode[] = "FIXED_LINK";
+	unsigned char env_enetaddr[6];
+
+	sprintf(mac_name, "mac@%d", dpmac_id);
+
+	/* node not found - create it */
+	nodeoffset = fdt_subnode_offset(blob, noff, (const char *) mac_name);
+	if (nodeoffset < 0) {
+		err = fdt_increase_size(blob, 200);
+		if (err) {
+			printf("fdt_increase_size: err=%s\n",
+				fdt_strerror(err));
+			return err;
+		}
+
+		nodeoffset = fdt_add_subnode(blob, noff, mac_name);
+
+		/* add default property of fixed link */
+		err = fdt_appendprop_string(blob, nodeoffset,
+					    "link_type", link_type_mode);
+		if (err) {
+			printf("fdt_appendprop_string: err=%s\n",
+				fdt_strerror(err));
+			return err;
+		}
+	}
+
+	/* port_mac_address property present in DPC */
+	if (fdt_get_property(blob, nodeoffset, "port_mac_address", NULL)) {
+		/* MAC addr randomly assigned - leave the one in DPC */
+		eth_getenv_enetaddr_by_index("eth", eth_dev->index,
+						env_enetaddr);
+		if (is_zero_ethaddr(env_enetaddr))
+			return err;
+
+		/* replace DPC MAC address with u-boot env one */
+		err = fdt_setprop(blob, nodeoffset, "port_mac_address",
+				  eth_dev->enetaddr, 6);
+		if (err) {
+			printf("fdt_setprop mac: err=%s\n", fdt_strerror(err));
+			return err;
+		}
+
+		return 0;
+	}
+
+	/* append port_mac_address property to mac node in DPC */
+	err = fdt_increase_size(blob, 80);
+	if (err) {
+		printf("fdt_increase_size: err=%s\n", fdt_strerror(err));
+		return err;
+	}
+
+	err = fdt_appendprop(blob, nodeoffset,
+			     "port_mac_address", eth_dev->enetaddr, 6);
+	if (err) {
+		printf("fdt_appendprop: err=%s\n", fdt_strerror(err));
+		return err;
+	}
+
+	return err;
+}
+
 static int mc_fixup_dpc(u64 dpc_addr)
 {
 	void *blob = (void *)dpc_addr;
-	int nodeoffset;
+	int nodeoffset, err = 0;
+	char ethname[10];
+	struct eth_device *eth_dev;
+	int i;
 
 	/* delete any existing ICID pools */
 	nodeoffset = fdt_path_offset(blob, "/resources/icid_pools");
@@ -220,9 +292,36 @@ static int mc_fixup_dpc(u64 dpc_addr)
 			     FSL_DPAA2_STREAM_ID_END -
 			     FSL_DPAA2_STREAM_ID_START + 1, 1);
 
+	/* fixup MAC addresses for dpmac ports */
+	nodeoffset = fdt_path_offset(blob, "/board_info/ports");
+	if (nodeoffset < 0)
+		goto out;
+
+	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+		/* port not enabled */
+		if ((wriop_is_enabled_dpmac(i) != 1) ||
+		    (wriop_get_phy_address(i) == -1))
+			continue;
+
+		sprintf(ethname, "DPMAC%d@%s", i,
+			phy_interface_strings[wriop_get_enet_if(i)]);
+
+		eth_dev = eth_get_dev_by_name(ethname);
+		if (eth_dev == NULL)
+			continue;
+
+		err = mc_fixup_dpc_mac_addr(blob, nodeoffset, i, eth_dev);
+		if (err) {
+			printf("mc_fixup_dpc_mac_addr failed: err=%s\n",
+			fdt_strerror(err));
+			goto out;
+		}
+	}
+
+out:
 	flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
 
-	return 0;
+	return err;
 }
 
 static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr)

include/configs/B4860QDS.h

@@ -63,7 +63,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */

include/configs/BSC9131RDB.h

@@ -46,7 +46,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 
 #define CONFIG_TSEC_ENET

include/configs/BSC9132QDS.h

@@ -68,7 +68,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 

include/configs/C29XPCIE.h

@@ -68,7 +68,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 

include/configs/MPC8536DS.h

@@ -37,7 +37,6 @@
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
 
-#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */

include/configs/MPC8569MDS.h

@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
-
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 

include/configs/MPC8572DS.h

@@ -28,7 +28,6 @@
 /* High Level Configuration Options */
 #define CONFIG_MP		1	/* support multiple processors */
 
-#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */

include/configs/P1010RDB.h

@@ -130,7 +130,6 @@
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
 

include/configs/P1022DS.h

@@ -96,7 +96,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif
 
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2			/* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3			/* PCIE controller 3 (ULI bridge) */

include/configs/P1023RDB.h

@@ -25,7 +25,6 @@
 /* High Level Configuration Options */
 #define CONFIG_MP		/* support multiple processors */
 
-#define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2		/* PCIE controller 2 (slot 2) */

include/configs/P2041RDB.h

@@ -41,7 +41,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */

include/configs/T102xQDS.h

@@ -23,7 +23,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 
 #define CONFIG_ENV_OVERWRITE
 

include/configs/T102xRDB.h

@@ -23,7 +23,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 
 #define CONFIG_ENV_OVERWRITE
 

include/configs/T1040QDS.h

@@ -51,7 +51,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controller 1 */

include/configs/T104xRDB.h

@@ -162,7 +162,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCIE1			/* PCIE controller 1 */

include/configs/T208xQDS.h

@@ -33,7 +33,6 @@
 
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC		/* Enable IFC Support */
 #define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
 #define CONFIG_ENV_OVERWRITE
 

include/configs/T208xRDB.h

@@ -27,7 +27,6 @@
 
 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC		/* Enable IFC Support */
 #define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
 #define CONFIG_ENV_OVERWRITE
 

include/configs/T4240RDB.h

@@ -73,7 +73,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */

include/configs/UCP1020.h

@@ -14,7 +14,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */

include/configs/controlcenterd.h

@@ -137,7 +137,6 @@
 /*
  * Local Bus Definitions
  */
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 
 #define CONFIG_SYS_ELBC_BASE		0xe0000000
 #ifdef CONFIG_PHYS_64BIT

include/configs/corenet_ds.h

@@ -59,7 +59,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */

include/configs/cyrus.h

@@ -49,7 +49,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */

include/configs/km/kmp204x-common.h

@@ -35,7 +35,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */

include/configs/ls1012a_common.h

@@ -29,6 +29,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ/4	/* 25MHz */

include/configs/ls1046aqds.h

@@ -135,6 +135,18 @@ unsigned long get_board_ddr_clk(void);
 #define CFG_LPUART_EN		0x2
 #endif
 
+/* USB */
+#define CONFIG_HAS_FSL_XHCI_USB
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_HCD
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         3
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI

include/configs/p1_p2_rdb_pc.h

@@ -260,7 +260,6 @@
 
 #define CONFIG_MP
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */

include/configs/p1_twr.h

@@ -40,7 +40,6 @@
 
 #define CONFIG_MP
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */

include/configs/t4qds.h

@@ -26,7 +26,6 @@
 
 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_IFC			/* Enable IFC Support */
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */

include/configs/xpedite537x.h

@@ -29,7 +29,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
-#define CONFIG_FSL_ELBC		1
 
 /*
  * Multicore config

include/configs/xpedite550x.h

@@ -30,7 +30,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
-#define CONFIG_FSL_ELBC		1
 
 /*
  * Multicore config