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Merge git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Tom Rini 2017-02-01 16:34:36 -05:00
parent 43ade93bdb de8c9317a8
commit 0ff27d4a94
5 changed files with 38 additions and 17 deletions
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3
arch/powerpc/cpu/mpc83xx/cpu_init.c
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@ -205,8 +205,7 @@ void cpu_init_f (volatile immap_t * im)
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
/* global data region was cleared in start.S */
/* system performance tweaking */
clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);

6
arch/powerpc/cpu/mpc83xx/spl_minimal.c
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@ -18,14 +18,10 @@ DECLARE_GLOBAL_DATA_PTR;
*/
void cpu_init_f (volatile immap_t * im)
{
int i;
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
/* global data region was cleared in start.S */
/* system performance tweaking */

36
arch/powerpc/cpu/mpc83xx/start.S
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@ -258,14 +258,40 @@ in_flash:
#endif
/* set up the stack pointer in our newly created
* cache-ram (r1) */
lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
* cache-ram; use r3 to keep the new SP for now to
* avoid overiding the SP it uselessly */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
/* r4 = end of GD area */
addi r4, r3, GENERATED_GBL_DATA_SIZE
/* Zero GD area */
li r0, 0
1:
subi r4, r4, 1
stb r0, 0(r4)
cmplw r3, r4
bne 1b
#ifdef CONFIG_SYS_MALLOC_F_LEN
#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
#endif
/* r3 = new stack pointer / pre-reloc malloc area */
subi r3, r3, CONFIG_SYS_MALLOC_F_LEN
/* Set pointer to pre-reloc malloc area in GD */
stw r3, GD_MALLOC_BASE(r4)
#endif
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
stwu r0, -4(r3) /* clear final stack frame so that */
stwu r0, -4(r3) /* stack backtraces terminate cleanly */
/* Finally, actually set SP */
mr r1, r3
/* let the C-code set up the rest */
/* */

8
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -1373,8 +1373,8 @@ icache_enable:
mtlr r8
isync
mfspr r4,L1CSR1
ori r4,r4,0x0001
oris r4,r4,0x0001
ori r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@l
oris r4,r4,(L1CSR1_CPE | L1CSR1_ICE)@h
mtspr L1CSR1,r4
isync
blr
@ -1402,8 +1402,8 @@ dcache_enable:
mtlr r8
isync
mfspr r0,L1CSR0
ori r0,r0,0x0001
oris r0,r0,0x0001
ori r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@l
oris r0,r0,(L1CSR0_CPE | L1CSR0_DCE)@h
msync
isync
mtspr L1CSR0,r0

2
arch/powerpc/lib/memcpy_mpc5200.c
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@ -31,7 +31,7 @@ void *memcpy(void *trg, const void *src, size_t len)
extern void* __memcpy(void *, const void *, size_t);
char *s = (char *)src;
char *t = (char *)trg;
void *dest = (void *)src;
void *dest = (void *)trg;
/*
* Check is source address is in flash: