zynq: Add clk framework support to zynq timer
If available use the clock framework to calculate the clock rate of the zynq timer. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -1,4 +1,7 @@
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/*
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/*
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* Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
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* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
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*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
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*
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*
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@ -25,8 +28,10 @@
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* SPDX-License-Identifier: GPL-2.0+
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* SPDX-License-Identifier: GPL-2.0+
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*/
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*/
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#include <clk.h>
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#include <common.h>
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#include <common.h>
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#include <div64.h>
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#include <div64.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/clk.h>
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@ -56,6 +61,26 @@ int timer_init(void)
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(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
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(TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
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SCUTIMER_CONTROL_ENABLE_MASK;
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SCUTIMER_CONTROL_ENABLE_MASK;
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#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK)
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(zynq_clk), &dev);
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if (ret)
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return ret;
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clk.id = cpu_6or4x_clk;
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ret = clk_request(dev, &clk);
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if (ret < 0)
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return ret;
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gd->cpu_clk = clk_get_rate(&clk);
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clk_free(&clk);
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#endif
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gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
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gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
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/* Load the timer counter register */
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/* Load the timer counter register */
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