imx: ventana: add additional DRAM configurations
- 64bit 8gB density (4GiB) IMX6DQ - 64bit 4gB density (2GiB) IMX6SDL Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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@ -355,6 +355,25 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
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.p1_mpwrdlctl = 0X40304239,
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.p1_mpwrdlctl = 0X40304239,
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};
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};
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static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x0048004A,
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.p0_mpwldectrl1 = 0x003F004A,
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.p1_mpwldectrl0 = 0x001E0028,
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.p1_mpwldectrl1 = 0x002C0043,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x02250219,
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.p0_mpdgctrl1 = 0x01790202,
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.p1_mpdgctrl0 = 0x02080208,
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.p1_mpdgctrl1 = 0x016C0175,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x4A4C4D4C,
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.p1_mprddlctl = 0x494C4A48,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x403F3437,
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.p1_mpwrdlctl = 0x383A3930,
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};
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static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
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static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
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/* write leveling calibration determine */
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x002A0025,
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.p0_mpwldectrl0 = 0x002A0025,
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@ -368,6 +387,25 @@ static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
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.p0_mpwrdlctl = 0x303E3C36,
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.p0_mpwrdlctl = 0x303E3C36,
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};
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};
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static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = {
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/* write leveling calibration determine */
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.p0_mpwldectrl0 = 0x00230020,
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.p0_mpwldectrl1 = 0x002F002A,
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.p1_mpwldectrl0 = 0x001D0027,
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.p1_mpwldectrl1 = 0x00100023,
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/* Read DQS Gating calibration */
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.p0_mpdgctrl0 = 0x03250339,
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.p0_mpdgctrl1 = 0x031C0316,
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.p1_mpdgctrl0 = 0x03210331,
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.p1_mpdgctrl1 = 0x031C025A,
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/* Read Calibration: DQS delay relative to DQ read access */
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.p0_mprddlctl = 0x40373C40,
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.p1_mprddlctl = 0x3A373646,
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/* Write Calibration: DQ/DM delay relative to DQS write access */
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.p0_mpwrdlctl = 0x2E353933,
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.p1_mpwrdlctl = 0x3C2F3F35,
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};
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static void spl_dram_init(int width, int size_mb, int board_model)
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static void spl_dram_init(int width, int size_mb, int board_model)
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{
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{
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struct mx6_ddr3_cfg *mem = NULL;
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struct mx6_ddr3_cfg *mem = NULL;
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@ -468,7 +506,14 @@ static void spl_dram_init(int width, int size_mb, int board_model)
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mem = &mt41k256m16ha_125;
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mem = &mt41k256m16ha_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_256x64_mmdc_calib;
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calib = &mx6dq_256x64_mmdc_calib;
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else
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calib = &mx6sdl_256x64_mmdc_calib;
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debug("4gB density\n");
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debug("4gB density\n");
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} else if (width == 64 && size_mb == 4096) {
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mem = &mt41k512m16ha_125;
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if (is_cpu_type(MXC_CPU_MX6Q))
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calib = &mx6dq_512x64_mmdc_calib;
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debug("8gB density\n");
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}
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}
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if (!(mem && calib)) {
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if (!(mem && calib)) {
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