rockchip: rk3328: add soc basic support
RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
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@ -38,6 +38,16 @@ config ROCKCHIP_RK3288
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and video codec support. Peripherals include Gigabit Ethernet,
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3328
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bool "Support Rockchip RK3328"
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select ARM64
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help
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The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3399
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config ROCKCHIP_RK3399
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bool "Support Rockchip RK3399"
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bool "Support Rockchip RK3399"
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select ARM64
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select ARM64
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@ -70,5 +80,6 @@ config SPL_MMC_SUPPORT
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source "arch/arm/mach-rockchip/rk3036/Kconfig"
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source "arch/arm/mach-rockchip/rk3036/Kconfig"
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source "arch/arm/mach-rockchip/rk3188/Kconfig"
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source "arch/arm/mach-rockchip/rk3188/Kconfig"
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source "arch/arm/mach-rockchip/rk3288/Kconfig"
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source "arch/arm/mach-rockchip/rk3288/Kconfig"
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source "arch/arm/mach-rockchip/rk3328/Kconfig"
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source "arch/arm/mach-rockchip/rk3399/Kconfig"
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source "arch/arm/mach-rockchip/rk3399/Kconfig"
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endif
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endif
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@ -28,4 +28,5 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
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endif
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endif
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obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
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obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
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obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
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obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
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obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
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@ -0,0 +1,8 @@
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#
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# (C) Copyright 2016 Rockchip Electronics Co., Ltd
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += rk3328.o
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obj-y += syscon_rk3328.o
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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static struct mm_region rk3328_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xf0000000UL,
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.phys = 0xf0000000UL,
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3328_mem_map;
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int arch_cpu_init(void)
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{
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/* We do some SoC one time setting here. */
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return 0;
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}
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@ -0,0 +1,20 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <dm.h>
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#include <syscon.h>
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static const struct udevice_id rk3328_syscon_ids[] = {
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{ .compatible = "rockchip,rk3328-grf", .data = ROCKCHIP_SYSCON_GRF },
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};
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U_BOOT_DRIVER(syscon_rk3328) = {
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.name = "rk3328_syscon",
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.id = UCLASS_SYSCON,
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.of_match = rk3328_syscon_ids,
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};
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@ -0,0 +1,65 @@
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/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3328_COMMON_H
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#define __CONFIG_RK3328_COMMON_H
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#include "rockchip-common.h"
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_BAUDRATE 1500000
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SYS_TEXT_BASE 0x00200000
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#define CONFIG_SYS_INIT_SP_ADDR 0x00300000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
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/* MMC/SD IP block */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_FS_FAT
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#define CONFIG_FAT_WRITE
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#define CONFIG_FS_EXT4
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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/* FAT sd card locations. */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00500000\0" \
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"pxefile_addr_r=0x00600000\0" \
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"fdt_addr_r=0x01f00000\0" \
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"kernel_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x04000000\0"
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#include <config_distro_bootcmd.h>
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#define CONFIG_EXTRA_ENV_SETTINGS \
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ENV_MEM_LAYOUT_SETTINGS \
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"partitions=" PARTS_DEFAULT \
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BOOTENV
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#endif
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#endif
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