i.MX6UL: isiot: Add eMMC boot support
Boot from eMMC: -------------- U-Boot SPL 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27) Trying to boot from MMC2 U-Boot 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 36C Reset cause: POR Model: Engicam Is.IoT MX6UL eMMC Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
parent
cde5aa3761
commit
7cf22dc8d8
|
@ -317,6 +317,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
|
||||||
imx6q-icore-rqs.dtb \
|
imx6q-icore-rqs.dtb \
|
||||||
imx6sx-sabreauto.dtb \
|
imx6sx-sabreauto.dtb \
|
||||||
imx6ul-geam-kit.dtb \
|
imx6ul-geam-kit.dtb \
|
||||||
|
imx6ul-isiot-emmc.dtb \
|
||||||
imx6ul-isiot-mmc.dtb \
|
imx6ul-isiot-mmc.dtb \
|
||||||
imx6ul-isiot-nand.dtb
|
imx6ul-isiot-nand.dtb
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,77 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Amarula Solutions B.V.
|
||||||
|
* Copyright (C) 2016 Engicam S.r.l.
|
||||||
|
*
|
||||||
|
* This file is dual-licensed: you can use it either under the terms
|
||||||
|
* of the GPL or the X11 license, at your option. Note that this dual
|
||||||
|
* licensing only applies to this file, and not this project as a
|
||||||
|
* whole.
|
||||||
|
*
|
||||||
|
* a) This file is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License
|
||||||
|
* version 2 as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This file is distributed in the hope that it will be useful
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* Or, alternatively
|
||||||
|
*
|
||||||
|
* b) Permission is hereby granted, free of charge, to any person
|
||||||
|
* obtaining a copy of this software and associated documentation
|
||||||
|
* files (the "Software"), to deal in the Software without
|
||||||
|
* restriction, including without limitation the rights to use
|
||||||
|
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||||
|
* sell copies of the Software, and to permit persons to whom the
|
||||||
|
* Software is furnished to do so, subject to the following
|
||||||
|
* conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be
|
||||||
|
* included in all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||||
|
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||||
|
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||||
|
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||||
|
* OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "imx6ul-isiot.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Engicam Is.IoT MX6UL eMMC Starterkit";
|
||||||
|
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usdhc2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||||
|
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
|
||||||
|
bus-width = <8>;
|
||||||
|
no-1-8-v;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&iomuxc {
|
||||||
|
pinctrl_usdhc2: usdhc2grp {
|
||||||
|
fsl,pins = <
|
||||||
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
|
||||||
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
|
||||||
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
|
||||||
|
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
|
||||||
|
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -4,7 +4,9 @@ S: Maintained
|
||||||
F: board/engicam/isiotmx6ul
|
F: board/engicam/isiotmx6ul
|
||||||
F: include/configs/imx6ul_isiot.h
|
F: include/configs/imx6ul_isiot.h
|
||||||
F: configs/imx6ul_isiot_mmc_defconfig
|
F: configs/imx6ul_isiot_mmc_defconfig
|
||||||
|
F: configs/imx6ul_isiot_emmc_defconfig
|
||||||
F: configs/imx6ul_isiot_nand_defconfig
|
F: configs/imx6ul_isiot_nand_defconfig
|
||||||
F: arch/arm/dts/imx6ul-isiot.dtsi
|
F: arch/arm/dts/imx6ul-isiot.dtsi
|
||||||
F: arch/arm/dts/imx6ul-isiot-mmc.dts
|
F: arch/arm/dts/imx6ul-isiot-mmc.dts
|
||||||
|
F: arch/arm/dts/imx6ul-isiot-emmc.dts
|
||||||
F: arch/arm/dts/imx6ul-isiot-nand.dts
|
F: arch/arm/dts/imx6ul-isiot-nand.dts
|
||||||
|
|
|
@ -153,10 +153,24 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||||
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||||
};
|
};
|
||||||
|
|
||||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
|
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
||||||
|
MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||||
|
};
|
||||||
|
|
||||||
struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
|
||||||
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
|
||||||
|
|
||||||
|
struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||||
{USDHC1_BASE_ADDR, 0, 4},
|
{USDHC1_BASE_ADDR, 0, 4},
|
||||||
|
{USDHC2_BASE_ADDR, 0, 8},
|
||||||
};
|
};
|
||||||
|
|
||||||
int board_mmc_getcd(struct mmc *mmc)
|
int board_mmc_getcd(struct mmc *mmc)
|
||||||
|
@ -168,6 +182,9 @@ int board_mmc_getcd(struct mmc *mmc)
|
||||||
case USDHC1_BASE_ADDR:
|
case USDHC1_BASE_ADDR:
|
||||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||||
break;
|
break;
|
||||||
|
case USDHC2_BASE_ADDR:
|
||||||
|
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
|
@ -181,6 +198,7 @@ int board_mmc_init(bd_t *bis)
|
||||||
* According to the board_mmc_init() the following map is done:
|
* According to the board_mmc_init() the following map is done:
|
||||||
* (U-boot device node) (Physical Port)
|
* (U-boot device node) (Physical Port)
|
||||||
* mmc0 USDHC1
|
* mmc0 USDHC1
|
||||||
|
* mmc1 USDHC2
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||||
switch (i) {
|
switch (i) {
|
||||||
|
@ -190,6 +208,12 @@ int board_mmc_init(bd_t *bis)
|
||||||
gpio_direction_input(USDHC1_CD_GPIO);
|
gpio_direction_input(USDHC1_CD_GPIO);
|
||||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||||
break;
|
break;
|
||||||
|
case 1:
|
||||||
|
imx_iomux_v3_setup_multiple_pads(
|
||||||
|
usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
|
||||||
|
gpio_direction_input(USDHC2_CD_GPIO);
|
||||||
|
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
printf("Warning - USDHC%d controller not supporting\n",
|
printf("Warning - USDHC%d controller not supporting\n",
|
||||||
i + 1);
|
i + 1);
|
||||||
|
|
|
@ -0,0 +1,39 @@
|
||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_MX6=y
|
||||||
|
CONFIG_SPL_GPIO_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||||
|
CONFIG_TARGET_MX6UL_ISIOT=y
|
||||||
|
CONFIG_SPL_EXT_SUPPORT=y
|
||||||
|
CONFIG_SPL_LIBDISK_SUPPORT=y
|
||||||
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||||
|
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||||
|
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
|
||||||
|
CONFIG_BOOTDELAY=3
|
||||||
|
CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_HUSH_PARSER=y
|
||||||
|
CONFIG_FIT=y
|
||||||
|
CONFIG_FIT_VERBOSE=y
|
||||||
|
CONFIG_FIT_SIGNATURE=y
|
||||||
|
CONFIG_SYS_PROMPT="isiotmx6ul> "
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
CONFIG_CMD_MEMTEST=y
|
||||||
|
CONFIG_CMD_MMC=y
|
||||||
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_MII=y
|
||||||
|
CONFIG_CMD_PING=y
|
||||||
|
CONFIG_CMD_CACHE=y
|
||||||
|
CONFIG_CMD_EXT2=y
|
||||||
|
CONFIG_CMD_EXT4=y
|
||||||
|
CONFIG_CMD_EXT4_WRITE=y
|
||||||
|
CONFIG_CMD_FAT=y
|
||||||
|
CONFIG_CMD_FS_GENERIC=y
|
||||||
|
# CONFIG_BLK is not set
|
||||||
|
# CONFIG_DM_MMC_OPS is not set
|
||||||
|
CONFIG_FEC_MXC=y
|
||||||
|
CONFIG_PINCTRL=y
|
||||||
|
CONFIG_PINCTRL_IMX6=y
|
||||||
|
CONFIG_MXC_UART=y
|
||||||
|
CONFIG_IMX_THERMAL=y
|
|
@ -145,7 +145,7 @@
|
||||||
/* MMC */
|
/* MMC */
|
||||||
#ifdef CONFIG_FSL_USDHC
|
#ifdef CONFIG_FSL_USDHC
|
||||||
# define CONFIG_SYS_MMC_ENV_DEV 0
|
# define CONFIG_SYS_MMC_ENV_DEV 0
|
||||||
# define CONFIG_SYS_FSL_USDHC_NUM 1
|
# define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||||
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
# define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue