i.MX6UL: isiot: Add eMMC boot support
Boot from eMMC: -------------- U-Boot SPL 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27) Trying to boot from MMC2 U-Boot 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 36C Reset cause: POR Model: Engicam Is.IoT MX6UL eMMC Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
Stefano Babic
parent
cde5aa3761
commit
7cf22dc8d8
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@ -317,6 +317,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6q-icore-rqs.dtb \
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imx6sx-sabreauto.dtb \
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imx6ul-geam-kit.dtb \
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imx6ul-isiot-emmc.dtb \
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imx6ul-isiot-mmc.dtb \
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imx6ul-isiot-nand.dtb
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@ -0,0 +1,77 @@
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/*
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* Copyright (C) 2016 Amarula Solutions B.V.
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* Copyright (C) 2016 Engicam S.r.l.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "imx6ul-isiot.dtsi"
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/ {
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model = "Engicam Is.IoT MX6UL eMMC Starterkit";
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compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
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bus-width = <8>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc {
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
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MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
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>;
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};
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};
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@ -4,7 +4,9 @@ S: Maintained
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F: board/engicam/isiotmx6ul
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F: include/configs/imx6ul_isiot.h
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F: configs/imx6ul_isiot_mmc_defconfig
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F: configs/imx6ul_isiot_emmc_defconfig
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F: configs/imx6ul_isiot_nand_defconfig
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F: arch/arm/dts/imx6ul-isiot.dtsi
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F: arch/arm/dts/imx6ul-isiot-mmc.dts
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F: arch/arm/dts/imx6ul-isiot-emmc.dts
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F: arch/arm/dts/imx6ul-isiot-nand.dts
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@ -153,10 +153,24 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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struct fsl_esdhc_cfg usdhc_cfg[1] = {
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#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
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#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
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struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC1_BASE_ADDR, 0, 4},
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{USDHC2_BASE_ADDR, 0, 8},
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};
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int board_mmc_getcd(struct mmc *mmc)
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@ -168,6 +182,9 @@ int board_mmc_getcd(struct mmc *mmc)
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case USDHC1_BASE_ADDR:
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ret = !gpio_get_value(USDHC1_CD_GPIO);
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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break;
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}
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return ret;
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@ -181,6 +198,7 @@ int board_mmc_init(bd_t *bis)
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* According to the board_mmc_init() the following map is done:
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* (U-boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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@ -190,6 +208,12 @@ int board_mmc_init(bd_t *bis)
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gpio_direction_input(USDHC1_CD_GPIO);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(
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usdhc1_pads, ARRAY_SIZE(usdhc2_pads));
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gpio_direction_input(USDHC2_CD_GPIO);
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usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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break;
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default:
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printf("Warning - USDHC%d controller not supporting\n",
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i + 1);
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@ -0,0 +1,39 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX6=y
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CONFIG_SPL_GPIO_SUPPORT=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_TARGET_MX6UL_ISIOT=y
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CONFIG_SPL_EXT_SUPPORT=y
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CONFIG_SPL_LIBDISK_SUPPORT=y
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
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CONFIG_BOOTDELAY=3
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CONFIG_DEFAULT_FDT_FILE="imx6ul-isiot-emmc.dtb"
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CONFIG_SPL=y
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CONFIG_HUSH_PARSER=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_SYS_PROMPT="isiotmx6ul> "
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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# CONFIG_BLK is not set
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# CONFIG_DM_MMC_OPS is not set
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CONFIG_FEC_MXC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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CONFIG_MXC_UART=y
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CONFIG_IMX_THERMAL=y
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@ -145,7 +145,7 @@
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/* MMC */
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#ifdef CONFIG_FSL_USDHC
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# define CONFIG_SYS_MMC_ENV_DEV 0
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# define CONFIG_SYS_FSL_USDHC_NUM 1
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# define CONFIG_SYS_FSL_USDHC_NUM 2
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# define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#endif
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