x86: Intel MID platforms has no microcode update
There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
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if (!stack)
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if (!stack)
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return -ENOMEM;
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return -ENOMEM;
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params->stack_top = (u32)(stack + size);
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params->stack_top = (u32)(stack + size);
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#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
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#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
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!defined(CONFIG_INTEL_MID)
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params->microcode_ptr = ucode_base;
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params->microcode_ptr = ucode_base;
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debug("Microcode at %x\n", params->microcode_ptr);
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debug("Microcode at %x\n", params->microcode_ptr);
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#endif
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#endif
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