bind: port a patch to fix a build failure
(From OE-Core rev: 2cc9106da45a14d41a5269d91d7f79b6ccd8597f) Signed-off-by: Roy Li <rongqing.li@windriver.com> Signed-off-by: Saul Wold <sgw@linux.intel.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
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bind: port a patch to fix a build failure
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mips1 does not support ll and sc instructions, and lead to below error, now
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we port a patch from debian to fix it
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[http://security.debian.org/debian-security/pool/updates/main/b/bind9/bind9_9.8.4.dfsg.P1-6+nmu2+deb7u1.diff.gz]
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| {standard input}: Assembler messages:
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| {standard input}:47: Error: Opcode not supported on this processor: mips1 (mips1) `ll $3,0($6)'
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| {standard input}:50: Error: Opcode not supported on this processor: mips1 (mips1) `sc $3,0($6)'
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Upstream-Status: Pending
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Signed-off-by: Roy Li <rongqing.li@windriver.com>
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--- bind9-9.8.4.dfsg.P1.orig/lib/isc/mips/include/isc/atomic.h
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+++ bind9-9.8.4.dfsg.P1/lib/isc/mips/include/isc/atomic.h
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@@ -31,18 +31,20 @@
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isc_atomic_xadd(isc_int32_t *p, int val) {
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isc_int32_t orig;
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- /* add is a cheat, since MIPS has no mov instruction */
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- __asm__ volatile (
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- "1:"
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- "ll $3, %1\n"
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- "add %0, $0, $3\n"
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- "add $3, $3, %2\n"
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- "sc $3, %1\n"
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- "beq $3, 0, 1b"
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- : "=&r"(orig)
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- : "m"(*p), "r"(val)
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- : "memory", "$3"
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- );
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+ __asm__ __volatile__ (
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+ " .set push \n"
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+ " .set mips2 \n"
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+ " .set noreorder \n"
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+ " .set noat \n"
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+ "1: ll $1, %1 \n"
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+ " addu %0, $1, %2 \n"
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+ " sc %0, %1 \n"
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+ " beqz %0, 1b \n"
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+ " move %0, $1 \n"
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+ " .set pop \n"
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+ : "=&r" (orig), "+R" (*p)
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+ : "r" (val)
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+ : "memory");
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return (orig);
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}
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@@ -52,16 +54,7 @@
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*/
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static inline void
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isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
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- __asm__ volatile (
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- "1:"
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- "ll $3, %0\n"
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- "add $3, $0, %1\n"
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- "sc $3, %0\n"
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- "beq $3, 0, 1b"
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- :
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- : "m"(*p), "r"(val)
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- : "memory", "$3"
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- );
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+ *p = val;
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}
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/*
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@@ -72,20 +65,23 @@
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static inline isc_int32_t
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isc_atomic_cmpxchg(isc_int32_t *p, int cmpval, int val) {
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isc_int32_t orig;
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+ isc_int32_t tmp;
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- __asm__ volatile(
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- "1:"
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- "ll $3, %1\n"
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- "add %0, $0, $3\n"
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- "bne $3, %2, 2f\n"
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- "add $3, $0, %3\n"
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- "sc $3, %1\n"
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- "beq $3, 0, 1b\n"
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- "2:"
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- : "=&r"(orig)
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- : "m"(*p), "r"(cmpval), "r"(val)
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- : "memory", "$3"
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- );
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+ __asm__ __volatile__ (
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+ " .set push \n"
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+ " .set mips2 \n"
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+ " .set noreorder \n"
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+ " .set noat \n"
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+ "1: ll $1, %1 \n"
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+ " bne $1, %3, 2f \n"
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+ " move %2, %4 \n"
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+ " sc %2, %1 \n"
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+ " beqz %2, 1b \n"
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+ "2: move %0, $1 \n"
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+ " .set pop \n"
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+ : "=&r"(orig), "+R" (*p), "=r" (tmp)
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+ : "r"(cmpval), "r"(val)
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+ : "memory");
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return (orig);
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}
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@ -18,6 +18,7 @@ SRC_URI = "ftp://ftp.isc.org/isc/bind9/${PV}/${BPN}-${PV}.tar.gz \
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file://bind-CVE-2012-3817.patch \
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file://bind-CVE-2013-2266.patch \
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file://bind-Fix-CVE-2012-4244.patch \
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file://mips1-not-support-opcode.diff \
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"
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SRC_URI[md5sum] = "cf31117c5d35af34d4c0702970ad9fb7"
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