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Author | SHA1 | Date |
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Holger Hans Peter Freyther | ae76afe1cd |
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@ -57,6 +57,28 @@ typedef enum SuperFemto_PrimId_t
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SuperFemto_PrimId_NUM
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SuperFemto_PrimId_NUM
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} SuperFemto_PrimId_t;
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} SuperFemto_PrimId_t;
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/****************************************************************************
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* Enum : SuperFemto_ClkSrcId_t
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************************************************************************//**
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*
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* Clock source intifiers.
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*
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* @ingroup superfemto_api
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*
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****************************************************************************/
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typedef enum SuperFemto_ClkSrcId_t
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{
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// RF Diagnostic Primitives
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SuperFemto_ClkSrcId_None = 0, ///< None
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SuperFemto_ClkSrcId_Ocxo, ///< Optional on-board OCXO
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SuperFemto_ClkSrcId_Tcxo, ///< Optional on-board TCXO
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SuperFemto_ClkSrcId_External, ///< Multi-Trx external clock
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SuperFemto_ClkSrcId_GpsPps, ///< GPS PPS
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SuperFemto_ClkSrcId_Trx, ///< TRX clock
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SuperFemto_ClkSrcId_Rx, ///< RX clock
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SuperFemto_ClkSrcId_NetList, ///< Network listening
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SuperFemto_ClkSrcId_Edge, ///< Debug edge connector clock,
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} SuperFemto_ClkSrcId_t;
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/****************************************************************************
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/****************************************************************************
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* Types *
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* Types *
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@ -71,6 +93,7 @@ typedef enum SuperFemto_PrimId_t
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* @ingroup superfemto_api_prim_sys
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* @ingroup superfemto_api_prim_sys
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*
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*
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****************************************************************************/
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****************************************************************************/
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#define FEMTOBTS_NO_BOARD_VERSION
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typedef struct SuperFemto_SystemInfoCnf
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typedef struct SuperFemto_SystemInfoCnf
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{
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{
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SuperFemto_Status_t status; ///< Status
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SuperFemto_Status_t status; ///< Status
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@ -148,14 +171,14 @@ typedef struct SuperFemto_ActivateRfReq
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struct
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struct
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{
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{
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int iClkCor; ///< Clock correction value in PPB.
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int iClkCor; ///< Clock correction value in PPB.
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uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX)
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uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX)
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} rfTrx;
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} rfTrx;
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// RX RF clock options
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// RX RF clock options
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struct
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struct
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{
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{
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int iClkCor; ///< Clock calibration value in PPB.
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int iClkCor; ///< Clock calibration value in PPB.
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uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved)
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uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved)
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} rfRx;
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} rfRx;
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} SuperFemto_ActivateRfReq_t;
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} SuperFemto_ActivateRfReq_t;
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@ -281,19 +304,19 @@ typedef struct SuperFemto_RfClockSetupReq
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struct
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struct
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{
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{
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int iClkCor; ///< Clock correction value in PPB.
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int iClkCor; ///< Clock correction value in PPB.
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uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX)
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uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:RX)
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} rfTrx;
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} rfTrx;
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// RX RF clock options
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// RX RF clock options
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struct
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struct
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{
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{
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int iClkCor; ///< Clock calibration value in PPB.
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int iClkCor; ///< Clock calibration value in PPB.
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uint8_t u8ClkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved)
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uint8_t clkSrc; ///< Clock source (0:None, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:TRX, 6:reserved)
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} rfRx;
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} rfRx;
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// RF clock calibration
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// RF clock calibration
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struct {
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struct {
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uint8_t u8ClkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:NL)
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uint8_t clkSrc; ///< Reference clock source (0:Off, 1:OCXO, 2:TCXO, 3:External, 4:GPS PPS, 5:reserved, 6:reserved, 7:NL)
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} rfTrxClkCal;
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} rfTrxClkCal;
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} SuperFemto_RfClockSetupReq_t;
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} SuperFemto_RfClockSetupReq_t;
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