Merge branch 'for-next/dts'
This commit is contained in:
commit
ca7a800c1f
|
@ -38,9 +38,6 @@
|
|||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx51-babbage {
|
||||
pinctrl_fec: fecgrp {
|
||||
/*
|
||||
|
|
|
@ -1,20 +1,21 @@
|
|||
Power Management Service Unit(PMSU)
|
||||
-----------------------------------
|
||||
Available on Marvell SOCs: Armada 370 and Armada XP
|
||||
Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,armada-370-xp-pmsu"
|
||||
- compatible: should be one of:
|
||||
- "marvell,armada-370-pmsu" for Armada 370 or Armada XP
|
||||
- "marvell,armada-380-pmsu" for Armada 38x
|
||||
- "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now
|
||||
deprecated and will be removed
|
||||
|
||||
- reg: Should contain PMSU registers location and length. First pair
|
||||
for the per-CPU SW Reset Control registers, second pair for the
|
||||
Power Management Service Unit.
|
||||
- reg: Should contain PMSU registers location and length.
|
||||
|
||||
Example:
|
||||
|
||||
armada-370-xp-pmsu@d0022000 {
|
||||
compatible = "marvell,armada-370-xp-pmsu";
|
||||
reg = <0xd0022100 0x430>,
|
||||
<0xd0020800 0x20>;
|
||||
armada-370-xp-pmsu@22000 {
|
||||
compatible = "marvell,armada-370-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
|
|
|
@ -0,0 +1,14 @@
|
|||
Marvell Armada CPU reset controller
|
||||
===================================
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "marvell,armada-370-cpu-reset".
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet for the CPU reset registers
|
||||
|
||||
cpurst: cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x20>;
|
||||
};
|
|
@ -0,0 +1,12 @@
|
|||
Axxia AXM55xx device tree bindings
|
||||
|
||||
Boards using the AXM55xx SoC need to have the following properties:
|
||||
|
||||
Required root node property:
|
||||
|
||||
- compatible = "lsi,axm5516"
|
||||
|
||||
Boards:
|
||||
|
||||
LSI AXM5516 Validation board (Amarillo)
|
||||
compatible = "lsi,axm5516-amarillo", "lsi,axm5516"
|
|
@ -1,16 +1,33 @@
|
|||
Coherency fabric
|
||||
----------------
|
||||
Available on Marvell SOCs: Armada 370 and Armada XP
|
||||
Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "marvell,coherency-fabric"
|
||||
- compatible: the possible values are:
|
||||
|
||||
* "marvell,coherency-fabric", to be used for the coherency fabric of
|
||||
the Armada 370 and Armada XP.
|
||||
|
||||
* "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
|
||||
fabric.
|
||||
|
||||
* "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
|
||||
fabric.
|
||||
|
||||
- reg: Should contain coherency fabric registers location and
|
||||
length. First pair for the coherency fabric registers, second pair
|
||||
for the per-CPU fabric registers registers.
|
||||
length.
|
||||
|
||||
Example:
|
||||
* For "marvell,coherency-fabric", the first pair for the coherency
|
||||
fabric registers, second pair for the per-CPU fabric registers.
|
||||
|
||||
* For "marvell,armada-375-coherency-fabric", only one pair is needed
|
||||
for the per-CPU fabric registers.
|
||||
|
||||
* For "marvell,armada-380-coherency-fabric", only one pair is needed
|
||||
for the per-CPU fabric registers.
|
||||
|
||||
Examples:
|
||||
|
||||
coherency-fabric@d0020200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
|
@ -19,3 +36,8 @@ coherency-fabric@d0020200 {
|
|||
|
||||
};
|
||||
|
||||
coherency-fabric@21810 {
|
||||
compatible = "marvell,armada-375-coherency-fabric";
|
||||
reg = <0x21810 0x1c>;
|
||||
};
|
||||
|
||||
|
|
|
@ -178,13 +178,19 @@ nodes to be present and contain the properties described below.
|
|||
Usage and definition depend on ARM architecture version.
|
||||
# On ARM v8 64-bit this property is required and must
|
||||
be one of:
|
||||
"spin-table"
|
||||
"psci"
|
||||
"spin-table"
|
||||
# On ARM 32-bit systems this property is optional and
|
||||
can be one of:
|
||||
"allwinner,sun6i-a31"
|
||||
"arm,psci"
|
||||
"marvell,armada-375-smp"
|
||||
"marvell,armada-380-smp"
|
||||
"marvell,armada-xp-smp"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,kpss-acc-v1"
|
||||
"qcom,kpss-acc-v2"
|
||||
"rockchip,rk3066-smp"
|
||||
|
||||
- cpu-release-addr
|
||||
Usage: required for systems that have an "enable-method"
|
||||
|
|
|
@ -0,0 +1,38 @@
|
|||
Samsung Exynos SYSRAM for SMP bringup:
|
||||
------------------------------------
|
||||
|
||||
Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
|
||||
of the secondary cores. Once the core gets powered up it executes the
|
||||
code that is residing at some specific location of the SYSRAM.
|
||||
|
||||
Therefore reserved section sub-nodes have to be added to the mmio-sram
|
||||
declaration. These nodes are of two types depending upon secure or
|
||||
non-secure execution environment.
|
||||
|
||||
Required sub-node properties:
|
||||
- compatible : depending upon boot mode, should be
|
||||
"samsung,exynos4210-sysram" : for Secure SYSRAM
|
||||
"samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
|
||||
|
||||
The rest of the properties should follow the generic mmio-sram discription
|
||||
found in ../../misc/sysram.txt
|
||||
|
||||
Example:
|
||||
|
||||
sysram@02020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x02020000 0x54000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x02020000 0x54000>;
|
||||
|
||||
smp-sysram@0 {
|
||||
compatible = "samsung,exynos4210-sysram";
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
smp-sysram@53000 {
|
||||
compatible = "samsung,exynos4210-sysram-ns";
|
||||
reg = <0x53000 0x1000>;
|
||||
};
|
||||
};
|
|
@ -4,8 +4,11 @@
|
|||
|
||||
** Timer node required properties:
|
||||
|
||||
- compatible : Should be "arm,cortex-a9-global-timer"
|
||||
Driver supports versions r2p0 and above.
|
||||
- compatible : should contain
|
||||
* "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
|
||||
* "arm,cortex-a9-global-timer" for Cortex-A9 global
|
||||
timers or any compatible implementation. Note: driver
|
||||
supports versions r2p0 and above.
|
||||
|
||||
- interrupts : One interrupt to each core
|
||||
|
||||
|
|
|
@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are:
|
|||
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
|
||||
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
|
||||
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
|
||||
"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
|
||||
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
|
||||
|
||||
* Example:
|
||||
|
@ -22,3 +23,104 @@ SoC and board used. Currently known SoC compatibles are:
|
|||
|
||||
...
|
||||
}
|
||||
|
||||
* Marvell Berlin2 chip control binding
|
||||
|
||||
Marvell Berlin SoCs have a chip control register set providing several
|
||||
individual registers dealing with pinmux, padmux, clock, reset, and secondary
|
||||
CPU boot address. Unfortunately, the individual registers are spread among the
|
||||
chip control registers, so there should be a single DT node only providing the
|
||||
different functions which are described below.
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of
|
||||
"marvell,berlin2-chip-ctrl" for BG2
|
||||
"marvell,berlin2cd-chip-ctrl" for BG2CD
|
||||
"marvell,berlin2q-chip-ctrl" for BG2Q
|
||||
- reg: address and length of following register sets for
|
||||
BG2/BG2CD: chip control register set
|
||||
BG2Q: chip control register set and cpu pll registers
|
||||
|
||||
* Marvell Berlin2 system control binding
|
||||
|
||||
Marvell Berlin SoCs have a system control register set providing several
|
||||
individual registers dealing with pinmux, padmux, and reset.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
"marvell,berlin2-system-ctrl" for BG2
|
||||
"marvell,berlin2cd-system-ctrl" for BG2CD
|
||||
"marvell,berlin2q-system-ctrl" for BG2Q
|
||||
- reg: address and length of the system control register set
|
||||
|
||||
* Clock provider binding
|
||||
|
||||
As clock related registers are spread among the chip control registers, the
|
||||
chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
|
||||
SoCs share the same IP for PLLs and clocks, with some minor differences in
|
||||
features and register layout.
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: shall be set to 1
|
||||
- clocks: clock specifiers referencing the core clock input clocks
|
||||
- clock-names: array of strings describing the input clock specifiers above.
|
||||
Allowed clock-names for the reference clocks are
|
||||
"refclk" for the SoCs osciallator input on all SoCs,
|
||||
and SoC-specific input clocks for
|
||||
BG2/BG2CD: "video_ext0" for the external video clock input
|
||||
|
||||
Clocks provided by core clocks shall be referenced by a clock specifier
|
||||
indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
|
||||
for the corresponding index mapping.
|
||||
|
||||
* Pin controller binding
|
||||
|
||||
Pin control registers are part of both register sets, chip control and system
|
||||
control. The pins controlled are organized in groups, so no actual pin
|
||||
information is needed.
|
||||
|
||||
A pin-controller node should contain subnodes representing the pin group
|
||||
configurations, one per function. Each subnode has the group name and the muxing
|
||||
function used.
|
||||
|
||||
Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
|
||||
a 'function' in the pin-controller subsystem.
|
||||
|
||||
Required subnode-properties:
|
||||
- groups: a list of strings describing the group names.
|
||||
- function: a string describing the function used to mux the groups.
|
||||
|
||||
Example:
|
||||
|
||||
chip: chip-control@ea0000 {
|
||||
compatible = "marvell,berlin2-chip-ctrl";
|
||||
#clock-cells = <1>;
|
||||
reg = <0xea0000 0x400>;
|
||||
clocks = <&refclk>, <&externaldev 0>;
|
||||
clock-names = "refclk", "video_ext0";
|
||||
|
||||
spi1_pmux: spi1-pmux {
|
||||
groups = "G0";
|
||||
function = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
sysctrl: system-controller@d000 {
|
||||
compatible = "marvell,berlin2-system-ctrl";
|
||||
reg = <0xd000 0x100>;
|
||||
|
||||
uart0_pmux: uart0-pmux {
|
||||
groups = "GSM4";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
uart1_pmux: uart1-pmux {
|
||||
groups = "GSM5";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
uart2_pmux: uart2-pmux {
|
||||
groups = "GSM3";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -6,6 +6,8 @@ provided by Arteris.
|
|||
Required properties:
|
||||
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
|
||||
Should be "ti,omap4-l3-noc" for OMAP4 family
|
||||
Should be "ti,dra7-l3-noc" for DRA7 family
|
||||
Should be "ti,am4372-l3-noc" for AM43 family
|
||||
- reg: Contains L3 register address range for each noc domain.
|
||||
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
|
||||
|
||||
|
|
|
@ -80,7 +80,10 @@ SoCs:
|
|||
compatible = "ti,omap5432", "ti,omap5"
|
||||
|
||||
- DRA742
|
||||
compatible = "ti,dra7xx", "ti,dra7"
|
||||
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA722
|
||||
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- AM4372
|
||||
compatible = "ti,am4372", "ti,am43"
|
||||
|
@ -102,6 +105,12 @@ Boards:
|
|||
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
|
||||
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
|
||||
|
||||
- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
|
||||
compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
|
||||
|
||||
- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
|
||||
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
|
||||
|
||||
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
|
||||
compatible = "ti,omap3-evm", "ti,omap3"
|
||||
|
||||
|
@ -120,5 +129,8 @@ Boards:
|
|||
- AM437x GP EVM
|
||||
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- DRA7 EVM: Software Developement Board for DRA7XX
|
||||
compatible = "ti,dra7-evm", "ti,dra7"
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA722 EVM: Software Development Board for DRA722
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
|
|
@ -8,6 +8,7 @@ Required properties:
|
|||
|
||||
- compatible : should be one of
|
||||
"arm,armv8-pmuv3"
|
||||
"arm,cortex-a17-pmu"
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a12-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
|
|
|
@ -21,7 +21,15 @@ to #0.
|
|||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : Must be "arm,psci"
|
||||
- compatible : should contain at least one of:
|
||||
|
||||
* "arm,psci" : for implementations complying to PSCI versions prior to
|
||||
0.2. For these cases function IDs must be provided.
|
||||
|
||||
* "arm,psci-0.2" : for implementations complying to PSCI 0.2. Function
|
||||
IDs are not required and should be ignored by an OS with PSCI 0.2
|
||||
support, but are permitted to be present for compatibility with
|
||||
existing software when "arm,psci" is later in the compatible list.
|
||||
|
||||
- method : The method of calling the PSCI firmware. Permitted
|
||||
values are:
|
||||
|
@ -45,6 +53,8 @@ Main node optional properties:
|
|||
|
||||
Example:
|
||||
|
||||
Case 1: PSCI v0.1 only.
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
|
@ -53,3 +63,28 @@ Example:
|
|||
cpu_on = <0x95c10002>;
|
||||
migrate = <0x95c10003>;
|
||||
};
|
||||
|
||||
|
||||
Case 2: PSCI v0.2 only
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
Case 3: PSCI v0.2 and PSCI v0.1.
|
||||
|
||||
A DTB may provide IDs for use by kernels without PSCI 0.2 support,
|
||||
enabling firmware and hypervisors to support existing and new kernels.
|
||||
These IDs will be ignored by kernels with PSCI 0.2 support, which will
|
||||
use the standard PSCI 0.2 IDs exclusively.
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
method = "hvc";
|
||||
|
||||
cpu_on = < arbitrary value >;
|
||||
cpu_off = < arbitrary value >;
|
||||
|
||||
...
|
||||
};
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
Rockchip platforms device tree bindings
|
||||
---------------------------------------
|
||||
|
||||
- bq Curie 2 tablet:
|
||||
Required root node properties:
|
||||
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
|
||||
|
||||
- Radxa Rock board:
|
||||
Required root node properties:
|
||||
- compatible = "radxa,rock", "rockchip,rk3188";
|
|
@ -2,6 +2,10 @@ SAMSUNG Exynos SoC series PMU Registers
|
|||
|
||||
Properties:
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
|
||||
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
|
||||
- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
|
||||
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
|
||||
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
|
||||
- "samsung,exynos5420-pmu" - for Exynos5420 SoC.
|
||||
second value must be always "syscon".
|
||||
|
|
|
@ -1,8 +1,10 @@
|
|||
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
Properties:
|
||||
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
|
||||
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
|
||||
- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
Example:
|
||||
|
@ -10,3 +12,8 @@ Example:
|
|||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,15 @@
|
|||
ST STi Platforms Device Tree Bindings
|
||||
---------------------------------------
|
||||
|
||||
Boards with the ST STiH415 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih415";
|
||||
|
||||
Boards with the ST STiH416 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih416";
|
||||
|
||||
Boards with the ST STiH407 SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible = "st,stih407";
|
||||
|
|
@ -8,6 +8,8 @@ interrupt generation, MMC and NOR Flash control etc.
|
|||
Required node properties:
|
||||
- compatible value : = "arm,vexpress,sysreg";
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Deprecated properties, replaced by GPIO subnodes (see below):
|
||||
- gpio-controller : specifies that the node is a GPIO controller
|
||||
- #gpio-cells : size of the GPIO specifier, should be 2:
|
||||
- first cell is the pseudo-GPIO line number:
|
||||
|
@ -16,35 +18,86 @@ Required node properties:
|
|||
2 - NOR FLASH WPn
|
||||
- second cell can take standard GPIO flags (currently ignored).
|
||||
|
||||
Control registers providing pseudo-GPIO lines must be represented
|
||||
by subnodes, each of them requiring the following properties:
|
||||
- compatible value : one of
|
||||
"arm,vexpress-sysreg,sys_led"
|
||||
"arm,vexpress-sysreg,sys_mci"
|
||||
"arm,vexpress-sysreg,sys_flash"
|
||||
- gpio-controller : makes the node a GPIO controller
|
||||
- #gpio-cells : size of the GPIO specifier, must be 2:
|
||||
- first cell is the function number:
|
||||
- for sys_led : 0..7 = LED 0..7
|
||||
- for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
|
||||
- for sys_flash : 0 = NOR FLASH WPn
|
||||
- second cell can take standard GPIO flags (currently ignored).
|
||||
|
||||
Example:
|
||||
v2m_sysreg: sysreg@10000000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x10000000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
v2m_led_gpios: sys_led@08 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_mmc_gpios: sys_mci@48 {
|
||||
compatible = "arm,vexpress-sysreg,sys_mci";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_flash_gpios: sys_flash@4c {
|
||||
compatible = "arm,vexpress-sysreg,sys_flash";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
This block also can also act a bridge to the platform's configuration
|
||||
bus via "system control" interface, addressing devices with site number,
|
||||
position in the board stack, config controller, function and device
|
||||
numbers - see motherboard's TRM for more details.
|
||||
|
||||
The node describing a config device must refer to the sysreg node via
|
||||
"arm,vexpress,config-bridge" phandle (can be also defined in the node's
|
||||
parent) and relies on the board topology properties - see main vexpress
|
||||
node documentation for more details. It must also define the following
|
||||
property:
|
||||
- arm,vexpress-sysreg,func : must contain two cells:
|
||||
- first cell defines function number (eg. 1 for clock generator,
|
||||
2 for voltage regulators etc.)
|
||||
- device number (eg. osc 0, osc 1 etc.)
|
||||
numbers - see motherboard's TRM for more details. All configuration
|
||||
controller accessible via this interface must reference the sysreg
|
||||
node via "arm,vexpress,config-bridge" phandle and define appropriate
|
||||
topology properties - see main vexpress node documentation for more
|
||||
details. Each child of such node describes one function and must
|
||||
define the following properties:
|
||||
- compatible value : must be one of (corresponding to the TRM):
|
||||
"arm,vexpress-amp"
|
||||
"arm,vexpress-dvimode"
|
||||
"arm,vexpress-energy"
|
||||
"arm,vexpress-muxfpga"
|
||||
"arm,vexpress-osc"
|
||||
"arm,vexpress-power"
|
||||
"arm,vexpress-reboot"
|
||||
"arm,vexpress-reset"
|
||||
"arm,vexpress-scc"
|
||||
"arm,vexpress-shutdown"
|
||||
"arm,vexpress-temp"
|
||||
"arm,vexpress-volt"
|
||||
- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
|
||||
- first cell of each group defines the function number
|
||||
(eg. 1 for clock generator, 2 for voltage regulators etc.)
|
||||
- second cell of each group defines device number (eg. osc 0,
|
||||
osc 1 etc.)
|
||||
- some functions (eg. energy meter, with its 64 bit long counter)
|
||||
are using more than one function/device number pair
|
||||
|
||||
Example:
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
};
|
||||
|
||||
energy@0 {
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -80,12 +80,17 @@ but also control clock generators, voltage regulators, gather
|
|||
environmental data like temperature, power consumption etc. Even
|
||||
the video output switch (FPGA) is controlled that way.
|
||||
|
||||
Nodes describing devices controlled by this infrastructure should
|
||||
point at the bridge device node:
|
||||
The controllers are not mapped into normal memory address space
|
||||
and must be accessed through bridges - other devices capable
|
||||
of generating transactions on the configuration bus.
|
||||
|
||||
The nodes describing configuration controllers must define
|
||||
the following properties:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
- bridge phandle:
|
||||
arm,vexpress,config-bridge = <phandle>;
|
||||
This property can be also defined in a parent node (eg. for a DCC)
|
||||
and is effective for all children.
|
||||
and children describing available functions.
|
||||
|
||||
|
||||
Platform topology
|
||||
|
@ -197,7 +202,7 @@ Example of a VE tile description (simplified)
|
|||
};
|
||||
|
||||
dcc {
|
||||
compatible = "simple-bus";
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
|
|
|
@ -4,10 +4,16 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
|
|||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, one of "snps,spear-ahci",
|
||||
"snps,exynos5440-ahci", "ibm,476gtr-ahci",
|
||||
"allwinner,sun4i-a10-ahci", "fsl,imx53-ahci"
|
||||
"fsl,imx6q-ahci" or "snps,dwc-ahci"
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "fsl,imx53-ahci"
|
||||
- "fsl,imx6q-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
- "marvell,armada-380-ahci"
|
||||
- "snps,dwc-ahci"
|
||||
- "snps,exynos5440-ahci"
|
||||
- "snps,spear-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
|
|
|
@ -0,0 +1,30 @@
|
|||
Broadcom GISB bus Arbiter controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,gisb-arb"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this arbiter gets interrupt line from
|
||||
- interrupts: specifies the two interrupts (timeout and TEA) to be used from
|
||||
the parent interrupt controller
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
|
||||
masters are valid at the system level
|
||||
- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
|
||||
masters. Should match the number of bits set in brcm,gisb-master-mask and
|
||||
the order in which they appear
|
||||
|
||||
Example:
|
||||
|
||||
gisb-arb@f0400000 {
|
||||
compatible = "brcm,gisb-arb";
|
||||
reg = <0xf0400000 0x800>;
|
||||
interrupts = <0>, <2>;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
|
||||
brcm,gisb-arb-master-mask = <0x7>;
|
||||
brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
|
||||
};
|
|
@ -197,7 +197,7 @@ to be set by the operating system and that are guaranteed to be free of overlaps
|
|||
with one another or with the system memory ranges.
|
||||
|
||||
Each entry in the property refers to exactly one window. If the operating system
|
||||
choses to use a different set of mbus windows, it must ensure that any address
|
||||
chooses to use a different set of mbus windows, it must ensure that any address
|
||||
translations performed from downstream devices are adapted accordingly.
|
||||
|
||||
The operating system may insert additional mbus windows that do not conflict
|
||||
|
|
|
@ -21,8 +21,8 @@ Optional properties:
|
|||
- fixed-divider : If clocks have a fixed divider value, use this property.
|
||||
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
|
||||
and the bit index.
|
||||
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
|
||||
and width.
|
||||
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
|
||||
the divider register, bit shift, and width.
|
||||
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
|
||||
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
|
||||
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
|
||||
|
|
|
@ -6,6 +6,16 @@ This binding uses the common clock binding[1].
|
|||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
This node contains the slow clock definitions.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-osc":
|
||||
at91 slow oscillator
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-rc-osc":
|
||||
at91 internal slow RC oscillator
|
||||
|
||||
"atmel,at91rm9200-pmc" or
|
||||
"atmel,at91sam9g45-pmc" or
|
||||
"atmel,at91sam9n12-pmc" or
|
||||
|
@ -15,8 +25,18 @@ Required properties:
|
|||
All at91 specific clocks (clocks defined below) must be child
|
||||
node of the PMC node.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow" (under sckc node)
|
||||
or
|
||||
"atmel,at91sam9260-clk-slow" (under pmc node):
|
||||
at91 slow clk
|
||||
|
||||
"atmel,at91rm9200-clk-main-osc"
|
||||
"atmel,at91sam9x5-clk-main-rc-osc"
|
||||
at91 main clk sources
|
||||
|
||||
"atmel,at91sam9x5-clk-main"
|
||||
"atmel,at91rm9200-clk-main":
|
||||
at91 main oscillator
|
||||
at91 main clock
|
||||
|
||||
"atmel,at91rm9200-clk-master" or
|
||||
"atmel,at91sam9x5-clk-master":
|
||||
|
@ -54,6 +74,63 @@ Required properties:
|
|||
"atmel,at91sam9x5-clk-utmi":
|
||||
at91 utmi clock
|
||||
|
||||
Required properties for SCKC node:
|
||||
- reg : defines the IO memory reserved for the SCKC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
|
||||
|
||||
For example:
|
||||
sckc: sckc@fffffe50 {
|
||||
compatible = "atmel,sama5d3-pmc";
|
||||
reg = <0xfffffe50 0x4>
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
/* put at91 slow clocks here */
|
||||
};
|
||||
|
||||
|
||||
Required properties for internal slow RC oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for slow oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91rm9200-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_xtal>;
|
||||
};
|
||||
|
||||
Required properties for slow clock:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the slow clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
clk32k: slck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
|
||||
Required properties for PMC node:
|
||||
- reg : defines the IO memory reserved for the PMC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
|
@ -62,7 +139,7 @@ Required properties for PMC node:
|
|||
- interrupt-controller : tell that the PMC is an interrupt controller.
|
||||
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
|
||||
and reflect the bit position in the PMC_ER/DR/SR registers.
|
||||
You can use the dt macros defined in dt-bindings/clk/at91.h.
|
||||
You can use the dt macros defined in dt-bindings/clock/at91.h.
|
||||
0 (AT91_PMC_MOSCS) -> main oscillator ready
|
||||
1 (AT91_PMC_LOCKA) -> PLL A ready
|
||||
2 (AT91_PMC_LOCKB) -> PLL B ready
|
||||
|
@ -85,24 +162,57 @@ For example:
|
|||
/* put at91 clocks here */
|
||||
};
|
||||
|
||||
Required properties for main clock internal RC oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
main_rc_osc: main_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for main clock oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
|
||||
on XIN.
|
||||
|
||||
clock signal is directly provided on XIN pin.
|
||||
|
||||
For example:
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
Required properties for main clock:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks (optional if clock-frequency is provided) : shall be the slow clock
|
||||
phandle. This clock is used to calculate the main clock rate if
|
||||
"clock-frequency" is not provided.
|
||||
- clock-frequency : the main oscillator frequency.Prefer the use of
|
||||
"clock-frequency" over automatic clock rate calculation.
|
||||
- clocks : shall encode the main clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
compatible = "atmel,at91sam9x5-clk-main";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&ck32k>;
|
||||
clock-frequency = <18432000>;
|
||||
clocks = <&main_rc_osc &main_osc>;
|
||||
};
|
||||
|
||||
Required properties for master clock:
|
||||
|
|
|
@ -10,12 +10,12 @@ This binding uses the common clock binding:
|
|||
|
||||
Required properties:
|
||||
- compatible
|
||||
Shall have one of the following values:
|
||||
- "brcm,bcm11351-root-ccu"
|
||||
- "brcm,bcm11351-aon-ccu"
|
||||
- "brcm,bcm11351-hub-ccu"
|
||||
- "brcm,bcm11351-master-ccu"
|
||||
- "brcm,bcm11351-slave-ccu"
|
||||
Shall have a value of the form "brcm,<model>-<which>-ccu",
|
||||
where <model> is a Broadcom SoC model number and <which> is
|
||||
the name of a defined CCU. For example:
|
||||
"brcm,bcm11351-root-ccu"
|
||||
The compatible strings used for each supported SoC family
|
||||
are defined below.
|
||||
- reg
|
||||
Shall define the base and range of the address space
|
||||
containing clock control registers
|
||||
|
@ -26,12 +26,48 @@ Required properties:
|
|||
Shall be an ordered list of strings defining the names of
|
||||
the clocks provided by the CCU.
|
||||
|
||||
Device tree example:
|
||||
|
||||
BCM281XX family SoCs use Kona CCUs. The following table defines
|
||||
the set of CCUs and clock specifiers for BCM281XX clocks. When
|
||||
a clock consumer references a clocks, its symbolic specifier
|
||||
(rather than its numeric index value) should be used. These
|
||||
specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = "brcm,bcm11351-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"uartb4";
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
BCM281XX family
|
||||
---------------
|
||||
CCU compatible string values for SoCs in the BCM281XX family are:
|
||||
"brcm,bcm11351-root-ccu"
|
||||
"brcm,bcm11351-aon-ccu"
|
||||
"brcm,bcm11351-hub-ccu"
|
||||
"brcm,bcm11351-master-ccu"
|
||||
"brcm,bcm11351-slave-ccu"
|
||||
|
||||
The following table defines the set of CCUs and clock specifiers for
|
||||
BCM281XX family clocks. When a clock consumer references a clocks,
|
||||
its symbolic specifier (rather than its numeric index value) should
|
||||
be used. These specifiers are defined in:
|
||||
"include/dt-bindings/clock/bcm281xx.h"
|
||||
|
||||
CCU Clock Type Index Specifier
|
||||
--- ----- ---- ----- ---------
|
||||
|
@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
|
|||
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
|
||||
|
||||
|
||||
Device tree example:
|
||||
BCM21664 family
|
||||
---------------
|
||||
CCU compatible string values for SoCs in the BCM21664 family are:
|
||||
"brcm,bcm21664-root-ccu"
|
||||
"brcm,bcm21664-aon-ccu"
|
||||
"brcm,bcm21664-master-ccu"
|
||||
"brcm,bcm21664-slave-ccu"
|
||||
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = "brcm,bcm11351-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"uartb4";
|
||||
};
|
||||
The following table defines the set of CCUs and clock specifiers for
|
||||
BCM21664 family clocks. When a clock consumer references a clocks,
|
||||
its symbolic specifier (rather than its numeric index value) should
|
||||
be used. These specifiers are defined in:
|
||||
"include/dt-bindings/clock/bcm21664.h"
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
CCU Clock Type Index Specifier
|
||||
--- ----- ---- ----- ---------
|
||||
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
|
||||
|
||||
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
|
||||
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
|
||||
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
|
||||
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
|
||||
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
|
||||
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
|
||||
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
|
||||
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
|
||||
|
||||
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
|
||||
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
|
||||
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
|
||||
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
|
||||
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
|
||||
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
|
||||
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
|
||||
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
|
||||
|
|
|
@ -44,10 +44,9 @@ For example:
|
|||
clocks by index. The names should reflect the clock output signal
|
||||
names for the device.
|
||||
|
||||
clock-indices: If the identifyng number for the clocks in the node
|
||||
is not linear from zero, then the this mapping allows
|
||||
the mapping of identifiers into the clock-output-names
|
||||
array.
|
||||
clock-indices: If the identifying number for the clocks in the node
|
||||
is not linear from zero, then this allows the mapping of
|
||||
identifiers into the clock-output-names array.
|
||||
|
||||
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
||||
|
||||
|
@ -58,7 +57,7 @@ For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
|||
clock-output-names = "clka", "clkb";
|
||||
}
|
||||
|
||||
This ensures we do not have any empty nodes in clock-output-names
|
||||
This ensures we do not have any empty strings in clock-output-names
|
||||
|
||||
|
||||
==Clock consumers==
|
||||
|
|
|
@ -0,0 +1,41 @@
|
|||
* Samsung Exynos3250 Clock Controller
|
||||
|
||||
The Exynos3250 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos3250 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos3250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
cmu: clock-controller@10030000 {
|
||||
compatible = "samsung,exynos3250-cmu";
|
||||
reg = <0x10030000 0x20000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@13800000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13800000 0x100>;
|
||||
interrupts = <0 109 0>;
|
||||
clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
|
@ -0,0 +1,190 @@
|
|||
* Samsung Exynos5260 Clock Controller
|
||||
|
||||
Exynos5260 has 13 clock controllers which are instantiated
|
||||
independently from the device-tree. These clock controllers
|
||||
generate and supply clocks to various hardware blocks within
|
||||
the SoC.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use
|
||||
this identifier to specify the clock which they consume. All
|
||||
available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5260-clk.h header and can be used in
|
||||
device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It
|
||||
is expected that they are defined using standard clock bindings
|
||||
with following clock-output-names:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
- "xrtcxti" - input clock from XRTCXTI
|
||||
- "ioclk_pcm_extclk" - pcm external operation clock
|
||||
- "ioclk_spdif_extclk" - spdif external operation clock
|
||||
- "ioclk_i2s_cdclk" - i2s0 codec clock
|
||||
|
||||
Phy clocks:
|
||||
|
||||
There are several clocks which are generated by specific PHYs.
|
||||
These clocks are fed into the clock controller and then routed to
|
||||
the hardware blocks. These clocks are defined as fixed clocks in the
|
||||
driver with following names:
|
||||
|
||||
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
|
||||
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
|
||||
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
|
||||
- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
|
||||
- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
|
||||
- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
|
||||
- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
|
||||
- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
|
||||
- "phyclk_dptx_phy_clk_div2"
|
||||
- "phyclk_mipi_dphy_4l_m_rxclkesc0"
|
||||
- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
|
||||
- "phyclk_usbhost20_phy_freeclk"
|
||||
- "phyclk_usbhost20_phy_clk48mohci"
|
||||
- "phyclk_usbdrd30_udrd30_pipe_pclk"
|
||||
- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
|
||||
|
||||
Required Properties for Clock Controller:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
1) "samsung,exynos5260-clock-top"
|
||||
2) "samsung,exynos5260-clock-peri"
|
||||
3) "samsung,exynos5260-clock-egl"
|
||||
4) "samsung,exynos5260-clock-kfc"
|
||||
5) "samsung,exynos5260-clock-g2d"
|
||||
6) "samsung,exynos5260-clock-mif"
|
||||
7) "samsung,exynos5260-clock-mfc"
|
||||
8) "samsung,exynos5260-clock-g3d"
|
||||
9) "samsung,exynos5260-clock-fsys"
|
||||
10) "samsung,exynos5260-clock-aud"
|
||||
11) "samsung,exynos5260-clock-isp"
|
||||
12) "samsung,exynos5260-clock-gscl"
|
||||
13) "samsung,exynos5260-clock-disp"
|
||||
|
||||
- reg: physical base address of the controller and the length of
|
||||
memory mapped region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- clocks: list of clock identifiers which are fed as the input to
|
||||
the given clock controller. Please refer the next section to find
|
||||
the input clocks for a given controller.
|
||||
|
||||
- clock-names: list of names of clocks which are fed as the input
|
||||
to the given clock controller.
|
||||
|
||||
Input clocks for top clock controller:
|
||||
- fin_pll
|
||||
- dout_mem_pll
|
||||
- dout_bus_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for peri clock controller:
|
||||
- fin_pll
|
||||
- ioclk_pcm_extclk
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_spdif_extclk
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- dout_aclk_peri_66
|
||||
- dout_sclk_peri_uart0
|
||||
- dout_sclk_peri_uart1
|
||||
- dout_sclk_peri_uart2
|
||||
- dout_sclk_peri_spi0_b
|
||||
- dout_sclk_peri_spi1_b
|
||||
- dout_sclk_peri_spi2_b
|
||||
- dout_aclk_peri_aud
|
||||
- dout_sclk_peri_spi0_b
|
||||
|
||||
Input clocks for egl clock controller:
|
||||
- fin_pll
|
||||
- dout_bus_pll
|
||||
|
||||
Input clocks for kfc clock controller:
|
||||
- fin_pll
|
||||
- dout_media_pll
|
||||
|
||||
Input clocks for g2d clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_g2d_333
|
||||
|
||||
Input clocks for mif clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for mfc clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_mfc_333
|
||||
|
||||
Input clocks for g3d clock controller:
|
||||
- fin_pll
|
||||
|
||||
Input clocks for fsys clock controller:
|
||||
- fin_pll
|
||||
- phyclk_usbhost20_phy_phyclock
|
||||
- phyclk_usbhost20_phy_freeclk
|
||||
- phyclk_usbhost20_phy_clk48mohci
|
||||
- phyclk_usbdrd30_udrd30_pipe_pclk
|
||||
- phyclk_usbdrd30_udrd30_phyclock
|
||||
- dout_aclk_fsys_200
|
||||
|
||||
Input clocks for aud clock controller:
|
||||
- fin_pll
|
||||
- fout_aud_pll
|
||||
- ioclk_i2s_cdclk
|
||||
- ioclk_pcm_extclk
|
||||
|
||||
Input clocks for isp clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_isp1_266
|
||||
- dout_aclk_isp1_400
|
||||
- mout_aclk_isp1_266
|
||||
|
||||
Input clocks for gscl clock controller:
|
||||
- fin_pll
|
||||
- dout_aclk_gscl_400
|
||||
- dout_aclk_gscl_333
|
||||
|
||||
Input clocks for disp clock controller:
|
||||
- fin_pll
|
||||
- phyclk_dptx_phy_ch3_txd_clk
|
||||
- phyclk_dptx_phy_ch2_txd_clk
|
||||
- phyclk_dptx_phy_ch1_txd_clk
|
||||
- phyclk_dptx_phy_ch0_txd_clk
|
||||
- phyclk_hdmi_phy_tmds_clko
|
||||
- phyclk_hdmi_phy_ref_clko
|
||||
- phyclk_hdmi_phy_pixel_clko
|
||||
- phyclk_hdmi_link_o_tmds_clkhi
|
||||
- phyclk_mipi_dphy_4l_m_txbyte_clkhs
|
||||
- phyclk_dptx_phy_o_ref_clk_24m
|
||||
- phyclk_dptx_phy_clk_div2
|
||||
- phyclk_mipi_dphy_4l_m_rxclkesc0
|
||||
- phyclk_hdmi_phy_ref_cko
|
||||
- ioclk_spdif_extclk
|
||||
- dout_aclk_peri_aud
|
||||
- dout_aclk_disp_222
|
||||
- dout_sclk_disp_pixel
|
||||
- dout_aclk_disp_333
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock_mfc: clock-controller@11090000 {
|
||||
compatible = "samsung,exynos5260-clock-mfc";
|
||||
clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
|
||||
clock-names = "fin_pll", "dout_aclk_mfc_333";
|
||||
reg = <0x11090000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the
|
||||
peri clock controller. Refer to the standard clock bindings for
|
||||
information about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C00000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 146 0>;
|
||||
clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
* Samsung Exynos5410 Clock Controller
|
||||
|
||||
The Exynos5410 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5410 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,exynos5410-clock"
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clock:
|
||||
|
||||
There is clock that is generated outside the SoC. It
|
||||
is expected that it is defined using standard clock bindings
|
||||
with following clock-output-name:
|
||||
|
||||
- "fin_pll" - PLL input clock from XXTI
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
clock: clock-controller@0x10010000 {
|
||||
compatible = "samsung,exynos5410-clock";
|
||||
reg = <0x10010000 0x30000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example 2: UART controller node that consumes the clock generated by the clock
|
||||
controller. Refer to the standard clock bindings for information
|
||||
about 'clocks' and 'clock-names' property.
|
||||
|
||||
serial@12C20000 {
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x12C00000 0x100>;
|
||||
interrupts = <0 51 0>;
|
||||
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
|
@ -1,12 +1,13 @@
|
|||
* Samsung Exynos5420 Clock Controller
|
||||
|
||||
The Exynos5420 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5420 SoC.
|
||||
controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
|
||||
- "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
|
|
@ -12,7 +12,6 @@ Required properties:
|
|||
Optional properties:
|
||||
- clock-accuracy : accuracy of clock in ppb (parts per billion).
|
||||
Should be a single cell.
|
||||
- gpios : From common gpio binding; gpio connection to clock enable pin.
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
* Hisilicon Hix5hd2 Clock Controller
|
||||
|
||||
The hix5hd2 clock controller generates and supplies clock to various
|
||||
controllers within the hix5hd2 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "hisilicon,hix5hd2-clock"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hix5hd2-clock.h>.
|
||||
|
||||
Examples:
|
||||
clock: clock@f8a22000 {
|
||||
compatible = "hisilicon,hix5hd2-clock";
|
||||
reg = <0xf8a22000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: uart@f8b00000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0xf8b00000 0x1000>;
|
||||
interrupts = <0 49 4>;
|
||||
clocks = <&clock HIX5HD2_FIXED_83M>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
|
@ -139,6 +139,9 @@ clocks and IDs.
|
|||
uart5_ipg 124
|
||||
reserved 125
|
||||
wdt_ipg 126
|
||||
cko_div 127
|
||||
cko_sel 128
|
||||
cko 129
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
@ -98,7 +98,12 @@ clocks and IDs.
|
|||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
spll_gate 86
|
||||
mshc_div 87
|
||||
rtic_ipg_gate 88
|
||||
mshc_ipg_gate 89
|
||||
rtic_ahb_gate 90
|
||||
mshc_baud_gate 91
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
@ -220,6 +220,7 @@ clocks and IDs.
|
|||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
esai_ahb 208
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
@ -0,0 +1,13 @@
|
|||
* Clock bindings for Freescale i.MX6 SoloX
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sx-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
|
||||
for the full list of i.MX6 SoloX clock IDs.
|
|
@ -0,0 +1,29 @@
|
|||
AXM5516 clock driver bindings
|
||||
-----------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "lsi,axm5516-clks"
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
The consumer specifies the desired clock by having the clock ID in its "clocks"
|
||||
phandle cell. See <dt-bindings/clock/lsi,axxia-clock.h> for the list of
|
||||
supported clock IDs.
|
||||
|
||||
Example:
|
||||
|
||||
clks: clock-controller@2010020000 {
|
||||
compatible = "lsi,axm5516-clks";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x20 0x10020000 0 0x20000>;
|
||||
};
|
||||
|
||||
serial0: uart@2010080000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10080000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
|
@ -29,6 +29,11 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
|
|||
2 = l2clk (L2 Cache clock derived from CPU0 clock)
|
||||
3 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Orion5x:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU0 clock)
|
||||
2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
|
||||
|
@ -38,6 +43,9 @@ Required properties:
|
|||
"marvell,dove-core-clock" - for Dove SoC core clocks
|
||||
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
||||
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
|
||||
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
|
||||
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
|
||||
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
|
||||
- reg : shall be the register address of the Sample-At-Reset (SAR) register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
|
|
|
@ -4,9 +4,12 @@ Qualcomm Global Clock & Reset Controller Binding
|
|||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
|
|
@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including
|
|||
cores and peripheral IP blocks.
|
||||
Please refer to the Reference Manual for details.
|
||||
|
||||
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
|
||||
which the chip complies.
|
||||
|
||||
Chassis Version Example Chips
|
||||
--------------- -------------
|
||||
1.0 p4080, p5020, p5040
|
||||
2.0 t4240, b4860, t1040
|
||||
|
||||
1. Clock Block Binding
|
||||
|
||||
Required properties:
|
||||
|
@ -85,7 +93,7 @@ Example for clock block and clock provider:
|
|||
#clock-cells = <0>;
|
||||
compatible = "fsl,qoriq-sysclk-1.0";
|
||||
clock-output-names = "sysclk";
|
||||
}
|
||||
};
|
||||
|
||||
pll0: pll0@800 {
|
||||
#clock-cells = <1>;
|
|
@ -10,6 +10,8 @@ index in the group, from 0 to 31.
|
|||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
|
||||
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
|
||||
|
@ -43,7 +45,7 @@ Example
|
|||
clock-output-names =
|
||||
"tpu0", "mmcif1", "sdhi3", "sdhi2",
|
||||
"sdhi1", "sdhi0", "mmcif0";
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
|
||||
R8A7790_CLK_MMCIF0
|
||||
|
|
|
@ -0,0 +1,41 @@
|
|||
These bindings should be considered EXPERIMENTAL for now.
|
||||
|
||||
* Renesas R8A7740 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
|
||||
and several fixed ratio and variable ratio dividers.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7740-cpg-clocks"
|
||||
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the three parent clocks
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are
|
||||
"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
|
||||
"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
|
||||
|
||||
- renesas,mode: board-specific settings of the MD_CK* bits
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@e6150000 {
|
||||
compatible = "renesas,r8a7740-cpg-clocks";
|
||||
reg = <0xe6150000 0x10000>;
|
||||
clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "system", "pllc0", "pllc1",
|
||||
"pllc2", "r",
|
||||
"usb24s",
|
||||
"i", "zg", "b", "m1", "hp",
|
||||
"hpp", "usbp", "s", "zb", "m3",
|
||||
"cp";
|
||||
};
|
||||
|
||||
&cpg_clocks {
|
||||
renesas,mode = <0x05>;
|
||||
};
|
|
@ -0,0 +1,27 @@
|
|||
* Renesas R8A7779 Clock Pulse Generator (CPG)
|
||||
|
||||
The CPG generates core clocks for the R8A7779. It includes one PLL and
|
||||
several fixed ratio dividers
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be "renesas,r8a7779-cpg-clocks"
|
||||
- reg: Base address and length of the memory resource used by the CPG
|
||||
|
||||
- clocks: Reference to the parent clock
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The names of the clocks. Supported clocks are "plla",
|
||||
"z", "zs", "s", "s1", "p", "b", "out".
|
||||
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
cpg_clocks: cpg_clocks@ffc80000 {
|
||||
compatible = "renesas,r8a7779-cpg-clocks";
|
||||
reg = <0 0xffc80000 0 0x30>;
|
||||
clocks = <&extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
|
||||
"b", "out";
|
||||
};
|
|
@ -0,0 +1,50 @@
|
|||
* Samsung S3C2410 Clock Controller
|
||||
|
||||
The S3C2410 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to the s3c2410,
|
||||
s3c2440 and s3c2442 SoCs in the s3c24x family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC.
|
||||
- "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC.
|
||||
- "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2410.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
The xti clock used as input for the plls is generated outside the SoC. It is
|
||||
expected that is are defined using standard clock bindings with a
|
||||
clock-output-names value of "xti".
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2410-clock";
|
||||
reg = <0x4c000000 0x20>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2440-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
|
@ -0,0 +1,50 @@
|
|||
* Samsung S3C2412 Clock Controller
|
||||
|
||||
The S3C2412 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to the s3c2412
|
||||
and s3c2413 SoCs in the s3c24x family.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "samsung,s3c2412-clock"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2412.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xti" - crystal input - required,
|
||||
- "ext" - external clock source - optional,
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2412-clock";
|
||||
reg = <0x4c000000 0x20>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2412-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
|
@ -0,0 +1,56 @@
|
|||
* Samsung S3C2443 Clock Controller
|
||||
|
||||
The S3C2443 clock controller generates and supplies clock to various controllers
|
||||
within the SoC. The clock binding described here is applicable to all SoCs in
|
||||
the s3c24x family starting with the s3c2443.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC.
|
||||
- "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC.
|
||||
- "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC.
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. Some of the clocks are available only
|
||||
on a particular SoC.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/s3c2443.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xti" - crystal input - required,
|
||||
- "ext" - external clock source - optional,
|
||||
- "ext_i2s" - external I2S clock - optional,
|
||||
- "ext_uart" - external uart clock - optional,
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
clocks: clock-controller@4c000000 {
|
||||
compatible = "samsung,s3c2416-clock";
|
||||
reg = <0x4c000000 0x40>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller (refer to the standard clock bindings for information about
|
||||
"clocks" and "clock-names" properties):
|
||||
|
||||
serial@50004000 {
|
||||
compatible = "samsung,s3c2440-uart";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1 23 3 4>, <1 23 4 4>;
|
||||
clock-names = "uart", "clk_uart_baud2",
|
||||
"clk_uart_baud3";
|
||||
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
|
||||
<&clocks SCLK_UART>;
|
||||
status = "disabled";
|
||||
};
|
|
@ -20,12 +20,15 @@ Required properties:
|
|||
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
|
||||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
|
@ -41,6 +44,7 @@ Required properties:
|
|||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
|
|
|
@ -0,0 +1,20 @@
|
|||
* Device tree bindings for Texas Instruments keystone pll controller
|
||||
|
||||
The main pll controller used to drive theC66x CorePacs, the switch fabric,
|
||||
and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
|
||||
the NETCP modules) requires a PLL Controller to manage the various clock
|
||||
divisions, gating, and synchronization.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,keystone-pllctrl", "syscon"
|
||||
|
||||
- reg: contains offset/length value for pll controller
|
||||
registers space.
|
||||
|
||||
Example:
|
||||
|
||||
pllctrl: pll-controller@0x02310000 {
|
||||
compatible = "ti,keystone-pllctrl", "syscon";
|
||||
reg = <0x02310000 0x200>;
|
||||
};
|
|
@ -14,18 +14,32 @@ a subtype of a DPLL [2], although a simplified one at that.
|
|||
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-apll-clock"
|
||||
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
||||
- reg : address and length of the register set for controlling the APLL.
|
||||
It contains the information of registers in the following order:
|
||||
"control" - contains the control register base address
|
||||
"idlest" - contains the idlest register base address
|
||||
"control" - contains the control register offset
|
||||
"idlest" - contains the idlest register offset
|
||||
"autoidle" - contains the autoidle register offset (OMAP2 only)
|
||||
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
|
||||
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
|
||||
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
|
||||
|
||||
Examples:
|
||||
apll_pcie_ck: apll_pcie_ck@4a008200 {
|
||||
apll_pcie_ck: apll_pcie_ck {
|
||||
#clock-cells = <0>;
|
||||
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
|
||||
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
|
||||
reg = <0x021c>, <0x0220>;
|
||||
compatible = "ti,dra7-apll-clock";
|
||||
};
|
||||
|
||||
apll96_ck: apll96_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2-apll-clock";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <2>;
|
||||
ti,idlest-shift = <8>;
|
||||
ti,clock-frequency = <96000000>;
|
||||
reg = <0x0500>, <0x0530>, <0x0520>;
|
||||
};
|
||||
|
|
|
@ -24,12 +24,14 @@ Required properties:
|
|||
"ti,omap4-dpll-core-clock",
|
||||
"ti,omap4-dpll-m4xen-clock",
|
||||
"ti,omap4-dpll-j-type-clock",
|
||||
"ti,omap5-mpu-dpll-clock",
|
||||
"ti,am3-dpll-no-gate-clock",
|
||||
"ti,am3-dpll-j-type-clock",
|
||||
"ti,am3-dpll-no-gate-j-type-clock",
|
||||
"ti,am3-dpll-clock",
|
||||
"ti,am3-dpll-core-clock",
|
||||
"ti,am3-dpll-x2-clock",
|
||||
"ti,omap2-dpll-core-clock",
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks, first entry lists reference clock
|
||||
|
@ -41,6 +43,7 @@ Required properties:
|
|||
"mult-div1" - contains the multiplier / divider register base address
|
||||
"autoidle" - contains the autoidle register base address (optional)
|
||||
ti,am3-* dpll types do not have autoidle register
|
||||
ti,omap2-* dpll type does not support idlest / autoidle registers
|
||||
|
||||
Optional properties:
|
||||
- DPLL mode setting - defining any one or more of the following overrides
|
||||
|
@ -73,3 +76,10 @@ Examples:
|
|||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x90>, <0x5c>, <0x68>;
|
||||
};
|
||||
|
||||
dpll_ck: dpll_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2-dpll-core-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0500>, <0x0540>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,96 @@
|
|||
Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
|
||||
|
||||
The ATL IP is used to generate clock to be used to synchronize baseband and
|
||||
audio codec. A single ATL IP provides four ATL clock instances sharing the same
|
||||
functional clock but can be configured to provide different clocks.
|
||||
ATL can maintain a clock averages to some desired frequency based on the bws/aws
|
||||
signals - can compensate the drift between the two ws signal.
|
||||
|
||||
In order to provide the support for ATL and it's output clocks (which can be used
|
||||
internally within the SoC or external components) two sets of bindings is needed:
|
||||
|
||||
Clock tree binding:
|
||||
This binding uses the common clock binding[1].
|
||||
To be able to integrate the ATL clocks with DT clock tree.
|
||||
Provides ccf level representation of the ATL clocks to be used by drivers.
|
||||
Since the clock instances are part of a single IP this binding is used as a node
|
||||
for the DT clock tree, the IP driver is needed to handle the actual configuration
|
||||
of the IP.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-atl-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles to functional clock of ATL
|
||||
|
||||
Binding for the IP driver:
|
||||
This binding is used to configure the IP driver which is going to handle the
|
||||
configuration of the IP for the ATL clock instances.
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-atl"
|
||||
- reg : base address for the ATL IP
|
||||
- ti,provided-clocks : List of phandles to the clocks associated with the ATL
|
||||
- clocks : link phandles to functional clock of ATL
|
||||
- clock-names : Shall be set to "fck"
|
||||
- ti,hwmods : Shall be set to "atl"
|
||||
|
||||
Optional properties:
|
||||
Configuration of ATL instances:
|
||||
- atl{0/1/2/3} {
|
||||
- bws : Baseband word select signal selection
|
||||
- aws : Audio word select signal selection
|
||||
};
|
||||
|
||||
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
|
||||
file.
|
||||
|
||||
Examples:
|
||||
/* clock bindings for atl provided clocks */
|
||||
atl_clkin0_ck: atl_clkin0_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin1_ck: atl_clkin1_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin2_ck: atl_clkin2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
atl_clkin3_ck: atl_clkin3_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dra7-atl-clock";
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
};
|
||||
|
||||
/* binding for the IP */
|
||||
atl: atl@4843c000 {
|
||||
compatible = "ti,dra7-atl";
|
||||
reg = <0x4843c000 0x3ff>;
|
||||
ti,hwmods = "atl";
|
||||
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
|
||||
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
||||
clocks = <&atl_gfclk_mux>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
|
||||
&atl {
|
||||
status = "okay";
|
||||
|
||||
atl2 {
|
||||
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
||||
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
||||
};
|
||||
};
|
|
@ -25,6 +25,11 @@ Required properties:
|
|||
to map clockdomains properly
|
||||
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
|
||||
required for a hardware errata
|
||||
"ti,composite-gate-clock" - composite gate clock, to be part of composite
|
||||
clock
|
||||
"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
|
||||
for clock to be active before returning
|
||||
from clk_enable()
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable gate, not needed for
|
||||
|
@ -41,7 +46,7 @@ Examples:
|
|||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x48004a00 0x4>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <25>;
|
||||
};
|
||||
|
||||
|
@ -57,7 +62,7 @@ Examples:
|
|||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
reg = <0x48004e00 0x4>;
|
||||
reg = <0x0e00>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
|
@ -65,7 +70,7 @@ Examples:
|
|||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x4800259c 0x4>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
|
@ -80,6 +85,22 @@ Examples:
|
|||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x48004d00 0x4>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
vlynq_gate_fck: vlynq_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0200>;
|
||||
};
|
||||
|
||||
sys_clkout2_src_gate: sys_clkout2_src_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <15>;
|
||||
reg = <0x0070>;
|
||||
};
|
||||
|
|
|
@ -21,6 +21,8 @@ Required properties:
|
|||
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
|
||||
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
|
||||
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
|
||||
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
|
||||
handling
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : base address for the control register
|
||||
|
|
|
@ -0,0 +1,34 @@
|
|||
Samsung SoC SSS (Security SubSystem) module
|
||||
|
||||
The SSS module in S5PV210 SoC supports the following:
|
||||
-- Feeder (FeedCtrl)
|
||||
-- Advanced Encryption Standard (AES)
|
||||
-- Data Encryption Standard (DES)/3DES
|
||||
-- Public Key Accelerator (PKA)
|
||||
-- SHA-1/SHA-256/MD5/HMAC (SHA-1/SHA-256/MD5)/PRNG
|
||||
-- PRNG: Pseudo Random Number Generator
|
||||
|
||||
The SSS module in Exynos4 (Exynos4210) and
|
||||
Exynos5 (Exynos5420 and Exynos5250) SoCs
|
||||
supports the following also:
|
||||
-- ARCFOUR (ARC4)
|
||||
-- True Random Number Generator (TRNG)
|
||||
-- Secure Key Manager
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should contain entries for this and backward compatible
|
||||
SSS versions:
|
||||
- "samsung,s5pv210-secss" for S5PV210 SoC.
|
||||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts, should contain
|
||||
following entries:
|
||||
- first : feed control interrupt (required for all variants),
|
||||
- second : hash interrupt (required only for samsung,s5pv210-secss).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
- clock-names : list of device clock input names; should contain one entry
|
||||
"secss".
|
|
@ -14,7 +14,7 @@ Required property:
|
|||
|
||||
Optional properties:
|
||||
- dma-channels: Number of DMA channels supported by the controller.
|
||||
- dma-requests: Number of DMA requests signals supported by the
|
||||
- dma-requests: Number of DMA request signals supported by the
|
||||
controller.
|
||||
|
||||
Example:
|
||||
|
@ -44,7 +44,7 @@ Required property:
|
|||
#dma-cells property in the node referenced by phandle
|
||||
containing DMA controller specific information. This
|
||||
typically contains a DMA request line number or a
|
||||
channel number, but can contain any data that is used
|
||||
channel number, but can contain any data that is
|
||||
required for configuring a channel.
|
||||
- dma-names: Contains one identifier string for each DMA specifier in
|
||||
the dmas property. The specific strings that can be used
|
||||
|
|
|
@ -8,7 +8,7 @@ Required properties:
|
|||
"fsl,imx51-sdma"
|
||||
"fsl,imx53-sdma"
|
||||
"fsl,imx6q-sdma"
|
||||
The -to variants should be preferred since they allow to determnine the
|
||||
The -to variants should be preferred since they allow to determine the
|
||||
correct ROM script addresses needed for the driver to work without additional
|
||||
firmware.
|
||||
- reg : Should contain SDMA registers location and length
|
||||
|
|
|
@ -1,17 +1,20 @@
|
|||
* MARVELL MMP DMA controller
|
||||
|
||||
Marvell Peripheral DMA Controller
|
||||
Used platfroms: pxa688, pxa910, pxa3xx, etc
|
||||
Used platforms: pxa688, pxa910, pxa3xx, etc
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pdma-1.0"
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Either contain all of the per-channel DMA interrupts
|
||||
or one irq for pdma device
|
||||
- #dma-channels: Number of DMA channels supported by the controller.
|
||||
|
||||
Optional properties:
|
||||
- #dma-channels: Number of DMA channels supported by the controller (defaults
|
||||
to 32 when not specified)
|
||||
|
||||
"marvell,pdma-1.0"
|
||||
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
||||
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
||||
|
||||
Examples:
|
||||
|
||||
|
@ -45,7 +48,7 @@ pdma: dma-controller@d4000000 {
|
|||
|
||||
|
||||
Marvell Two Channel DMA Controller used specifically for audio
|
||||
Used platfroms: pxa688, pxa910
|
||||
Used platforms: pxa688, pxa910
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
|
||||
|
|
|
@ -2,11 +2,8 @@ TI EDMA
|
|||
|
||||
Required properties:
|
||||
- compatible : "ti,edma3"
|
||||
- ti,edma-regions: Number of regions
|
||||
- ti,edma-slots: Number of slots
|
||||
- #dma-cells: Should be set to <1>
|
||||
Clients should use a single channel number per DMA request.
|
||||
- dma-channels: Specify total DMA channels per CC
|
||||
- reg: Memory map for accessing module
|
||||
- interrupt-parent: Interrupt controller the interrupt is routed through
|
||||
- interrupts: Exactly 3 interrupts need to be specified in the order:
|
||||
|
@ -17,6 +14,13 @@ Optional properties:
|
|||
- ti,hwmods: Name of the hwmods associated to the EDMA
|
||||
- ti,edma-xbar-event-map: Crossbar event to channel map
|
||||
|
||||
Deprecated properties:
|
||||
Listed here in case one wants to boot an old kernel with new DTB. These
|
||||
properties might need to be added to the new DTS files.
|
||||
- ti,edma-regions: Number of regions
|
||||
- ti,edma-slots: Number of slots
|
||||
- dma-channels: Specify total DMA channels per CC
|
||||
|
||||
Example:
|
||||
|
||||
edma: edma@49000000 {
|
||||
|
@ -26,9 +30,6 @@ edma: edma@49000000 {
|
|||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <64>;
|
||||
ti,edma-regions = <4>;
|
||||
ti,edma-slots = <256>;
|
||||
ti,edma-xbar-event-map = <1 12
|
||||
2 13>;
|
||||
ti,edma-xbar-event-map = /bits/ 16 <1 12
|
||||
2 13>;
|
||||
};
|
||||
|
|
|
@ -0,0 +1,75 @@
|
|||
Xilinx AXI VDMA engine, it does transfers between memory and video devices.
|
||||
It can be configured to have one channel or two channels. If configured
|
||||
as two channels, one is to transmit to the video device and another is
|
||||
to receive from the video device.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a"
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain VDMA registers location and length.
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
It takes following values:
|
||||
{1}, flush both channels
|
||||
{2}, flush mm2s channel
|
||||
{3}, flush s2mm channel
|
||||
|
||||
Required child node properties:
|
||||
- compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or
|
||||
"xlnx,axi-vdma-s2mm-channel".
|
||||
- interrupts: Should contain per channel VDMA interrupts.
|
||||
- xlnx,data-width: Should contain the stream data width, take values
|
||||
{32,64...1024}.
|
||||
|
||||
Optional child node properties:
|
||||
- xlnx,include-dre: Tells hardware is configured for Data
|
||||
Realignment Engine.
|
||||
- xlnx,genlock-mode: Tells Genlock synchronization is
|
||||
enabled/disabled in hardware.
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
axi_vdma_0: axivdma@40030000 {
|
||||
compatible = "xlnx,axi-vdma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40030000 0x10000 >;
|
||||
xlnx,num-fstores = <0x8>;
|
||||
xlnx,flush-fsync = <0x1>;
|
||||
dma-channel@40030000 {
|
||||
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||
interrupts = < 0 54 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
dma-channel@40030030 {
|
||||
compatible = "xlnx,axi-vdma-s2mm-channel";
|
||||
interrupts = < 0 53 4 >;
|
||||
xlnx,datawidth = <0x40>;
|
||||
} ;
|
||||
} ;
|
||||
|
||||
|
||||
* DMA client
|
||||
|
||||
Required properties:
|
||||
- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
|
||||
where Channel ID is '0' for write/tx and '1' for read/rx
|
||||
channel.
|
||||
- dma-names: a list of DMA channel names, one per "dmas" entry
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
vdmatest_0: vdmatest@0 {
|
||||
compatible ="xlnx,axi-vdma-test-1.00.a";
|
||||
dmas = <&axi_vdma_0 0
|
||||
&axi_vdma_0 1>;
|
||||
dma-names = "vdma0", "vdma1";
|
||||
} ;
|
|
@ -54,7 +54,7 @@ Optional device specific properties:
|
|||
IO 8-15 are bank 2. These chips have two different interrupt outputs:
|
||||
One for bank 1 and another for bank 2. If irq-mirror is set, both
|
||||
interrupts are generated regardless of the bank that an input change
|
||||
occured on. If it is not set, the interrupt are only generated for the
|
||||
occurred on. If it is not set, the interrupt are only generated for the
|
||||
bank they belong to.
|
||||
On devices with only one interrupt output this property is useless.
|
||||
|
||||
|
|
|
@ -21,6 +21,12 @@ Required Properties:
|
|||
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
|
||||
- gpio-ranges: Range of pins managed by the GPIO controller.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: Must contain a reference to the functional clock. The property is
|
||||
mandatory if the hardware implements a controllable functional clock for
|
||||
the GPIO instance.
|
||||
|
||||
Please refer to gpio.txt in this directory for details of gpio-ranges property
|
||||
and the common GPIO bindings used by client devices.
|
||||
|
||||
|
|
|
@ -136,6 +136,7 @@ of the following host1x client modules:
|
|||
- compatible: "nvidia,tegra<chip>-hdmi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- hdmi-supply: supply for the +5V HDMI connector pin
|
||||
- vdd-supply: regulator for supply voltage
|
||||
- pll-supply: regulator for PLL
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
|
@ -180,6 +181,7 @@ of the following host1x client modules:
|
|||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- dsi
|
||||
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
|
||||
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
|
||||
which pads are used by this DSI output and need to be calibrated. See also
|
||||
../mipi/nvidia,tegra114-mipi.txt.
|
||||
|
|
|
@ -0,0 +1,44 @@
|
|||
Each HSI port is supposed to have one child node, which
|
||||
symbols the remote device connected to the HSI port. The
|
||||
following properties are standardized for HSI clients:
|
||||
|
||||
Required HSI configuration properties:
|
||||
|
||||
- hsi-channel-ids: A list of channel ids
|
||||
|
||||
- hsi-rx-mode: Receiver Bit transmission mode ("stream" or "frame")
|
||||
- hsi-tx-mode: Transmitter Bit transmission mode ("stream" or "frame")
|
||||
- hsi-mode: May be used instead hsi-rx-mode and hsi-tx-mode if
|
||||
the transmission mode is the same for receiver and
|
||||
transmitter
|
||||
- hsi-speed-kbps: Max bit transmission speed in kbit/s
|
||||
- hsi-flow: RX flow type ("synchronized" or "pipeline")
|
||||
- hsi-arb-mode: Arbitration mode for TX frame ("round-robin", "priority")
|
||||
|
||||
Optional HSI configuration properties:
|
||||
|
||||
- hsi-channel-names: A list with one name per channel specified in the
|
||||
hsi-channel-ids property
|
||||
|
||||
|
||||
Device Tree node example for an HSI client:
|
||||
|
||||
hsi-controller {
|
||||
hsi-port {
|
||||
modem: hsi-client {
|
||||
compatible = "nokia,n900-modem";
|
||||
|
||||
hsi-channel-ids = <0>, <1>, <2>, <3>;
|
||||
hsi-channel-names = "mcsaab-control",
|
||||
"speech-control",
|
||||
"speech-data",
|
||||
"mcsaab-data";
|
||||
hsi-speed-kbps = <55000>;
|
||||
hsi-mode = "frame";
|
||||
hsi-flow = "synchronized";
|
||||
hsi-arb-mode = "round-robin";
|
||||
|
||||
/* more client specific properties */
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,57 @@
|
|||
Nokia modem client bindings
|
||||
|
||||
The Nokia modem HSI client follows the common HSI client binding
|
||||
and inherits all required properties. The following additional
|
||||
properties are needed by the Nokia modem HSI client:
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
"nokia,n900-modem"
|
||||
- hsi-channel-names: Should contain the following strings
|
||||
"mcsaab-control"
|
||||
"speech-control"
|
||||
"speech-data"
|
||||
"mcsaab-data"
|
||||
- gpios: Should provide a GPIO handler for each GPIO listed in
|
||||
gpio-names
|
||||
- gpio-names: Should contain the following strings
|
||||
"cmt_apeslpx"
|
||||
"cmt_rst_rq"
|
||||
"cmt_en"
|
||||
"cmt_rst"
|
||||
"cmt_bsi"
|
||||
- interrupts: Should be IRQ handle for modem's reset indication
|
||||
|
||||
Example:
|
||||
|
||||
&ssi_port {
|
||||
modem: hsi-client {
|
||||
compatible = "nokia,n900-modem";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&modem_pins>;
|
||||
|
||||
hsi-channel-ids = <0>, <1>, <2>, <3>;
|
||||
hsi-channel-names = "mcsaab-control",
|
||||
"speech-control",
|
||||
"speech-data",
|
||||
"mcsaab-data";
|
||||
hsi-speed-kbps = <55000>;
|
||||
hsi-mode = "frame";
|
||||
hsi-flow = "synchronized";
|
||||
hsi-arb-mode = "round-robin";
|
||||
|
||||
interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
|
||||
|
||||
gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>, /* 70 */
|
||||
<&gpio3 9 GPIO_ACTIVE_HIGH>, /* 73 */
|
||||
<&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
|
||||
<&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
|
||||
<&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
|
||||
gpio-names = "cmt_apeslpx",
|
||||
"cmt_rst_rq",
|
||||
"cmt_en",
|
||||
"cmt_rst",
|
||||
"cmt_bsi";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,97 @@
|
|||
OMAP SSI controller bindings
|
||||
|
||||
OMAP Synchronous Serial Interface (SSI) controller implements a legacy
|
||||
variant of MIPI's High Speed Synchronous Serial Interface (HSI).
|
||||
|
||||
Required properties:
|
||||
- compatible: Should include "ti,omap3-ssi".
|
||||
- reg-names: Contains the values "sys" and "gdd" (in this order).
|
||||
- reg: Contains a matching register specifier for each entry
|
||||
in reg-names.
|
||||
- interrupt-names: Contains the value "gdd_mpu".
|
||||
- interrupts: Contains matching interrupt information for each entry
|
||||
in interrupt-names.
|
||||
- ranges: Represents the bus address mapping between the main
|
||||
controller node and the child nodes below.
|
||||
- clock-names: Must include the following entries:
|
||||
"ssi_ssr_fck": The OMAP clock of that name
|
||||
"ssi_sst_fck": The OMAP clock of that name
|
||||
"ssi_ick": The OMAP clock of that name
|
||||
- clocks: Contains a matching clock specifier for each entry in
|
||||
clock-names.
|
||||
- #address-cells: Should be set to <1>
|
||||
- #size-cells: Should be set to <1>
|
||||
|
||||
Each port is represented as a sub-node of the ti,omap3-ssi device.
|
||||
|
||||
Required Port sub-node properties:
|
||||
- compatible: Should be set to the following value
|
||||
ti,omap3-ssi-port (applicable to OMAP34xx devices)
|
||||
- reg-names: Contains the values "tx" and "rx" (in this order).
|
||||
- reg: Contains a matching register specifier for each entry
|
||||
in reg-names.
|
||||
- interrupt-parent Should be a phandle for the interrupt controller
|
||||
- interrupts: Should contain interrupt specifiers for mpu interrupts
|
||||
0 and 1 (in this order).
|
||||
- ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE
|
||||
events for the port. This is an optional board-specific
|
||||
property. If it's missing the port will not be
|
||||
enabled.
|
||||
|
||||
Example for Nokia N900:
|
||||
|
||||
ssi-controller@48058000 {
|
||||
compatible = "ti,omap3-ssi";
|
||||
|
||||
/* needed until hwmod is updated to use the compatible string */
|
||||
ti,hwmods = "ssi";
|
||||
|
||||
reg = <0x48058000 0x1000>,
|
||||
<0x48059000 0x1000>;
|
||||
reg-names = "sys",
|
||||
"gdd";
|
||||
|
||||
interrupts = <55>;
|
||||
interrupt-names = "gdd_mpu";
|
||||
|
||||
clocks = <&ssi_ssr_fck>,
|
||||
<&ssi_sst_fck>,
|
||||
<&ssi_ick>;
|
||||
clock-names = "ssi_ssr_fck",
|
||||
"ssi_sst_fck",
|
||||
"ssi_ick";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
ssi-port@4805a000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805a000 0x800>,
|
||||
<0x4805a800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <67>,
|
||||
<68>;
|
||||
|
||||
ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
|
||||
}
|
||||
|
||||
ssi-port@4805a000 {
|
||||
compatible = "ti,omap3-ssi-port";
|
||||
|
||||
reg = <0x4805b000 0x800>,
|
||||
<0x4805b800 0x800>;
|
||||
reg-names = "tx",
|
||||
"rx";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <69>,
|
||||
<70>;
|
||||
|
||||
status = "disabled"; /* second port is not used on N900 */
|
||||
}
|
||||
}
|
|
@ -8,6 +8,12 @@ the standard I2C multi-master rules. Using GPIOs is generally useful in
|
|||
the case where there is a device on the bus that has errata and/or bugs
|
||||
that makes standard multimaster mode not feasible.
|
||||
|
||||
Note that this scheme works well enough but has some downsides:
|
||||
* It is nonstandard (not using standard I2C multimaster)
|
||||
* Having two masters on a bus in general makes it relatively hard to debug
|
||||
problems (hard to tell if i2c issues were caused by one master, another, or
|
||||
some device on the bus).
|
||||
|
||||
|
||||
Algorithm:
|
||||
|
||||
|
|
|
@ -0,0 +1,39 @@
|
|||
I2C bus that tunnels through the ChromeOS EC (cros-ec)
|
||||
======================================================
|
||||
On some ChromeOS board designs we've got a connection to the EC (embedded
|
||||
controller) but no direct connection to some devices on the other side of
|
||||
the EC (like a battery and PMIC). To get access to those devices we need
|
||||
to tunnel our i2c commands through the EC.
|
||||
|
||||
The node for this device should be under a cros-ec node like google,cros-ec-spi
|
||||
or google,cros-ec-i2c.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: google,cros-ec-i2c-tunnel
|
||||
- google,remote-bus: The EC bus we'd like to talk to.
|
||||
|
||||
Optional child nodes:
|
||||
- One node per I2C device connected to the tunnelled I2C bus.
|
||||
|
||||
|
||||
Example:
|
||||
cros-ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
|
||||
...
|
||||
|
||||
i2c-tunnel {
|
||||
compatible = "google,cros-ec-i2c-tunnel";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
google,remote-bus = <0>;
|
||||
|
||||
battery: sbs-battery@b {
|
||||
compatible = "sbs,sbs-battery";
|
||||
reg = <0xb>;
|
||||
sbs,poll-retry-count = <1>;
|
||||
};
|
||||
};
|
||||
}
|
|
@ -5,7 +5,14 @@ at various speeds ranging from 100khz to 3.4Mhz.
|
|||
|
||||
Required properties:
|
||||
- compatible: value should be.
|
||||
-> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.
|
||||
-> "samsung,exynos5-hsi2c", (DEPRECATED)
|
||||
for i2c compatible with HSI2C available
|
||||
on Exynos5250 and Exynos5420 SoCs.
|
||||
-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos5250 and Exynos5420 SoCs.
|
||||
-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos5260 SoCs.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
@ -26,7 +33,7 @@ Optional properties:
|
|||
Example:
|
||||
|
||||
hsi2c@12ca0000 {
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
compatible = "samsung,exynos5250-hsi2c";
|
||||
reg = <0x12ca0000 0x100>;
|
||||
interrupts = <56>;
|
||||
clock-frequency = <100000>;
|
||||
|
|
|
@ -5,7 +5,7 @@ Required properties :
|
|||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : Should be either:
|
||||
- "allwinner,sun4i-i2c"
|
||||
- "allwinner,sun4i-a10-i2c"
|
||||
- "allwinner,sun6i-a31-i2c"
|
||||
- "marvell,mv64xxx-i2c"
|
||||
- "marvell,mv78230-i2c"
|
||||
|
|
|
@ -7,6 +7,9 @@ Required properties:
|
|||
"renesas,i2c-r8a7779"
|
||||
"renesas,i2c-r8a7790"
|
||||
"renesas,i2c-r8a7791"
|
||||
"renesas,i2c-r8a7792"
|
||||
"renesas,i2c-r8a7793"
|
||||
"renesas,i2c-r8a7794"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt specifier.
|
||||
|
|
|
@ -0,0 +1,42 @@
|
|||
* Rockchip RK3xxx I2C controller
|
||||
|
||||
This driver interfaces with the native I2C controller present in Rockchip
|
||||
RK3xxx SoCs.
|
||||
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
|
||||
"rockchip,rk3288-i2c".
|
||||
- interrupts : interrupt number
|
||||
- clocks : parent clock
|
||||
|
||||
Required on RK3066, RK3188 :
|
||||
|
||||
- rockchip,grf : the phandle of the syscon node for the general register
|
||||
file (GRF)
|
||||
- on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
|
||||
is also required.
|
||||
|
||||
Optional properties :
|
||||
|
||||
- clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
|
||||
|
||||
Example:
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
}
|
||||
|
||||
i2c0: i2c@2002d000 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
reg = <0x2002d000 0x1000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C0>;
|
||||
};
|
|
@ -0,0 +1,26 @@
|
|||
Device tree configuration for Renesas IIC (sh_mobile) driver
|
||||
|
||||
Required properties:
|
||||
- compatible : "renesas,iic-<soctype>". "renesas,rmobile-iic" as fallback
|
||||
- reg : address start and address range size of device
|
||||
- interrupts : interrupt of device
|
||||
- clocks : clock for device
|
||||
- #address-cells : should be <1>
|
||||
- #size-cells : should be <0>
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset.
|
||||
|
||||
Pinctrl properties might be needed, too. See there.
|
||||
|
||||
Example:
|
||||
|
||||
iic0: i2c@e6500000 {
|
||||
compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6500000 0 0x425>;
|
||||
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
|
||||
clock-frequency = <400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
|
@ -0,0 +1,41 @@
|
|||
|
||||
* Allwinner P2WI (Push/Pull 2 Wire Interface) controller
|
||||
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device.
|
||||
- compatible : Should one of the following:
|
||||
- "allwinner,sun6i-a31-p2wi"
|
||||
- interrupts : The interrupt line connected to the P2WI peripheral.
|
||||
- clocks : The gate clk connected to the P2WI peripheral.
|
||||
- resets : The reset line connected to the P2WI peripheral.
|
||||
|
||||
Optional properties :
|
||||
|
||||
- clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the
|
||||
default frequency is 100kHz
|
||||
|
||||
A P2WI may contain one child node encoding a P2WI slave device.
|
||||
|
||||
Slave device properties:
|
||||
Required properties:
|
||||
- reg : the I2C slave address used during the initialization
|
||||
process to switch from I2C to P2WI mode
|
||||
|
||||
Example:
|
||||
|
||||
p2wi@01f03400 {
|
||||
compatible = "allwinner,sun6i-a31-p2wi";
|
||||
reg = <0x01f03400 0x400>;
|
||||
interrupts = <0 39 4>;
|
||||
clocks = <&apb0_gates 3>;
|
||||
clock-frequency = <6000000>;
|
||||
resets = <&apb0_rst 3>;
|
||||
|
||||
axp221: pmic@68 {
|
||||
compatible = "x-powers,axp221";
|
||||
reg = <0x68>;
|
||||
|
||||
/* ... */
|
||||
};
|
||||
};
|
|
@ -0,0 +1,28 @@
|
|||
Austrian Microsystems AS3935 Franklin lightning sensor device driver
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "ams,as3935"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-cpha: SPI Mode 1. Refer to spi/spi-bus.txt for generic SPI
|
||||
slave node bindings.
|
||||
- interrupt-parent : should be the phandle for the interrupt controller
|
||||
- interrupts : the sole interrupt generated by the device
|
||||
|
||||
Refer to interrupt-controller/interrupts.txt for generic
|
||||
interrupt client node bindings.
|
||||
|
||||
Optional properties:
|
||||
- ams,tuning-capacitor-pf: Calibration tuning capacitor stepping
|
||||
value 0 - 120pF. This will require using the calibration data from
|
||||
the manufacturer.
|
||||
|
||||
Example:
|
||||
|
||||
as3935@0 {
|
||||
compatible = "ams,as3935";
|
||||
reg = <0>;
|
||||
spi-cpha;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <16 1>;
|
||||
ams,tuning-capacitor-pf = <80>;
|
||||
};
|
|
@ -0,0 +1,60 @@
|
|||
* ST Keyscan controller Device Tree bindings
|
||||
|
||||
The ST keyscan controller Device Tree binding is based on the
|
||||
matrix-keymap.
|
||||
|
||||
Required properties:
|
||||
- compatible: "st,sti-keyscan"
|
||||
|
||||
- reg: Register base address and size of st-keyscan controller.
|
||||
|
||||
- interrupts: Interrupt number for the st-keyscan controller.
|
||||
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
- pinctrl: Should specify pin control groups used for this controller.
|
||||
See ../pinctrl/pinctrl-bindings.txt for details.
|
||||
|
||||
- linux,keymap: The keymap for keys as described in the binding document
|
||||
devicetree/bindings/input/matrix-keymap.txt.
|
||||
|
||||
- keypad,num-rows: Number of row lines connected to the keypad controller.
|
||||
|
||||
- keypad,num-columns: Number of column lines connected to the keypad
|
||||
controller.
|
||||
|
||||
Optional property:
|
||||
- st,debounce_us: Debouncing interval time in microseconds
|
||||
|
||||
Example:
|
||||
|
||||
keyscan: keyscan@fe4b0000 {
|
||||
compatible = "st,sti-keyscan";
|
||||
reg = <0xfe4b0000 0x2000>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
|
||||
clocks = <&CLK_SYSIN>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_keyscan>;
|
||||
|
||||
keypad,num-rows = <4>;
|
||||
keypad,num-columns = <4>;
|
||||
st,debounce_us = <5000>;
|
||||
|
||||
linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13)
|
||||
MATRIX_KEY(0x00, 0x01, KEY_F9)
|
||||
MATRIX_KEY(0x00, 0x02, KEY_F5)
|
||||
MATRIX_KEY(0x00, 0x03, KEY_F1)
|
||||
MATRIX_KEY(0x01, 0x00, KEY_F14)
|
||||
MATRIX_KEY(0x01, 0x01, KEY_F10)
|
||||
MATRIX_KEY(0x01, 0x02, KEY_F6)
|
||||
MATRIX_KEY(0x01, 0x03, KEY_F2)
|
||||
MATRIX_KEY(0x02, 0x00, KEY_F15)
|
||||
MATRIX_KEY(0x02, 0x01, KEY_F11)
|
||||
MATRIX_KEY(0x02, 0x02, KEY_F7)
|
||||
MATRIX_KEY(0x02, 0x03, KEY_F3)
|
||||
MATRIX_KEY(0x03, 0x00, KEY_F16)
|
||||
MATRIX_KEY(0x03, 0x01, KEY_F12)
|
||||
MATRIX_KEY(0x03, 0x02, KEY_F8)
|
||||
MATRIX_KEY(0x03, 0x03, KEY_F4) >;
|
||||
};
|
|
@ -0,0 +1,20 @@
|
|||
sun4i resistive touchscreen controller
|
||||
--------------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,sun4i-a10-ts"
|
||||
- reg: mmio address range of the chip
|
||||
- interrupts: interrupt to which the chip is connected
|
||||
|
||||
Optional properties:
|
||||
- allwinner,ts-attached: boolean indicating that an actual touchscreen is
|
||||
attached to the controller
|
||||
|
||||
Example:
|
||||
|
||||
rtp: rtp@01c25000 {
|
||||
compatible = "allwinner,sun4i-a10-ts";
|
||||
reg = <0x01c25000 0x100>;
|
||||
interrupts = <29>;
|
||||
allwinner,ts-attached;
|
||||
};
|
|
@ -0,0 +1,27 @@
|
|||
General Touchscreen Properties:
|
||||
|
||||
Optional properties for Touchscreens:
|
||||
- touchscreen-size-x : horizontal resolution of touchscreen
|
||||
(in pixels)
|
||||
- touchscreen-size-y : vertical resolution of touchscreen
|
||||
(in pixels)
|
||||
- touchscreen-max-pressure : maximum reported pressure (arbitrary range
|
||||
dependent on the controller)
|
||||
- touchscreen-fuzz-x : horizontal noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-fuzz-y : vertical noise value of the absolute input
|
||||
device (in pixels)
|
||||
- touchscreen-fuzz-pressure : pressure noise value of the absolute input
|
||||
device (arbitrary range dependent on the
|
||||
controller)
|
||||
- touchscreen-inverted-x : X axis is inverted (boolean)
|
||||
- touchscreen-inverted-y : Y axis is inverted (boolean)
|
||||
|
||||
Deprecated properties for Touchscreens:
|
||||
- x-size : deprecated name for touchscreen-size-x
|
||||
- y-size : deprecated name for touchscreen-size-y
|
||||
- moving-threshold : deprecated name for a combination of
|
||||
touchscreen-fuzz-x and touchscreen-fuzz-y
|
||||
- contact-threshold : deprecated name for touchscreen-fuzz-pressure
|
||||
- x-invert : deprecated name for touchscreen-inverted-x
|
||||
- y-invert : deprecated name for touchscreen-inverted-y
|
|
@ -0,0 +1,42 @@
|
|||
* Texas Instruments tsc2005 touchscreen controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "ti,tsc2005"
|
||||
- reg : SPI device address
|
||||
- spi-max-frequency : Maximal SPI speed
|
||||
- interrupts : IRQ specifier
|
||||
- reset-gpios : GPIO specifier
|
||||
- vio-supply : Regulator specifier
|
||||
|
||||
Optional properties:
|
||||
- ti,x-plate-ohms : integer, resistance of the touchscreen's X plates
|
||||
in ohm (defaults to 280)
|
||||
- ti,esd-recovery-timeout-ms : integer, if the touchscreen does not respond after
|
||||
the configured time (in milli seconds), the driver
|
||||
will reset it. This is disabled by default.
|
||||
- properties defined in touchscreen.txt
|
||||
|
||||
Example:
|
||||
|
||||
&mcspi1 {
|
||||
tsc2005@0 {
|
||||
compatible = "ti,tsc2005";
|
||||
spi-max-frequency = <6000000>;
|
||||
reg = <0>;
|
||||
|
||||
vio-supply = <&vio>;
|
||||
|
||||
reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
|
||||
interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>; /* 100 */
|
||||
|
||||
touchscreen-fuzz-x = <4>;
|
||||
touchscreen-fuzz-y = <7>;
|
||||
touchscreen-fuzz-pressure = <2>;
|
||||
touchscreen-max-x = <4096>;
|
||||
touchscreen-max-y = <4096>;
|
||||
touchscreen-max-pressure = <2048>;
|
||||
|
||||
ti,x-plate-ohms = <280>;
|
||||
ti,esd-recovery-timeout-ms = <8000>;
|
||||
};
|
||||
}
|
|
@ -0,0 +1,29 @@
|
|||
Broadcom Generic Level 2 Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "brcm,l2-intc"
|
||||
- reg: specifies the base physical address and size of the registers
|
||||
- interrupt-controller: identifies the node as an interrupt controller
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an
|
||||
interrupt source. Should be 1.
|
||||
- interrupt-parent: specifies the phandle to the parent interrupt controller
|
||||
this controller is cacaded from
|
||||
- interrupts: specifies the interrupt line in the interrupt-parent irq space
|
||||
to be used for cascading
|
||||
|
||||
Optional properties:
|
||||
|
||||
- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
|
||||
wakeup source for system suspend/resume.
|
||||
|
||||
Example:
|
||||
|
||||
hif_intr2_intc: interrupt-controller@f0441000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0xf0441000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0x0 0x20 0x0>;
|
||||
};
|
|
@ -0,0 +1,70 @@
|
|||
Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
|
||||
|
||||
Samsung's Exynos architecture contains System MMUs that enables scattered
|
||||
physical memory chunks visible as a contiguous region to DMA-capable peripheral
|
||||
devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
|
||||
|
||||
System MMU is an IOMMU and supports identical translation table format to
|
||||
ARMv7 translation tables with minimum set of page properties including access
|
||||
permissions, shareability and security protection. In addition, System MMU has
|
||||
another capabilities like L2 TLB or block-fetch buffers to minimize translation
|
||||
latency.
|
||||
|
||||
System MMUs are in many to one relation with peripheral devices, i.e. single
|
||||
peripheral device might have multiple System MMUs (usually one for each bus
|
||||
master), but one System MMU can handle transactions from only one peripheral
|
||||
device. The relation between a System MMU and the peripheral device needs to be
|
||||
defined in device node of the peripheral device.
|
||||
|
||||
MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
|
||||
MMUs.
|
||||
* MFC has one System MMU on its left and right bus.
|
||||
* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
|
||||
for window 1, 2 and 3.
|
||||
* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
|
||||
the other System MMU on the write channel.
|
||||
The drivers must consider how to handle those System MMUs. One of the idea is
|
||||
to implement child devices or sub-devices which are the client devices of the
|
||||
System MMU.
|
||||
|
||||
Note:
|
||||
The current DT binding for the Exynos System MMU is incomplete.
|
||||
The following properties can be removed or changed, if found incompatible with
|
||||
the "Generic IOMMU Binding" support for attaching devices to the IOMMU.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,exynos-sysmmu"
|
||||
- reg: A tuple of base address and size of System MMU registers.
|
||||
- interrupt-parent: The phandle of the interrupt controller of System MMU
|
||||
- interrupts: An interrupt specifier for interrupt signal of System MMU,
|
||||
according to the format defined by a particular interrupt
|
||||
controller.
|
||||
- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
|
||||
Optional "master" if the clock to the System MMU is gated by
|
||||
another gate clock other than "sysmmu".
|
||||
Exynos4 SoCs, there needs no "master" clock.
|
||||
Exynos5 SoCs, some System MMUs must have "master" clocks.
|
||||
- clocks: Required if the System MMU is needed to gate its clock.
|
||||
- samsung,power-domain: Required if the System MMU is needed to gate its power.
|
||||
Please refer to the following document:
|
||||
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
|
||||
|
||||
Examples:
|
||||
gsc_0: gsc@13e00000 {
|
||||
compatible = "samsung,exynos5-gsc";
|
||||
reg = <0x13e00000 0x1000>;
|
||||
interrupts = <0 85 0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
clocks = <&clock CLK_GSCL0>;
|
||||
clock-names = "gscl";
|
||||
};
|
||||
|
||||
sysmmu_gsc0: sysmmu@13E80000 {
|
||||
compatible = "samsung,exynos-sysmmu";
|
||||
reg = <0x13E80000 0x1000>;
|
||||
interrupt-parent = <&combiner>;
|
||||
interrupts = <2 0>;
|
||||
clock-names = "sysmmu", "master";
|
||||
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
|
||||
samsung,power-domain = <&pd_gsc>;
|
||||
};
|
|
@ -1,7 +1,13 @@
|
|||
Binding for TI/National Semiconductor LP55xx Led Drivers
|
||||
|
||||
Required properties:
|
||||
- compatible: "national,lp5521" or "national,lp5523" or "ti,lp5562" or "ti,lp8501"
|
||||
- compatible: one of
|
||||
national,lp5521
|
||||
national,lp5523
|
||||
ti,lp55231
|
||||
ti,lp5562
|
||||
ti,lp8501
|
||||
|
||||
- reg: I2C slave address
|
||||
- clock-mode: Input clock mode, (0: automode, 1: internal, 2: external)
|
||||
|
||||
|
|
|
@ -13,6 +13,8 @@ LED sub-node properties:
|
|||
For the pwms and pwm-names property please refer to:
|
||||
Documentation/devicetree/bindings/pwm/pwm.txt
|
||||
- max-brightness : Maximum brightness possible for the LED
|
||||
- active-low : (optional) For PWMs where the LED is wired to supply
|
||||
rather than ground.
|
||||
- label : (optional)
|
||||
see Documentation/devicetree/bindings/leds/common.txt
|
||||
- linux,default-trigger : (optional)
|
||||
|
|
|
@ -0,0 +1,70 @@
|
|||
* Analog Devices ADV7604/11 video decoder with HDMI receiver
|
||||
|
||||
The ADV7604 and ADV7611 are multiformat video decoders with an integrated HDMI
|
||||
receiver. The ADV7604 has four multiplexed HDMI inputs and one analog input,
|
||||
and the ADV7611 has one HDMI input and no analog input.
|
||||
|
||||
These device tree bindings support the ADV7611 only at the moment.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must contain one of the following
|
||||
- "adi,adv7611" for the ADV7611
|
||||
|
||||
- reg: I2C slave address
|
||||
|
||||
- hpd-gpios: References to the GPIOs that control the HDMI hot-plug
|
||||
detection pins, one per HDMI input. The active flag indicates the GPIO
|
||||
level that enables hot-plug detection.
|
||||
|
||||
The device node must contain one 'port' child node per device input and output
|
||||
port, in accordance with the video interface bindings defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
|
||||
are numbered as follows.
|
||||
|
||||
Port ADV7611
|
||||
------------------------------------------------------------
|
||||
HDMI 0
|
||||
Digital output 1
|
||||
|
||||
The digital output port node must contain at least one endpoint.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- reset-gpios: Reference to the GPIO connected to the device's reset pin.
|
||||
|
||||
Optional Endpoint Properties:
|
||||
|
||||
The following three properties are defined in video-interfaces.txt and are
|
||||
valid for source endpoints only.
|
||||
|
||||
- hsync-active: Horizontal synchronization polarity. Defaults to active low.
|
||||
- vsync-active: Vertical synchronization polarity. Defaults to active low.
|
||||
- pclk-sample: Pixel clock polarity. Defaults to output on the falling edge.
|
||||
|
||||
If none of hsync-active, vsync-active and pclk-sample is specified the
|
||||
endpoint will use embedded BT.656 synchronization.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
hdmi_receiver@4c {
|
||||
compatible = "adi,adv7611";
|
||||
reg = <0x4c>;
|
||||
|
||||
reset-gpios = <&ioexp 0 GPIO_ACTIVE_LOW>;
|
||||
hpd-gpios = <&ioexp 2 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi_in: endpoint {
|
||||
remote-endpoint = <&ccdc_in>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,43 @@
|
|||
* Renesas VSP1 Video Processing Engine
|
||||
|
||||
The VSP1 is a video processing engine that supports up-/down-scaling, alpha
|
||||
blending, color space conversion and various other image processing features.
|
||||
It can be found in the Renesas R-Car second generation SoCs.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must contain "renesas,vsp1"
|
||||
|
||||
- reg: Base address and length of the registers block for the VSP1.
|
||||
- interrupts: VSP1 interrupt specifier.
|
||||
- clocks: A phandle + clock-specifier pair for the VSP1 functional clock.
|
||||
|
||||
- renesas,#rpf: Number of Read Pixel Formatter (RPF) modules in the VSP1.
|
||||
- renesas,#uds: Number of Up Down Scaler (UDS) modules in the VSP1.
|
||||
- renesas,#wpf: Number of Write Pixel Formatter (WPF) modules in the VSP1.
|
||||
|
||||
|
||||
Optional properties:
|
||||
|
||||
- renesas,has-lif: Boolean, indicates that the LCD Interface (LIF) module is
|
||||
available.
|
||||
- renesas,has-lut: Boolean, indicates that the Look Up Table (LUT) module is
|
||||
available.
|
||||
- renesas,has-sru: Boolean, indicates that the Super Resolution Unit (SRU)
|
||||
module is available.
|
||||
|
||||
|
||||
Example: R8A7790 (R-Car H2) VSP1-S node
|
||||
|
||||
vsp1@fe928000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
|
||||
|
||||
renesas,has-lut;
|
||||
renesas,has-sru;
|
||||
renesas,#rpf = <5>;
|
||||
renesas,#uds = <3>;
|
||||
renesas,#wpf = <4>;
|
||||
};
|
|
@ -10,7 +10,8 @@ Required properties:
|
|||
- compatible : value should be either one among the following
|
||||
(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
|
||||
(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
|
||||
(b) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
|
||||
(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
|
||||
(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
|
|
@ -6,10 +6,11 @@ The actual devices are instantiated from the child nodes of a Device Bus node.
|
|||
|
||||
Required properties:
|
||||
|
||||
- compatible: Currently only Armada 370/XP SoC are supported,
|
||||
with this compatible string:
|
||||
- compatible: Armada 370/XP SoC are supported using the
|
||||
"marvell,mvebu-devbus" compatible string.
|
||||
|
||||
marvell,mvebu-devbus
|
||||
Orion5x SoC are supported using the
|
||||
"marvell,orion-devbus" compatible string.
|
||||
|
||||
- reg: A resource specifier for the register space.
|
||||
This is the base address of a chip select within
|
||||
|
@ -22,7 +23,14 @@ Required properties:
|
|||
integer values for each chip-select line in use:
|
||||
0 <physical address of mapping> <size>
|
||||
|
||||
Mandatory timing properties for child nodes:
|
||||
Optional properties:
|
||||
|
||||
- devbus,keep-config This property can optionally be used to keep
|
||||
using the timing parameters set by the
|
||||
bootloader. It makes all the timing properties
|
||||
described below unused.
|
||||
|
||||
Timing properties for child nodes:
|
||||
|
||||
Read parameters:
|
||||
|
||||
|
@ -30,21 +38,26 @@ Read parameters:
|
|||
drive the AD bus after the completion of a device read.
|
||||
This prevents contentions on the Device Bus after a read
|
||||
cycle from a slow device.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,bus-width: Defines the bus width (e.g. <16>)
|
||||
- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
|
||||
to read data sample. This parameter is useful for
|
||||
synchronous pipelined devices, where the address
|
||||
precedes the read data by one or two cycles.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,acc-first-ps: Defines the time delay from the negation of
|
||||
ALE[0] to the cycle that the first read data is sampled
|
||||
by the controller.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,acc-next-ps: Defines the time delay between the cycle that
|
||||
samples data N and the cycle that samples data N+1
|
||||
(in burst accesses).
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
|
||||
DEV_OEn assertion. If set to 0 (default),
|
||||
|
@ -52,6 +65,8 @@ Read parameters:
|
|||
This parameter has no affect on <acc-first-ps> parameter
|
||||
(no affect on first data sample). Set <rd-setup-ps>
|
||||
to a value smaller than <acc-first-ps>.
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
- devbus,rd-hold-ps: Defines the time between the last data sample to the
|
||||
de-assertion of DEV_CSn. If set to 0 (default),
|
||||
|
@ -62,16 +77,20 @@ Read parameters:
|
|||
last data sampled. Also this parameter has no
|
||||
affect on <turn-off-ps> parameter.
|
||||
Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
Write parameters:
|
||||
|
||||
- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
|
||||
to the DEV_WEn assertion.
|
||||
Mandatory.
|
||||
|
||||
- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
|
||||
A[2:0] and Data are kept valid as long as DEV_WEn
|
||||
is active. This parameter defines the setup time of
|
||||
address and data to DEV_WEn rise.
|
||||
Mandatory.
|
||||
|
||||
- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
|
||||
inactive (high) between data beats of a burst write.
|
||||
|
@ -79,10 +98,13 @@ Write parameters:
|
|||
<wr-high-ps> - <tick> ps.
|
||||
This parameter defines the hold time of address and
|
||||
data after DEV_WEn rise.
|
||||
Mandatory.
|
||||
|
||||
- devbus,sync-enable: Synchronous device enable.
|
||||
1: True
|
||||
0: False
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
An example for an Armada XP GP board, with a 16 MiB NOR device as child
|
||||
is showed below. Note that the Device Bus driver is in charge of allocating
|
||||
|
|
|
@ -19,7 +19,9 @@ Optional child nodes:
|
|||
The valid regulator node names for BCM59056 are:
|
||||
rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo,
|
||||
mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo,
|
||||
csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr
|
||||
csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
|
||||
gpldo1, gpldo2, gpldo3, gpldo4, gpldo5, gpldo6,
|
||||
vbus
|
||||
|
||||
Example:
|
||||
pmu: bcm59056@8 {
|
||||
|
|
|
@ -0,0 +1,25 @@
|
|||
KEYMILE bfticu Chassis Management FPGA
|
||||
|
||||
The bfticu is a multifunction device that manages the whole chassis.
|
||||
Its main functionality is to collect IRQs from the whole chassis and signals
|
||||
them to a single controller.
|
||||
|
||||
Required properties:
|
||||
- compatible: "keymile,bfticu"
|
||||
- interrupt-controller: the bfticu FPGA is an interrupt controller
|
||||
- interrupts: the main IRQ line to signal the collected IRQs
|
||||
- #interrupt-cells : is 2 and their usage is compliant to the 2 cells variant
|
||||
of Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- interrupt-parent: the parent IRQ ctrl the main IRQ is connected to
|
||||
- reg: access on the parent local bus (chip select, offset in chip select, size)
|
||||
|
||||
Example:
|
||||
|
||||
chassis-mgmt@3,0 {
|
||||
compatible = "keymile,bfticu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <3 0 0x100>;
|
||||
interrupt-parent = <&mpic>;
|
||||
interrupts = <6 1 0 0>;
|
||||
};
|
|
@ -10,6 +10,9 @@ Optional properties:
|
|||
- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
|
||||
|
||||
Sub-nodes:
|
||||
- codec: Contain the Audio Codec node.
|
||||
- adc-port: Contain PMIC SSI port number used for ADC.
|
||||
- dac-port: Contain PMIC SSI port number used for DAC.
|
||||
- leds : Contain the led nodes and initial register values in property
|
||||
"led-control". Number of register depends of used IC, for MC13783 is 6,
|
||||
for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of
|
||||
|
|
|
@ -0,0 +1,17 @@
|
|||
KEYMILE qrio Board Control CPLD
|
||||
|
||||
The qrio is a multifunction device that controls the KEYMILE boards based on
|
||||
the kmp204x design.
|
||||
It is consists of a reset controller, watchdog timer, LEDs, and 2 IRQ capable
|
||||
GPIO blocks.
|
||||
|
||||
Required properties:
|
||||
- compatible: "keymile,qriox"
|
||||
- reg: access on the parent local bus (chip select, offset in chip select, size)
|
||||
|
||||
Example:
|
||||
|
||||
board-control@1,0 {
|
||||
compatible = "keymile,qriox";
|
||||
reg = <1 0 0x80>;
|
||||
};
|
|
@ -56,6 +56,20 @@ for a particular group of BUCKs. So provide same regulator-ramp-delay<value>.
|
|||
Grouping of BUCKs sharing ramp rate setting is as follow : BUCK[1, 6],
|
||||
BUCK[3, 4], and BUCK[7, 8, 10]
|
||||
|
||||
On S2MPS14 the LDO10, LDO11 and LDO12 can be configured to external control
|
||||
over GPIO. To turn this feature on this property must be added to the regulator
|
||||
sub-node:
|
||||
- samsung,ext-control-gpios: GPIO specifier for one GPIO
|
||||
controlling this regulator (enable/disable);
|
||||
Example:
|
||||
LDO12 {
|
||||
regulator-name = "V_EMMC_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
samsung,ext-control-gpios = <&gpk0 2 0>;
|
||||
};
|
||||
|
||||
|
||||
The regulator constraints inside the regulator nodes use the standard regulator
|
||||
bindings which are documented elsewhere.
|
||||
|
||||
|
|
|
@ -0,0 +1,59 @@
|
|||
* Allwinner PRCM (Power/Reset/Clock Management) Multi-Functional Device
|
||||
|
||||
PRCM is an MFD device exposing several Power Management related devices
|
||||
(like clks and reset controllers).
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,sun6i-a31-prcm"
|
||||
- reg: The PRCM registers range
|
||||
|
||||
The prcm node may contain several subdevices definitions:
|
||||
- see Documentation/devicetree/clk/sunxi.txt for clock devices
|
||||
- see Documentation/devicetree/reset/allwinner,sunxi-clock-reset.txt for reset
|
||||
controller devices
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
prcm: prcm@01f01400 {
|
||||
compatible = "allwinner,sun6i-a31-prcm";
|
||||
reg = <0x01f01400 0x200>;
|
||||
|
||||
/* Put subdevices here */
|
||||
ar100: ar100_clk {
|
||||
compatible = "allwinner,sun6i-a31-ar100-clk";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
|
||||
};
|
||||
|
||||
ahb0: ahb0_clk {
|
||||
compatible = "fixed-factor-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&ar100_div>;
|
||||
clock-output-names = "ahb0";
|
||||
};
|
||||
|
||||
apb0: apb0_clk {
|
||||
compatible = "allwinner,sun6i-a31-apb0-clk";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&ahb0>;
|
||||
clock-output-names = "apb0";
|
||||
};
|
||||
|
||||
apb0_gates: apb0_gates_clk {
|
||||
compatible = "allwinner,sun6i-a31-apb0-gates-clk";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&apb0>;
|
||||
clock-output-names = "apb0_pio", "apb0_ir",
|
||||
"apb0_timer01", "apb0_p2wi",
|
||||
"apb0_uart", "apb0_1wire",
|
||||
"apb0_i2c";
|
||||
};
|
||||
|
||||
apb0_rst: apb0_rst {
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
|
@ -0,0 +1,19 @@
|
|||
* Device tree bindings for Texas Instruments keystone device state control
|
||||
|
||||
The Keystone II devices have a set of registers that are used to control
|
||||
the status of its peripherals. This node is intended to allow access to
|
||||
this functionality.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,keystone-devctrl", "syscon"
|
||||
|
||||
- reg: contains offset/length value for device state control
|
||||
registers space.
|
||||
|
||||
Example:
|
||||
|
||||
devctrl: device-state-control@0x02620000 {
|
||||
compatible = "ti,keystone-devctrl", "syscon";
|
||||
reg = <0x02620000 0x1000>;
|
||||
};
|
|
@ -5,7 +5,22 @@ to control the power resources, including power scripts. For now, the
|
|||
binding only supports the complete shutdown of the system after poweroff.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "ti,twl4030-power"
|
||||
- compatible : must be one of the following
|
||||
"ti,twl4030-power"
|
||||
"ti,twl4030-power-reset"
|
||||
"ti,twl4030-power-idle"
|
||||
"ti,twl4030-power-idle-osc-off"
|
||||
|
||||
The use of ti,twl4030-power-reset is recommended at least on
|
||||
3530 that needs a special configuration for warm reset to work.
|
||||
|
||||
When using ti,twl4030-power-idle, the TI recommended configuration
|
||||
for idle modes is loaded to the tlw4030 PMIC.
|
||||
|
||||
When using ti,twl4030-power-idle-osc-off, the TI recommended
|
||||
configuration is used with the external oscillator being shut
|
||||
down during off-idle. Note that this does not work on all boards
|
||||
depending on how the external oscillator is wired.
|
||||
|
||||
Optional properties:
|
||||
- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
|
||||
|
|
|
@ -19,6 +19,8 @@ Required properties:
|
|||
|
||||
Optional properties, nodes:
|
||||
- enable-active-high: To power on the twl6040 during boot.
|
||||
- clocks: phandle to the clk32k clock provider
|
||||
- clock-names: Must be "clk32k"
|
||||
|
||||
Vibra functionality
|
||||
Required properties:
|
||||
|
|
|
@ -0,0 +1,18 @@
|
|||
ARM Versatile Character LCD
|
||||
-----------------------------------------------------
|
||||
This binding defines the character LCD interface found on ARM Versatile AB
|
||||
and PB reference platforms.
|
||||
|
||||
Required properties:
|
||||
- compatible : "arm,versatile-clcd"
|
||||
- reg : Location and size of character LCD registers
|
||||
|
||||
Optional properties:
|
||||
- interrupts - single interrupt for character LCD. The character LCD can
|
||||
operate in polled mode without an interrupt.
|
||||
|
||||
Example:
|
||||
lcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
};
|
|
@ -12,7 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
|
|||
Required Properties:
|
||||
|
||||
* compatible: should be one of the following.
|
||||
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extentions.
|
||||
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -38,6 +38,8 @@ Optional properties:
|
|||
- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
|
||||
- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
|
||||
- mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
|
||||
- mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
|
||||
- mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
|
||||
|
||||
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
|
||||
polarity properties, we have to fix the meaning of the "normal" and "inverted"
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue