dts: update to v3.16-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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* Rockchip RK3xxx I2C controller
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This driver interfaces with the native I2C controller present in Rockchip
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RK3xxx SoCs.
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Required properties :
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- reg : Offset and length of the register set for the device
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- compatible : should be "rockchip,rk3066-i2c", "rockchip,rk3188-i2c" or
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"rockchip,rk3288-i2c".
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- interrupts : interrupt number
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- clocks : parent clock
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Required on RK3066, RK3188 :
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- rockchip,grf : the phandle of the syscon node for the general register
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file (GRF)
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- on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
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is also required.
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Optional properties :
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- clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
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Example:
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aliases {
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i2c0 = &i2c0;
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}
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i2c0: i2c@2002d000 {
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compatible = "rockchip,rk3188-i2c";
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reg = <0x2002d000 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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rockchip,grf = <&grf>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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};
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@ -0,0 +1,41 @@
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* Allwinner P2WI (Push/Pull 2 Wire Interface) controller
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Required properties :
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- reg : Offset and length of the register set for the device.
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- compatible : Should one of the following:
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- "allwinner,sun6i-a31-p2wi"
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- interrupts : The interrupt line connected to the P2WI peripheral.
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- clocks : The gate clk connected to the P2WI peripheral.
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- resets : The reset line connected to the P2WI peripheral.
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Optional properties :
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- clock-frequency : Desired P2WI bus clock frequency in Hz. If not set the
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default frequency is 100kHz
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A P2WI may contain one child node encoding a P2WI slave device.
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Slave device properties:
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Required properties:
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- reg : the I2C slave address used during the initialization
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process to switch from I2C to P2WI mode
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Example:
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p2wi@01f03400 {
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compatible = "allwinner,sun6i-a31-p2wi";
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reg = <0x01f03400 0x400>;
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interrupts = <0 39 4>;
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clocks = <&apb0_gates 3>;
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clock-frequency = <6000000>;
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resets = <&apb0_rst 3>;
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axp221: pmic@68 {
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compatible = "x-powers,axp221";
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reg = <0x68>;
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/* ... */
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};
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};
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@ -91,6 +91,8 @@
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "U-Boot";
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@ -98,6 +98,8 @@
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "U-Boot";
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@ -25,7 +25,7 @@
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
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reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
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};
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soc {
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@ -24,3 +24,7 @@
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reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
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};
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};
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&serial0 {
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status = "ok";
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};
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@ -273,8 +273,9 @@
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};
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serial0: serial@1c020000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550";
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compatible = "ns16550a";
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reg = <0 0x1c020000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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@ -282,6 +283,39 @@
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interrupts = <0x0 0x4c 0x4>;
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};
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serial1: serial@1c021000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c021000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4d 0x4>;
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};
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serial2: serial@1c022000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c022000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4e 0x4>;
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};
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serial3: serial@1c023000 {
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status = "disabled";
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device_type = "serial";
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compatible = "ns16550a";
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reg = <0 0x1c023000 0x0 0x1000>;
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reg-shift = <2>;
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clock-frequency = <10000000>; /* Updated by bootloader */
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x4f 0x4>;
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};
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phy1: phy@1f21a000 {
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compatible = "apm,xgene-phy";
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reg = <0x0 0x1f21a000 0x0 0x100>;
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