drm/radeon: flush read cache for gtt with fence on r6xx and newer GPU
svn path=/dists/sid/linux-2.6/; revision=18428
This commit is contained in:
Ben Hutchings
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576fc1b72c
commit
e3c3cf2822
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@ -3,6 +3,8 @@ linux-2.6 (3.1.6-2) UNRELEASED; urgency=low
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[ Ben Hutchings ]
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* snapshot: Implement compat_ioctl (Closes: #502816)
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* iwlwifi: allow to switch to HT40 if not associated (Closes: #653423)
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* drm/radeon: flush read cache for gtt with fence on r6xx and newer GPU
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(Closes: #646376)
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[ Jonathan Nieder ]
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* prerm: Print an error message when aborting removal of the running
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96
debian/patches/bugfix/all/drm-radeon-flush-read-cache-for-gtt-with-fence-on-r6.patch
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96
debian/patches/bugfix/all/drm-radeon-flush-read-cache-for-gtt-with-fence-on-r6.patch
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@ -0,0 +1,96 @@
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From: Jerome Glisse <jglisse@redhat.com>
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Date: Wed, 26 Oct 2011 11:41:22 -0400
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Subject: [PATCH] drm/radeon: flush read cache for gtt with fence on r6xx and
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newer GPU V3
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commit 77b1bad423599c9841ea282a82172f039bb2ff92 upstream.
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Cayman seems to be particularly sensitive to read cache returning
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old data after bind/unbind to GTT. Flush read cache for GTT range
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with each fences for all new hw. Should fix several rendering glitches.
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Like
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V2 flush whole address space
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V3 also flush shader read cache
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https://bugs.freedesktop.org/show_bug.cgi?id=40221
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https://bugs.freedesktop.org/show_bug.cgi?id=38022
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https://bugzilla.redhat.com/show_bug.cgi?id=738790
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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Signed-off-by: Dave Airlie <airlied@redhat.com>
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[bwh: For 3.1, patch ring size numbers in {r600,evergreen}_blit_prepare_copy()
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instead of {r600,evergreen}_blit_init().]
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---
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drivers/gpu/drm/radeon/evergreen_blit_kms.c | 4 ++--
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drivers/gpu/drm/radeon/r600.c | 16 ++++++++++++++++
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drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++--
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3 files changed, 20 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
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index 551e76f..914e5af 100644
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--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
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+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
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@@ -779,9 +779,9 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev,
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 55; /* shaders + def state */
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- ring_size += 10; /* fence emit for VB IB */
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+ ring_size += 16; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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- ring_size += 10; /* fence emit for done copy */
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+ ring_size += 16; /* fence emit for done copy */
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r = radeon_ring_lock(rdev, ring_size);
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if (r)
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return r;
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diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
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index 12470b0..1f007ad 100644
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--- a/drivers/gpu/drm/radeon/r600.c
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+++ b/drivers/gpu/drm/radeon/r600.c
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@@ -2331,6 +2331,14 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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if (rdev->wb.use_event) {
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u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
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(u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
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+ /* flush read cache over gart */
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+ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
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+ radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
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+ PACKET3_VC_ACTION_ENA |
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+ PACKET3_SH_ACTION_ENA);
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+ radeon_ring_write(rdev, 0xFFFFFFFF);
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+ radeon_ring_write(rdev, 0);
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+ radeon_ring_write(rdev, 10); /* poll interval */
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/* EVENT_WRITE_EOP - flush caches, send int */
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radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
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radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
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@@ -2339,6 +2347,14 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(rdev, fence->seq);
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radeon_ring_write(rdev, 0);
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} else {
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+ /* flush read cache over gart */
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+ radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
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+ radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA |
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+ PACKET3_VC_ACTION_ENA |
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+ PACKET3_SH_ACTION_ENA);
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+ radeon_ring_write(rdev, 0xFFFFFFFF);
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+ radeon_ring_write(rdev, 0);
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+ radeon_ring_write(rdev, 10); /* poll interval */
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radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
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radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
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/* wait for 3D idle clean */
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diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
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index ff36532..e09d281 100644
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--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
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+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
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@@ -632,9 +632,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev,
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 40; /* shaders + def state */
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- ring_size += 10; /* fence emit for VB IB */
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+ ring_size += 16; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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- ring_size += 10; /* fence emit for done copy */
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+ ring_size += 16; /* fence emit for done copy */
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r = radeon_ring_lock(rdev, ring_size);
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if (r)
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return r;
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@ -88,3 +88,4 @@
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+ bugfix/all/cciss-Add-IRQF_SHARED-back-in-for-the-non-MSI-X-inte.patch
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+ bugfix/all/snapshot-Implement-compat_ioctl.patch
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+ bugfix/all/iwlwifi-allow-to-switch-to-ht40-if-not-associated.patch
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+ bugfix/all/drm-radeon-flush-read-cache-for-gtt-with-fence-on-r6.patch
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