[x86] drm/i915:: Disable FBC on SandyBridge (Closes: #675022)
svn path=/dists/sid/linux-2.6/; revision=19046
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@ -7,6 +7,7 @@ linux-2.6 (3.2.18-2) UNRELEASED; urgency=low
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* net/sched: Add codel and fq_codel from Linux 3.5-rc1
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* net/sched: Add codel and fq_codel from Linux 3.5-rc1
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* [x86] udeb: Add hyperv-modules containing Hyper-V paravirtualised drivers
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* [x86] udeb: Add hyperv-modules containing Hyper-V paravirtualised drivers
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* [x86] ata_piix: defer disks to the Hyper-V drivers by default
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* [x86] ata_piix: defer disks to the Hyper-V drivers by default
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* [x86] drm/i915:: Disable FBC on SandyBridge (Closes: #675022)
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-- Ben Hutchings <ben@decadent.org.uk> Sun, 27 May 2012 01:12:44 +0100
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-- Ben Hutchings <ben@decadent.org.uk> Sun, 27 May 2012 01:12:44 +0100
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@ -0,0 +1,32 @@
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From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Tue, 8 Nov 2011 23:17:34 +0000
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Subject: [PATCH] drm/i915:: Disable FBC on SandyBridge
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commit d56d8b28e9247e7e35e02fbb12b12239a2c33ad1 upstream.
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Enabling FBC is causing the BLT ring to run between 10-100x slower than
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normal and frequently lockup. The interim solution is disable FBC once
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more until we know why.
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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---
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drivers/gpu/drm/i915/intel_display.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
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index b3b51c4..19f35ec 100644
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--- a/drivers/gpu/drm/i915/intel_display.c
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+++ b/drivers/gpu/drm/i915/intel_display.c
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@@ -1872,7 +1872,7 @@ static void intel_update_fbc(struct drm_device *dev)
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if (enable_fbc < 0) {
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DRM_DEBUG_KMS("fbc set to per-chip default\n");
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enable_fbc = 1;
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- if (INTEL_INFO(dev)->gen <= 5)
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+ if (INTEL_INFO(dev)->gen <= 6)
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enable_fbc = 0;
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}
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if (!enable_fbc) {
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--
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1.7.10
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@ -307,3 +307,5 @@
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+ features/all/codel/0005-net-codel-fix-build-errors.patch
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+ features/all/codel/0005-net-codel-fix-build-errors.patch
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+ features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch
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+ features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch
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+ features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch
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+ features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch
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+ bugfix/all/drm-i915-Disable-FBC-on-SandyBridge.patch
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