[armhf] mvebu: do not register custom DMA operations when coherency is disabled
(Closes: #780858) svn path=/dists/sid/linux/; revision=22457
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@ -3,6 +3,8 @@ linux (3.16.7-ckt7-2) UNRELEASED; urgency=medium
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[ Ian Campbell ]
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* Initialise framebuffer console earlier. (Closes: #779935)
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* [xen] Enable Xen MCE log support. (Closes: #779698)
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* [armhf] mvebu: do not register custom DMA operations when coherency is
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disabled (Closes: #780858)
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-- Ian Campbell <ijc@debian.org> Wed, 18 Mar 2015 21:07:15 +0000
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@ -0,0 +1,57 @@
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu Mar 12 03:58:12 PDT 2015
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Subject: [PATCH 3.18-stable v2] ARM: mvebu: do not register custom DMA operations when coherency is disabled
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Origin: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330108.html
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This patch is a partial backport of commit ef01c6c36bb8 ("ARM: mvebu:
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remove Armada 375 Z1 workaround for I/O coherency"). This commit was
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merged in v3.19, so kernel versions later than v3.19 are not affected
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by the problem that this commit fixes.
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It does not make a lot of sense to backport this commit entirely,
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since it is mainly removing some no longer useful code. However, this
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commit is also making sure that the bus_register_notifier that
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register the custom DMA operations that should be used for HW I/O
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coherency does not get registered when said HW I/O coherency is not
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enabled.
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This is particularly critical since we have decided to disable HW I/O
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coherency completely in all kernels < 4.0, to be on the safe side,
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while experimenting a new implementation of the HW I/O coherency in >=
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4.0.
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Without this commit, kernels earlier than 3.18 have the custom DMA
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operations normally used for HW I/O coherency registered (they don't
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do cache maintenance operations), while HW I/O coherency is
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disabled. It essentially causes every DMA transfer to transfer
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garbage.
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The issue fixed by this commit was introduced by 5ab5afd8ba83 ("ARM:
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mvebu: implement Armada 375 coherency workaround"), but it was not
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visible until now since it didn't cause any problem when HW I/O
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coherency is enabled.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
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Cc: <stable at vger.kernel.org> v3.16..v3.18
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---
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arch/arm/mach-mvebu/coherency.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
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index 2ffccd4..01efe13 100644
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--- a/arch/arm/mach-mvebu/coherency.c
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+++ b/arch/arm/mach-mvebu/coherency.c
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@@ -448,8 +448,9 @@ static int __init coherency_late_init(void)
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armada_375_coherency_init_wa();
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}
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- bus_register_notifier(&platform_bus_type,
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- &mvebu_hwcc_nb);
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+ if (coherency_available())
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+ bus_register_notifier(&platform_bus_type,
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+ &mvebu_hwcc_nb);
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return 0;
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}
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--
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2.1.0
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@ -65,6 +65,7 @@ bugfix/x86/acpi-video-add-disable_native_backlight-quirk-for-samsung-730u3e-740u
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bugfix/x86/acpi-video-add-disable_native_backlight-quirk-for-samsung-510r.patch
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bugfix/x86/acpi-video-disable-native-backlight-on-samsung-series-9.patch
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bugfix/x86/drm-i915-quietly-reject-attempts-to-create-non-pagealigned-stolen-objects.patch
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bugfix/arm/mvebu-do-not-register-custom-DMA-operations-when-coherency-is-disabled.patch
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# Arch features
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features/mips/MIPS-Support-hard-limit-of-cpu-count-nr_cpu_ids.patch
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