[mips/octeon] Backport from upstream PCIe2 support and interface
mode detection for Octeon. svn path=/dists/sid/linux/; revision=21585
This commit is contained in:
Aurelien Jarno
parent
c7d9ba6084
commit
b9720c4878
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@ -32,6 +32,8 @@ linux (3.14.12-2) UNRELEASED; urgency=medium
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corresponding flavour.
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* [mips,mipsel] Remove the sb1a-bcm91480b flavour.
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* [mips,mipsel] Add mips64 and mips64el support (Closes: #749688).
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* [mips/octeon] Backport from upstream PCIe2 support and interface
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mode detection for Octeon.
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[ Ben Hutchings ]
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* net/l2tp: don't fall back on UDP [get|set]sockopt (CVE-2014-4943)
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45
debian/patches/features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch
vendored
Normal file
45
debian/patches/features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch
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@ -0,0 +1,45 @@
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From: Eunbong Song <eunb.song@samsung.com>
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Date: Fri, 11 Apr 2014 08:32:54 +0000
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Subject: MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()
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Origin: https://git.kernel.org/linus/d19648d7f3b047bac9922fe097f62afbb48fee62
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In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality
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fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type"
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message. This patch solve this problem.
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Signed-off-by: Eunbong Song <eunb.song@samsung.com>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/6747/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/pci/msi-octeon.c | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
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index 2b91b0e..ab0c5d1 100644
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--- a/arch/mips/pci/msi-octeon.c
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+++ b/arch/mips/pci/msi-octeon.c
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@@ -15,6 +15,7 @@
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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#include <asm/octeon/cvmx-npei-defs.h>
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+#include <asm/octeon/cvmx-sli-defs.h>
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#include <asm/octeon/cvmx-pexp-defs.h>
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#include <asm/octeon/pci-octeon.h>
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@@ -162,6 +163,11 @@ msi_irq_allocated:
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msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
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msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
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break;
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+ case OCTEON_DMA_BAR_TYPE_PCIE2:
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+ /* When using PCIe2, Bar 0 is based at 0 */
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+ msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
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+ msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
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+ break;
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default:
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panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
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}
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--
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2.0.0
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207
debian/patches/features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch
vendored
Normal file
207
debian/patches/features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch
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@ -0,0 +1,207 @@
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From: Alex Smith <alex.smith@imgtec.com>
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Date: Thu, 29 May 2014 11:10:01 +0100
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Subject: MIPS: octeon: Add interface mode detection for Octeon II
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Origin: https://git.kernel.org/linus/d8ce75934b888df0bd73dfd9c030a2b034a04977
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Add interface mode detection for Octeon II. This is necessary to detect
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the interface modes correctly on the UBNT E200 board. Code is taken
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from the UBNT GPL source release, with some alterations: SRIO, ILK and
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RXAUI interface modes are removed and instead return disabled as these
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modes are not currently supported.
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Signed-off-by: Alex Smith <alex.smith@imgtec.com>
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Tested-by: David Daney <david.daney@cavium.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/7039/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/cavium-octeon/executive/cvmx-helper.c | 166 ++++++++++++++++++++++++
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1 file changed, 166 insertions(+)
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diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
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index 8553ad5..7e5cf7a 100644
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--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
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+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
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@@ -106,6 +106,158 @@ int cvmx_helper_ports_on_interface(int interface)
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EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface);
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/**
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+ * @INTERNAL
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+ * Return interface mode for CN68xx.
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+ */
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+static cvmx_helper_interface_mode_t __cvmx_get_mode_cn68xx(int interface)
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+{
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+ switch (interface) {
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+ case 0:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ case 2:
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+ case 3:
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+ case 4:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(interface));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ case 7:
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(3));
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+ /* QLM is disabled when QLM SPD is 15. */
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+ if (qlm_cfg.s.qlm_spd == 15) {
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (qlm_cfg.s.qlm_cfg != 0) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
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+ if (qlm_cfg.s.qlm_cfg != 0)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ return CVMX_HELPER_INTERFACE_MODE_NPI;
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+ case 8:
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+ return CVMX_HELPER_INTERFACE_MODE_LOOP;
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+ default:
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+}
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+
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+/**
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+ * @INTERNAL
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+ * Return interface mode for an Octeon II
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+ */
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+static cvmx_helper_interface_mode_t __cvmx_get_mode_octeon2(int interface)
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+{
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+ union cvmx_gmxx_inf_mode mode;
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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+ return __cvmx_get_mode_cn68xx(interface);
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+
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+ if (interface == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_NPI;
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+
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+ if (interface == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_LOOP;
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+
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+ /* Only present in CN63XX & CN66XX Octeon model */
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+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX) &&
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+ (interface == 4 || interface == 5)) ||
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+ (OCTEON_IS_MODEL(OCTEON_CN66XX) &&
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+ interface >= 4 && interface <= 7)) {
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
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+ union cvmx_mio_qlmx_cfg mio_qlm_cfg;
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+
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+ /* QLM2 is SGMII0 and QLM1 is SGMII1 */
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+ if (interface == 0)
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+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
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+ else if (interface == 1)
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+ mio_qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(1));
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mio_qlm_cfg.s.qlm_spd == 15)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mio_qlm_cfg.s.qlm_cfg == 9)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (mio_qlm_cfg.s.qlm_cfg == 11)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+
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+ if (interface == 0) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(2));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ } else if (interface == 1) {
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ else if (qlm_cfg.s.qlm_cfg == 3)
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ } else if (OCTEON_IS_MODEL(OCTEON_CNF71XX)) {
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+ if (interface == 0) {
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+ union cvmx_mio_qlmx_cfg qlm_cfg;
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+ qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(0));
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+ if (qlm_cfg.s.qlm_cfg == 2)
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ }
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+
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+ if (interface == 1 && OCTEON_IS_MODEL(OCTEON_CN63XX))
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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+
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+ if (OCTEON_IS_MODEL(OCTEON_CN63XX)) {
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+ switch (mode.cn63xx.mode) {
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+ case 0:
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+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
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+ case 1:
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+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
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+ default:
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+ }
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+ } else {
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+ if (!mode.s.en)
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ if (mode.s.type)
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+ return CVMX_HELPER_INTERFACE_MODE_GMII;
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+ else
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+ return CVMX_HELPER_INTERFACE_MODE_RGMII;
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+ }
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+}
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+
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+/**
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* Get the operating mode of an interface. Depending on the Octeon
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* chip and configuration, this function returns an enumeration
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* of the type of packet I/O supported by an interface.
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@@ -118,6 +270,20 @@ EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface);
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cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
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{
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union cvmx_gmxx_inf_mode mode;
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+
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+ if (interface < 0 ||
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+ interface >= cvmx_helper_get_number_of_interfaces())
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+ return CVMX_HELPER_INTERFACE_MODE_DISABLED;
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+
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+ /*
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+ * Octeon II models
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+ */
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+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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+ return __cvmx_get_mode_octeon2(interface);
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+
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+ /*
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+ * Octeon and Octeon Plus models
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+ */
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if (interface == 2)
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return CVMX_HELPER_INTERFACE_MODE_NPI;
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--
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2.0.0
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@ -98,3 +98,5 @@ features/mips/0010-MIPS-Loongson-Add-Loongson-3-Kconfig-options.patch
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features/mips/0011-MIPS-Loongson-3-Add-Loongson-3-SMP-support.patch
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features/mips/0012-MIPS-Loongson-3-Add-CPU-hotplug-support.patch
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features/mips/0013-MIPS-Loongson-Add-a-Loongson-3-default-config-file.patch
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features/mips/MIPS-Octeon-Add-PCIe2-support-in-arch_setup_msi_irq.patch
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features/mips/MIPS-octeon-Add-interface-mode-detection-for-Octeon-.patch
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