905 lines
27 KiB
Diff
905 lines
27 KiB
Diff
--- a/drivers/ssb/Kconfig
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+++ b/drivers/ssb/Kconfig
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@@ -138,13 +138,13 @@ config SSB_DRIVER_MIPS
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config SSB_SFLASH
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bool "SSB serial flash support"
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- depends on SSB_DRIVER_MIPS && BROKEN
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+ depends on SSB_DRIVER_MIPS
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default y
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# Assumption: We are on embedded, if we compile the MIPS core.
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config SSB_EMBEDDED
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bool
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- depends on SSB_DRIVER_MIPS
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+ depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
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default y
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config SSB_DRIVER_EXTIF
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@@ -168,6 +168,7 @@ config SSB_DRIVER_GIGE
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config SSB_DRIVER_GPIO
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bool "SSB GPIO driver"
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depends on SSB && GPIOLIB
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+ select IRQ_DOMAIN if SSB_EMBEDDED
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help
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Driver to provide access to the GPIO pins on the bus.
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--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -38,6 +38,7 @@ static const struct pci_device_id b43_pc
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
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{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4351) },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
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--- a/drivers/ssb/driver_chipcommon_sflash.c
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+++ b/drivers/ssb/driver_chipcommon_sflash.c
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@@ -9,6 +9,19 @@
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#include "ssb_private.h"
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+static struct resource ssb_sflash_resource = {
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+ .name = "ssb_sflash",
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+ .start = SSB_FLASH2,
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+ .end = 0,
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+ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
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+};
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+
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+struct platform_device ssb_sflash_dev = {
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+ .name = "ssb_sflash",
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+ .resource = &ssb_sflash_resource,
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+ .num_resources = 1,
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+};
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+
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struct ssb_sflash_tbl_e {
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char *name;
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u32 id;
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@@ -16,7 +29,7 @@ struct ssb_sflash_tbl_e {
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u16 numblocks;
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
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{ "M25P20", 0x11, 0x10000, 4, },
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{ "M25P40", 0x12, 0x10000, 8, },
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@@ -24,10 +37,10 @@ static struct ssb_sflash_tbl_e ssb_sflas
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{ "M25P32", 0x15, 0x10000, 64, },
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{ "M25P64", 0x16, 0x10000, 128, },
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{ "M25FL128", 0x17, 0x10000, 256, },
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- { 0 },
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+ { NULL },
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
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{ "SST25WF512", 1, 0x1000, 16, },
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{ "SST25VF512", 0x48, 0x1000, 16, },
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{ "SST25WF010", 2, 0x1000, 32, },
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@@ -42,10 +55,10 @@ static struct ssb_sflash_tbl_e ssb_sflas
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{ "SST25VF016", 0x41, 0x1000, 512, },
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{ "SST25VF032", 0x4a, 0x1000, 1024, },
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{ "SST25VF064", 0x4b, 0x1000, 2048, },
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- { 0 },
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+ { NULL },
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};
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-static struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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+static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
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{ "AT45DB011", 0xc, 256, 512, },
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{ "AT45DB021", 0x14, 256, 1024, },
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{ "AT45DB041", 0x1c, 256, 2048, },
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@@ -53,7 +66,7 @@ static struct ssb_sflash_tbl_e ssb_sflas
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{ "AT45DB161", 0x2c, 512, 4096, },
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{ "AT45DB321", 0x34, 512, 8192, },
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{ "AT45DB642", 0x3c, 1024, 8192, },
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- { 0 },
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+ { NULL },
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};
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static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
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@@ -73,7 +86,8 @@ static void ssb_sflash_cmd(struct ssb_ch
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/* Initialize serial flash access */
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int ssb_sflash_init(struct ssb_chipcommon *cc)
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{
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- struct ssb_sflash_tbl_e *e;
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+ struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
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+ const struct ssb_sflash_tbl_e *e;
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u32 id, id2;
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switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
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@@ -131,10 +145,20 @@ int ssb_sflash_init(struct ssb_chipcommo
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return -ENOTSUPP;
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}
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- pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
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- e->name, e->blocksize, e->numblocks);
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-
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- pr_err("Serial flash support is not implemented yet!\n");
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+ sflash->window = SSB_FLASH2;
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+ sflash->blocksize = e->blocksize;
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+ sflash->numblocks = e->numblocks;
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+ sflash->size = sflash->blocksize * sflash->numblocks;
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+ sflash->present = true;
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+
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+ pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
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+ e->name, sflash->size / 1024, e->blocksize, e->numblocks);
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+
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+ /* Prepare platform device, but don't register it yet. It's too early,
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+ * malloc (required by device_private_init) is not available yet. */
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+ ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
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+ sflash->size;
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+ ssb_sflash_dev.dev.platform_data = sflash;
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- return -ENOTSUPP;
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+ return 0;
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}
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--- a/drivers/ssb/driver_gpio.c
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+++ b/drivers/ssb/driver_gpio.c
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@@ -9,16 +9,40 @@
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*/
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#include <linux/gpio.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+#include <linux/irqdomain.h>
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#include <linux/export.h>
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#include <linux/ssb/ssb.h>
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#include "ssb_private.h"
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+
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+/**************************************************
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+ * Shared
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+ **************************************************/
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+
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static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
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{
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return container_of(chip, struct ssb_bus, gpio);
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}
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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+{
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+ struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+
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+ if (bus->bustype == SSB_BUSTYPE_SSB)
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+ return irq_find_mapping(bus->irq_domain, gpio);
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+ else
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+ return -EINVAL;
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+}
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+#endif
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+
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+/**************************************************
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+ * ChipCommon
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+ **************************************************/
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+
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static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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@@ -74,19 +98,129 @@ static void ssb_gpio_chipco_free(struct
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ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
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}
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-static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+static void ssb_gpio_irq_chipco_mask(struct irq_data *d)
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{
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- struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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- if (bus->bustype == SSB_BUSTYPE_SSB)
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- return ssb_mips_irq(bus->chipco.dev) + 2;
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- else
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- return -EINVAL;
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+ ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), 0);
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+}
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+
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+static void ssb_gpio_irq_chipco_unmask(struct irq_data *d)
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+{
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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+ u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio));
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+
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+ ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val);
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+ ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), BIT(gpio));
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+}
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+
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+static struct irq_chip ssb_gpio_irq_chipco_chip = {
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+ .name = "SSB-GPIO-CC",
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+ .irq_mask = ssb_gpio_irq_chipco_mask,
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+ .irq_unmask = ssb_gpio_irq_chipco_unmask,
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+};
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+
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+static irqreturn_t ssb_gpio_irq_chipco_handler(int irq, void *dev_id)
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+{
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+ struct ssb_bus *bus = dev_id;
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ u32 val = chipco_read32(chipco, SSB_CHIPCO_GPIOIN);
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+ u32 mask = chipco_read32(chipco, SSB_CHIPCO_GPIOIRQ);
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+ u32 pol = chipco_read32(chipco, SSB_CHIPCO_GPIOPOL);
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+ unsigned long irqs = (val ^ pol) & mask;
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+ int gpio;
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+
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+ if (!irqs)
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+ return IRQ_NONE;
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+
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+ for_each_set_bit(gpio, &irqs, bus->gpio.ngpio)
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+ generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio));
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+ ssb_chipco_gpio_polarity(chipco, irqs, val & irqs);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus)
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+{
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio, hwirq, err;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return 0;
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+
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+ bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
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+ &irq_domain_simple_ops, chipco);
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+ if (!bus->irq_domain) {
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+ err = -ENODEV;
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+ goto err_irq_domain;
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+ }
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_create_mapping(bus->irq_domain, gpio);
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+
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+ irq_set_chip_data(irq, bus);
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+ irq_set_chip_and_handler(irq, &ssb_gpio_irq_chipco_chip,
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+ handle_simple_irq);
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+ }
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+
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+ hwirq = ssb_mips_irq(bus->chipco.dev) + 2;
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+ err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED,
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+ "gpio", bus);
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+ if (err)
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+ goto err_req_irq;
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+
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+ ssb_chipco_gpio_intmask(&bus->chipco, ~0, 0);
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+ chipco_set32(chipco, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO);
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+
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+ return 0;
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+
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+err_req_irq:
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+err_irq_domain:
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+ return err;
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+}
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+
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+static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus)
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+{
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+ struct ssb_chipcommon *chipco = &bus->chipco;
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+ struct gpio_chip *chip = &bus->gpio;
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+ int gpio;
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+
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
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+ return;
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+
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+ chipco_mask32(chipco, SSB_CHIPCO_IRQMASK, ~SSB_CHIPCO_IRQ_GPIO);
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+ free_irq(ssb_mips_irq(bus->chipco.dev) + 2, chipco);
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+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
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+ int irq = irq_find_mapping(bus->irq_domain, gpio);
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+
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+ irq_dispose_mapping(irq);
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+ }
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+ irq_domain_remove(bus->irq_domain);
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+}
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+#else
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+static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus)
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+{
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+ return 0;
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+}
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+
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+static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus)
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+{
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}
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+#endif
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static int ssb_gpio_chipco_init(struct ssb_bus *bus)
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{
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struct gpio_chip *chip = &bus->gpio;
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+ int err;
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chip->label = "ssb_chipco_gpio";
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chip->owner = THIS_MODULE;
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@@ -96,7 +230,9 @@ static int ssb_gpio_chipco_init(struct s
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chip->set = ssb_gpio_chipco_set_value;
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chip->direction_input = ssb_gpio_chipco_direction_input;
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chip->direction_output = ssb_gpio_chipco_direction_output;
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- chip->to_irq = ssb_gpio_chipco_to_irq;
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
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+ chip->to_irq = ssb_gpio_to_irq;
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+#endif
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chip->ngpio = 16;
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/* There is just one SoC in one device and its GPIO addresses should be
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* deterministic to address them more easily. The other buses could get
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@@ -106,9 +242,23 @@ static int ssb_gpio_chipco_init(struct s
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else
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chip->base = -1;
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- return gpiochip_add(chip);
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+ err = ssb_gpio_irq_chipco_domain_init(bus);
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+ if (err)
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+ return err;
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+
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+ err = gpiochip_add(chip);
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+ if (err) {
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+ ssb_gpio_irq_chipco_domain_exit(bus);
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+ return err;
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+ }
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+
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+ return 0;
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}
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|
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+/**************************************************
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+ * EXTIF
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+ **************************************************/
|
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+
|
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#ifdef CONFIG_SSB_DRIVER_EXTIF
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|
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static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
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@@ -145,19 +295,127 @@ static int ssb_gpio_extif_direction_outp
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return 0;
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}
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|
|
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-static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
|
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+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
|
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+static void ssb_gpio_irq_extif_mask(struct irq_data *d)
|
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{
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- struct ssb_bus *bus = ssb_gpio_get_bus(chip);
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
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+ int gpio = irqd_to_hwirq(d);
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|
|
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- if (bus->bustype == SSB_BUSTYPE_SSB)
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- return ssb_mips_irq(bus->extif.dev) + 2;
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- else
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- return -EINVAL;
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+ ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), 0);
|
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+}
|
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+
|
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+static void ssb_gpio_irq_extif_unmask(struct irq_data *d)
|
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+{
|
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+ struct ssb_bus *bus = irq_data_get_irq_chip_data(d);
|
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+ int gpio = irqd_to_hwirq(d);
|
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+ u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio));
|
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+
|
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+ ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val);
|
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+ ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio));
|
|
+}
|
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+
|
|
+static struct irq_chip ssb_gpio_irq_extif_chip = {
|
|
+ .name = "SSB-GPIO-EXTIF",
|
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+ .irq_mask = ssb_gpio_irq_extif_mask,
|
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+ .irq_unmask = ssb_gpio_irq_extif_unmask,
|
|
+};
|
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+
|
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+static irqreturn_t ssb_gpio_irq_extif_handler(int irq, void *dev_id)
|
|
+{
|
|
+ struct ssb_bus *bus = dev_id;
|
|
+ struct ssb_extif *extif = &bus->extif;
|
|
+ u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN);
|
|
+ u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK);
|
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+ u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL);
|
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+ unsigned long irqs = (val ^ pol) & mask;
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+ int gpio;
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+
|
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+ if (!irqs)
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+ return IRQ_NONE;
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+
|
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+ for_each_set_bit(gpio, &irqs, bus->gpio.ngpio)
|
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+ generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio));
|
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+ ssb_extif_gpio_polarity(extif, irqs, val & irqs);
|
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+
|
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+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
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+static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus)
|
|
+{
|
|
+ struct ssb_extif *extif = &bus->extif;
|
|
+ struct gpio_chip *chip = &bus->gpio;
|
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+ int gpio, hwirq, err;
|
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+
|
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+ if (bus->bustype != SSB_BUSTYPE_SSB)
|
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+ return 0;
|
|
+
|
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+ bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
|
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+ &irq_domain_simple_ops, extif);
|
|
+ if (!bus->irq_domain) {
|
|
+ err = -ENODEV;
|
|
+ goto err_irq_domain;
|
|
+ }
|
|
+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
|
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+ int irq = irq_create_mapping(bus->irq_domain, gpio);
|
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+
|
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+ irq_set_chip_data(irq, bus);
|
|
+ irq_set_chip_and_handler(irq, &ssb_gpio_irq_extif_chip,
|
|
+ handle_simple_irq);
|
|
+ }
|
|
+
|
|
+ hwirq = ssb_mips_irq(bus->extif.dev) + 2;
|
|
+ err = request_irq(hwirq, ssb_gpio_irq_extif_handler, IRQF_SHARED,
|
|
+ "gpio", bus);
|
|
+ if (err)
|
|
+ goto err_req_irq;
|
|
+
|
|
+ ssb_extif_gpio_intmask(&bus->extif, ~0, 0);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_req_irq:
|
|
+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
|
|
+ int irq = irq_find_mapping(bus->irq_domain, gpio);
|
|
+
|
|
+ irq_dispose_mapping(irq);
|
|
+ }
|
|
+ irq_domain_remove(bus->irq_domain);
|
|
+err_irq_domain:
|
|
+ return err;
|
|
}
|
|
|
|
+static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus)
|
|
+{
|
|
+ struct ssb_extif *extif = &bus->extif;
|
|
+ struct gpio_chip *chip = &bus->gpio;
|
|
+ int gpio;
|
|
+
|
|
+ if (bus->bustype != SSB_BUSTYPE_SSB)
|
|
+ return;
|
|
+
|
|
+ free_irq(ssb_mips_irq(bus->extif.dev) + 2, extif);
|
|
+ for (gpio = 0; gpio < chip->ngpio; gpio++) {
|
|
+ int irq = irq_find_mapping(bus->irq_domain, gpio);
|
|
+
|
|
+ irq_dispose_mapping(irq);
|
|
+ }
|
|
+ irq_domain_remove(bus->irq_domain);
|
|
+}
|
|
+#else
|
|
+static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus)
|
|
+{
|
|
+}
|
|
+#endif
|
|
+
|
|
static int ssb_gpio_extif_init(struct ssb_bus *bus)
|
|
{
|
|
struct gpio_chip *chip = &bus->gpio;
|
|
+ int err;
|
|
|
|
chip->label = "ssb_extif_gpio";
|
|
chip->owner = THIS_MODULE;
|
|
@@ -165,7 +423,9 @@ static int ssb_gpio_extif_init(struct ss
|
|
chip->set = ssb_gpio_extif_set_value;
|
|
chip->direction_input = ssb_gpio_extif_direction_input;
|
|
chip->direction_output = ssb_gpio_extif_direction_output;
|
|
- chip->to_irq = ssb_gpio_extif_to_irq;
|
|
+#if IS_ENABLED(CONFIG_SSB_EMBEDDED)
|
|
+ chip->to_irq = ssb_gpio_to_irq;
|
|
+#endif
|
|
chip->ngpio = 5;
|
|
/* There is just one SoC in one device and its GPIO addresses should be
|
|
* deterministic to address them more easily. The other buses could get
|
|
@@ -175,7 +435,17 @@ static int ssb_gpio_extif_init(struct ss
|
|
else
|
|
chip->base = -1;
|
|
|
|
- return gpiochip_add(chip);
|
|
+ err = ssb_gpio_irq_extif_domain_init(bus);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ err = gpiochip_add(chip);
|
|
+ if (err) {
|
|
+ ssb_gpio_irq_extif_domain_exit(bus);
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
}
|
|
|
|
#else
|
|
@@ -185,6 +455,10 @@ static int ssb_gpio_extif_init(struct ss
|
|
}
|
|
#endif
|
|
|
|
+/**************************************************
|
|
+ * Init
|
|
+ **************************************************/
|
|
+
|
|
int ssb_gpio_init(struct ssb_bus *bus)
|
|
{
|
|
if (ssb_chipco_available(&bus->chipco))
|
|
--- a/drivers/ssb/main.c
|
|
+++ b/drivers/ssb/main.c
|
|
@@ -553,6 +553,14 @@ static int ssb_devices_register(struct s
|
|
}
|
|
#endif
|
|
|
|
+#ifdef CONFIG_SSB_SFLASH
|
|
+ if (bus->mipscore.sflash.present) {
|
|
+ err = platform_device_register(&ssb_sflash_dev);
|
|
+ if (err)
|
|
+ pr_err("Error registering serial flash\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
return 0;
|
|
error:
|
|
/* Unwind the already registered devices. */
|
|
@@ -582,6 +590,13 @@ static int ssb_attach_queued_buses(void)
|
|
ssb_pcicore_init(&bus->pcicore);
|
|
if (bus->bustype == SSB_BUSTYPE_SSB)
|
|
ssb_watchdog_register(bus);
|
|
+
|
|
+ err = ssb_gpio_init(bus);
|
|
+ if (err == -ENOTSUPP)
|
|
+ ssb_dbg("GPIO driver not activated\n");
|
|
+ else if (err)
|
|
+ ssb_dbg("Error registering GPIO driver: %i\n", err);
|
|
+
|
|
ssb_bus_may_powerdown(bus);
|
|
|
|
err = ssb_devices_register(bus);
|
|
@@ -819,11 +834,6 @@ static int ssb_bus_register(struct ssb_b
|
|
ssb_chipcommon_init(&bus->chipco);
|
|
ssb_extif_init(&bus->extif);
|
|
ssb_mipscore_init(&bus->mipscore);
|
|
- err = ssb_gpio_init(bus);
|
|
- if (err == -ENOTSUPP)
|
|
- ssb_dbg("GPIO driver not activated\n");
|
|
- else if (err)
|
|
- ssb_dbg("Error registering GPIO driver: %i\n", err);
|
|
err = ssb_fetch_invariants(bus, get_invariants);
|
|
if (err) {
|
|
ssb_bus_may_powerdown(bus);
|
|
--- a/drivers/ssb/pci.c
|
|
+++ b/drivers/ssb/pci.c
|
|
@@ -326,13 +326,13 @@ err_ctlreg:
|
|
return err;
|
|
}
|
|
|
|
-static s8 r123_extract_antgain(u8 sprom_revision, const u16 *in,
|
|
- u16 mask, u16 shift)
|
|
+static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
|
|
+ u16 mask, u16 shift)
|
|
{
|
|
u16 v;
|
|
u8 gain;
|
|
|
|
- v = in[SPOFF(SSB_SPROM1_AGAIN)];
|
|
+ v = in[SPOFF(offset)];
|
|
gain = (v & mask) >> shift;
|
|
if (gain == 0xFF)
|
|
gain = 2; /* If unset use 2dBm */
|
|
@@ -416,12 +416,14 @@ static void sprom_extract_r123(struct ss
|
|
SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
|
|
|
|
/* Extract the antenna gain values. */
|
|
- out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
|
|
- SSB_SPROM1_AGAIN_BG,
|
|
- SSB_SPROM1_AGAIN_BG_SHIFT);
|
|
- out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
|
|
- SSB_SPROM1_AGAIN_A,
|
|
- SSB_SPROM1_AGAIN_A_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM1_AGAIN,
|
|
+ SSB_SPROM1_AGAIN_BG,
|
|
+ SSB_SPROM1_AGAIN_BG_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM1_AGAIN,
|
|
+ SSB_SPROM1_AGAIN_A,
|
|
+ SSB_SPROM1_AGAIN_A_SHIFT);
|
|
if (out->revision >= 2)
|
|
sprom_extract_r23(out, in);
|
|
}
|
|
@@ -468,7 +470,15 @@ static void sprom_extract_r458(struct ss
|
|
|
|
static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
|
|
{
|
|
+ static const u16 pwr_info_offset[] = {
|
|
+ SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
|
|
+ SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
|
|
+ };
|
|
u16 il0mac_offset;
|
|
+ int i;
|
|
+
|
|
+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
|
|
+ ARRAY_SIZE(out->core_pwr_info));
|
|
|
|
if (out->revision == 4)
|
|
il0mac_offset = SSB_SPROM4_IL0MAC;
|
|
@@ -524,14 +534,59 @@ static void sprom_extract_r45(struct ssb
|
|
}
|
|
|
|
/* Extract the antenna gain values. */
|
|
- SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
|
|
- SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
|
|
- SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
|
|
- SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
|
|
- SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
|
|
- SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
|
|
- SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
|
|
- SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN01,
|
|
+ SSB_SPROM4_AGAIN0,
|
|
+ SSB_SPROM4_AGAIN0_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN01,
|
|
+ SSB_SPROM4_AGAIN1,
|
|
+ SSB_SPROM4_AGAIN1_SHIFT);
|
|
+ out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN23,
|
|
+ SSB_SPROM4_AGAIN2,
|
|
+ SSB_SPROM4_AGAIN2_SHIFT);
|
|
+ out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM4_AGAIN23,
|
|
+ SSB_SPROM4_AGAIN3,
|
|
+ SSB_SPROM4_AGAIN3_SHIFT);
|
|
+
|
|
+ /* Extract cores power info info */
|
|
+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
|
|
+ u16 o = pwr_info_offset[i];
|
|
+
|
|
+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
|
|
+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_2G_MAXP, 0);
|
|
+
|
|
+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
|
|
+
|
|
+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
|
|
+ SSB_SPROM4_5G_MAXP, 0);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
|
|
+ SSB_SPROM4_5GH_MAXP, 0);
|
|
+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
|
|
+ SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
|
|
+
|
|
+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
|
|
+ SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
|
|
+ }
|
|
|
|
sprom_extract_r458(out, in);
|
|
|
|
@@ -621,14 +676,22 @@ static void sprom_extract_r8(struct ssb_
|
|
SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
|
|
|
|
/* Extract the antenna gain values. */
|
|
- SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
|
|
- SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
|
|
- SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
|
|
- SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
|
|
- SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
|
|
- SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
|
|
- SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
|
|
- SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
|
|
+ out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN01,
|
|
+ SSB_SPROM8_AGAIN0,
|
|
+ SSB_SPROM8_AGAIN0_SHIFT);
|
|
+ out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN01,
|
|
+ SSB_SPROM8_AGAIN1,
|
|
+ SSB_SPROM8_AGAIN1_SHIFT);
|
|
+ out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN23,
|
|
+ SSB_SPROM8_AGAIN2,
|
|
+ SSB_SPROM8_AGAIN2_SHIFT);
|
|
+ out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
|
|
+ SSB_SPROM8_AGAIN23,
|
|
+ SSB_SPROM8_AGAIN3,
|
|
+ SSB_SPROM8_AGAIN3_SHIFT);
|
|
|
|
/* Extract cores power info info */
|
|
for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
|
|
--- a/drivers/ssb/pcihost_wrapper.c
|
|
+++ b/drivers/ssb/pcihost_wrapper.c
|
|
@@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
|
|
struct ssb_bus *ssb = pci_get_drvdata(dev);
|
|
int err;
|
|
|
|
- pci_set_power_state(dev, 0);
|
|
+ pci_set_power_state(dev, PCI_D0);
|
|
err = pci_enable_device(dev);
|
|
if (err)
|
|
return err;
|
|
--- a/drivers/ssb/sprom.c
|
|
+++ b/drivers/ssb/sprom.c
|
|
@@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
|
|
while (cnt < sprom_size_words) {
|
|
memcpy(tmp, dump, 4);
|
|
dump += 4;
|
|
- err = strict_strtoul(tmp, 16, &parsed);
|
|
+ err = kstrtoul(tmp, 16, &parsed);
|
|
if (err)
|
|
return err;
|
|
sprom[cnt++] = swab16((u16)parsed);
|
|
--- a/drivers/ssb/ssb_private.h
|
|
+++ b/drivers/ssb/ssb_private.h
|
|
@@ -243,6 +243,10 @@ static inline int ssb_sflash_init(struct
|
|
extern struct platform_device ssb_pflash_dev;
|
|
#endif
|
|
|
|
+#ifdef CONFIG_SSB_SFLASH
|
|
+extern struct platform_device ssb_sflash_dev;
|
|
+#endif
|
|
+
|
|
#ifdef CONFIG_SSB_DRIVER_EXTIF
|
|
extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
|
|
extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
|
|
--- a/include/linux/ssb/ssb.h
|
|
+++ b/include/linux/ssb/ssb.h
|
|
@@ -33,6 +33,7 @@ struct ssb_sprom {
|
|
u8 et1phyaddr; /* MII address for enet1 */
|
|
u8 et0mdcport; /* MDIO for enet0 */
|
|
u8 et1mdcport; /* MDIO for enet1 */
|
|
+ u16 dev_id; /* Device ID overriding e.g. PCI ID */
|
|
u16 board_rev; /* Board revision number from SPROM. */
|
|
u16 board_num; /* Board number from SPROM. */
|
|
u16 board_type; /* Board type from SPROM. */
|
|
@@ -486,6 +487,7 @@ struct ssb_bus {
|
|
#endif /* EMBEDDED */
|
|
#ifdef CONFIG_SSB_DRIVER_GPIO
|
|
struct gpio_chip gpio;
|
|
+ struct irq_domain *irq_domain;
|
|
#endif /* DRIVER_GPIO */
|
|
|
|
/* Internal-only stuff follows. Do not touch. */
|
|
--- a/include/linux/ssb/ssb_driver_gige.h
|
|
+++ b/include/linux/ssb/ssb_driver_gige.h
|
|
@@ -108,6 +108,16 @@ static inline int ssb_gige_get_macaddr(s
|
|
return 0;
|
|
}
|
|
|
|
+/* Get the device phy address */
|
|
+static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
|
|
+{
|
|
+ struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
|
|
+ if (!dev)
|
|
+ return -ENODEV;
|
|
+
|
|
+ return dev->dev->bus->sprom.et0phyaddr;
|
|
+}
|
|
+
|
|
extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
|
|
struct pci_dev *pdev);
|
|
extern int ssb_gige_map_irq(struct ssb_device *sdev,
|
|
@@ -174,6 +184,10 @@ static inline int ssb_gige_get_macaddr(s
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
+static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
|
|
+{
|
|
+ return -ENODEV;
|
|
+}
|
|
|
|
#endif /* CONFIG_SSB_DRIVER_GIGE */
|
|
#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
|
|
--- a/include/linux/ssb/ssb_driver_mips.h
|
|
+++ b/include/linux/ssb/ssb_driver_mips.h
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@@ -20,6 +20,18 @@ struct ssb_pflash {
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u32 window_size;
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};
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+#ifdef CONFIG_SSB_SFLASH
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+struct ssb_sflash {
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+ bool present;
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+ u32 window;
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+ u32 blocksize;
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+ u16 numblocks;
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+ u32 size;
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+
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+ void *priv;
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+};
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+#endif
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+
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struct ssb_mipscore {
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struct ssb_device *dev;
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@@ -27,6 +39,9 @@ struct ssb_mipscore {
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struct ssb_serial_port serial_ports[4];
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struct ssb_pflash pflash;
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+#ifdef CONFIG_SSB_SFLASH
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+ struct ssb_sflash sflash;
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+#endif
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};
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extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -172,6 +172,7 @@
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#define SSB_SPROMSIZE_WORDS_R4 220
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#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
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#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
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+#define SSB_SPROMSIZE_WORDS_R10 230
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#define SSB_SPROM_BASE1 0x1000
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#define SSB_SPROM_BASE31 0x0800
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#define SSB_SPROM_REVISION 0x007E
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@@ -344,6 +345,43 @@
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#define SSB_SPROM4_TXPID5GH2_SHIFT 0
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#define SSB_SPROM4_TXPID5GH3 0xFF00
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#define SSB_SPROM4_TXPID5GH3_SHIFT 8
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+
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+/* There are 4 blocks with power info sharing the same layout */
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+#define SSB_SPROM4_PWR_INFO_CORE0 0x0080
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+#define SSB_SPROM4_PWR_INFO_CORE1 0x00AE
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+#define SSB_SPROM4_PWR_INFO_CORE2 0x00DC
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+#define SSB_SPROM4_PWR_INFO_CORE3 0x010A
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+
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+#define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
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+#define SSB_SPROM4_2G_MAXP 0x00FF
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+#define SSB_SPROM4_2G_ITSSI 0xFF00
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+#define SSB_SPROM4_2G_ITSSI_SHIFT 8
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+#define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */
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+#define SSB_SPROM4_2G_PA_1 0x04
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+#define SSB_SPROM4_2G_PA_2 0x06
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+#define SSB_SPROM4_2G_PA_3 0x08
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+#define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */
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+#define SSB_SPROM4_5G_MAXP 0x00FF
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+#define SSB_SPROM4_5G_ITSSI 0xFF00
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+#define SSB_SPROM4_5G_ITSSI_SHIFT 8
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+#define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */
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+#define SSB_SPROM4_5GH_MAXP 0x00FF
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+#define SSB_SPROM4_5GL_MAXP 0xFF00
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+#define SSB_SPROM4_5GL_MAXP_SHIFT 8
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+#define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */
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+#define SSB_SPROM4_5G_PA_1 0x10
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+#define SSB_SPROM4_5G_PA_2 0x12
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+#define SSB_SPROM4_5G_PA_3 0x14
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+#define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */
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+#define SSB_SPROM4_5GL_PA_1 0x18
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+#define SSB_SPROM4_5GL_PA_2 0x1A
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+#define SSB_SPROM4_5GL_PA_3 0x1C
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+#define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */
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+#define SSB_SPROM4_5GH_PA_1 0x20
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+#define SSB_SPROM4_5GH_PA_2 0x22
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+#define SSB_SPROM4_5GH_PA_3 0x24
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+
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+/* TODO: Make it deprecated */
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#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
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#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
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#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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--- a/arch/mips/bcm47xx/sprom.c
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+++ b/arch/mips/bcm47xx/sprom.c
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@@ -168,6 +168,7 @@ static void nvram_read_alpha2(const char
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static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
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const char *prefix, bool fallback)
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{
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+ nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
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nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
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nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
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nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
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