From d78ae71cdb5c4b1be66a0c1bd632d3a2c9769bbd Mon Sep 17 00:00:00 2001 From: Frank Voorburg Date: Fri, 20 Mar 2020 16:51:43 +0000 Subject: [PATCH] Refs #816. Added S32K144 EVB demo programs for the IAR Embedded Workbench. git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@764 5dc33758-31d5-4daf-9ae8-b24bf3d40d73 --- .../Boot/S32K144_64_flash.icf | 121 + .../Boot/bin/openblt_s32k144.out | Bin 0 -> 152164 bytes .../Boot/bin/openblt_s32k144.srec | 486 + .../Boot/blt_conf.h | 176 + .../Boot/boot.dox | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c | 307 + .../Boot/ide/s32k144.dep | 695 + .../Boot/ide/s32k144.ewd | 2966 ++++ .../Boot/ide/s32k144.ewp | 2266 +++ .../Boot/ide/s32k144.ewt | 2528 ++++ .../Boot/ide/s32k144.eww | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c | 108 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h | 40 + .../Boot/lib/S32K144.h | 11937 ++++++++++++++++ .../Boot/lib/S32K144_features.h | 1507 ++ .../Boot/lib/devassert.h | 84 + .../Boot/lib/device_registers.h | 70 + .../Boot/lib/s32_core_cm4.h | 209 + .../Boot/lib/startup.c | 248 + .../Boot/lib/startup.h | 133 + .../Boot/lib/system_S32K144.c | 197 + .../Boot/lib/system_S32K144.h | 111 + .../ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c | 208 + .../Boot/startup_S32K144.s | 693 + .../Prog/S32K144_64_flash.icf | 121 + .../Prog/bin/demoprog_s32k144.out | Bin 0 -> 60328 bytes .../Prog/bin/demoprog_s32k144.srec | 240 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.c | 772 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h | 40 + .../Prog/header.h | 42 + .../Prog/ide/s32k144.dep | 264 + .../Prog/ide/s32k144.ewd | 2966 ++++ .../Prog/ide/s32k144.ewp | 2167 +++ .../Prog/ide/s32k144.ewt | 2432 ++++ .../Prog/ide/s32k144.eww | 7 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c | 96 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h | 39 + .../Prog/lib/S32K144.h | 11937 ++++++++++++++++ .../Prog/lib/S32K144_features.h | 1507 ++ .../Prog/lib/devassert.h | 84 + .../Prog/lib/device_registers.h | 70 + .../Prog/lib/s32_core_cm4.h | 209 + .../Prog/lib/startup.c | 248 + .../Prog/lib/startup.h | 133 + .../Prog/lib/system_S32K144.c | 197 + .../Prog/lib/system_S32K144.h | 111 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c | 204 + .../Prog/prog.dox | 13 + .../Prog/startup_S32K144.s | 693 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c | 88 + .../ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h | 38 + .../ARMCM4_S32K14_S32K144EVB_IAR/demo.dox | 8 + Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c | 59 + Target/Source/ARMCM4_S32K14/rs232.c | 2 +- 54 files changed, 49890 insertions(+), 1 deletion(-) create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.srec create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewd create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewp create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.ewt create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144_features.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/devassert.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/device_registers.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/s32_core_cm4.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/startup_S32K144.s create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/S32K144_64_flash.icf create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.out create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.srec create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.dep create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewd create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewp create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewt create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.eww create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144_features.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/devassert.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/device_registers.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/s32_core_cm4.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/prog.dox create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/startup_S32K144.s create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h create mode 100644 Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/demo.dox create mode 100644 Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf new file mode 100644 index 00000000..295c8d15 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/S32K144_64_flash.icf @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processor: S32K144 with 64 KB SRAM +** Compiler: IAR ANSI C/C++ Compiler for ARM +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015-2016 Freescale Semiconductor, Inc. +** Copyright 2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from FLASH will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x00000400; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000003FF; + +/* Flash */ +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x00001FFF; + +/* SRAM_L */ +define symbol m_interrupts_ram_start = 0x1FFF8000; +define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +/* SRAM_U */ +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x20006FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x00000400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x00000400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define exported symbol __RAM_START = m_interrupts_ram_start; +define exported symbol __RAM_END = m_data_2_end; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* Custom Section Block that can be used to place data at absolute address. */ +/* Use __attribute__((section (".customSection"))) to place data here. */ +define block customSectionBlock { section .customSection }; + +define block __CODE_ROM { section .textrw_init }; +define block __CODE_RAM { section .textrw }; + +initialize manually { section .textrw }; +initialize manually { section .bss }; +initialize manually { section .customSection }; +initialize manually { section .data }; +initialize manually { section __DLIB_PERTHREAD }; +do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in TEXT_region { block __CODE_ROM }; +place in DATA_region { block RW }; +place in DATA_region { block __CODE_RAM }; +place in DATA_region_2 { first block customSectionBlock }; +place in DATA_region_2 { block ZI }; +place in DATA_region_2 { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/bin/openblt_s32k144.out new file mode 100644 index 0000000000000000000000000000000000000000..842d7c8e4d6ac348eef0b60373e87ba7e9ba285a GIT binary patch literal 152164 zcmeEv31C#k{r|jccXMyZ2?W@LD*@yd@gyV=2m&Gjk4l?_WHC`lLJo}9BU%r%R;@>C zJ*u_VYPGGRSZk&7YpvB*ZG!r%wFmL2+FIKcP!>?~|9ocN+antgV>Z~|-;#P#|ef=74f3V$)MhbB>?jygrzmUNfI`Chq13kU2{TKE0Y!8Znc4^P3%0SQ5 z?ZNgePnG&@T5!Za0&`7~0;^FO&^+6NwQYY42E2a^?h*uN!%BiMFjWAUwro zTQ_Ni$z47n06$2}i+r&? zXj&rR+S5_y?si-PrU-l->?mX0Tiyv=9NbJ=v~k;mf643$27Fz?UEZs5myaAWynf_W zC1RTxH%&adNh?a1R7~6J7L$h7jwD4B_Z|&MPm$57$*1UY{JOg6GFxojBm%eZafzvT z+p(o%v*rU)-`pN-%1o>q^1hZfxl0syZ0gy4V$ar1`WE0UKw8WkT9;6FRW5!< zsHbO|dM4XXul>xlpSkuk{euhF)2EmqI)!iRrltkn&Dxml!3PYjE*(6Wog#2w5QRXO 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+S9031DFDE2 diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h new file mode 100644 index 00000000..966813dd --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h @@ -0,0 +1,176 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/blt_conf.h +* \brief Bootloader configuration header file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BLT_CONF_H +#define BLT_CONF_H + +/**************************************************************************************** +* C P U D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* To properly initialize the baudrate clocks of the communication interface, typically + * the speed of the crystal oscillator and/or the speed at which the system runs is + * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and + * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is + * not dependent on the targets architecture, the byte ordering needs to be known. + * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects + * little endian mode. + * + * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be + * called the moment the user program is about to be started. This could be used to + * de-initialize application specific parts, for example to stop blinking an LED, etc. + */ +/** \brief Frequency of the external crystal oscillator. */ +#define BOOT_CPU_XTAL_SPEED_KHZ (8000) +/** \brief Desired system speed. */ +#define BOOT_CPU_SYSTEM_SPEED_KHZ (80000) +/** \brief Motorola or Intel style byte ordering. */ +#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0) +/** \brief Enable/disable hook function call right before user program start. */ +#define BOOT_CPU_USER_PROGRAM_START_HOOK (1) + + +/**************************************************************************************** +* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N +****************************************************************************************/ +/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE + * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed + * in bits/second. The maximum amount of data bytes in a message for data transmission + * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA, + * respectively. It is common for a microcontroller to have more than 1 UART interface + * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface. + * + */ +/** \brief Enable/disable UART transport layer. */ +#define BOOT_COM_RS232_ENABLE (1) +/** \brief Configure the desired communication speed. */ +#define BOOT_COM_RS232_BAUDRATE (57600) +/** \brief Configure number of bytes in the target->host data packet. */ +#define BOOT_COM_RS232_TX_MAX_DATA (64) +/** \brief Configure number of bytes in the host->target data packet. */ +#define BOOT_COM_RS232_RX_MAX_DATA (64) +/** \brief Select the desired UART peripheral as a zero based index. */ +#define BOOT_COM_RS232_CHANNEL_INDEX (1) + +/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE + * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed + * in bits/second. Two CAN messages are reserved for communication with the host. The + * message identifier for sending data from the target to the host is configured with + * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with + * BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by + * OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data + * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and + * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more + * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the + * CAN controller channel. + * + */ +/** \brief Enable/disable CAN transport layer. */ +#define BOOT_COM_CAN_ENABLE (1) +/** \brief Configure the desired CAN baudrate. */ +#define BOOT_COM_CAN_BAUDRATE (500000) +/** \brief Configure CAN message ID target->host. */ +#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/) +/** \brief Configure number of bytes in the target->host CAN message. */ +#define BOOT_COM_CAN_TX_MAX_DATA (8) +/** \brief Configure CAN message ID host->target. */ +#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/) +/** \brief Configure number of bytes in the host->target CAN message. */ +#define BOOT_COM_CAN_RX_MAX_DATA (8) +/** \brief Select the desired CAN peripheral as a zero based index. */ +#define BOOT_COM_CAN_CHANNEL_INDEX (0) + + +/**************************************************************************************** +* B A C K D O O R E N T R Y C O N F I G U R A T I O N +****************************************************************************************/ +/* It is possible to implement an application specific method to force the bootloader to + * stay active after a reset. Such a backdoor entry into the bootloader is desired in + * situations where the user program does not run properly and therefore cannot + * reactivate the bootloader. By enabling these hook functions, the application can + * implement the backdoor, which overrides the default backdoor entry that is programmed + * into the bootloader. When desired for security purposes, these hook functions can + * also be implemented in a way that disables the backdoor entry altogether. + */ +/** \brief Enable/disable the backdoor override hook functions. */ +#define BOOT_BACKDOOR_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The NVM driver typically supports erase and program operations of the internal memory + * present on the microcontroller. Through these hook functions the NVM driver can be + * extended to support additional memory types such as external flash memory and serial + * eeproms. The size of the internal memory in kilobytes is specified with configurable + * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can + * be overridden with a application specific method by enabling configuration switch + * BOOT_NVM_CHECKSUM_HOOKS_ENABLE. + */ +/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */ +#define BOOT_NVM_HOOKS_ENABLE (0) +/** \brief Configure the size of the default memory device (typically flash EEPROM). */ +#define BOOT_NVM_SIZE_KB (512) +/** \brief Enable/disable hooks functions to override the user program checksum handling. */ +#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0) + + +/**************************************************************************************** +* W A T C H D O G D R I V E R C O N F I G U R A T I O N +****************************************************************************************/ +/* The COP driver cannot be configured internally in the bootloader, because its use + * and configuration is application specific. The bootloader does need to service the + * watchdog in case it is used. When the application requires the use of a watchdog, + * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through + * hook functions. + */ +/** \brief Enable/disable the hook functions for controlling the watchdog. */ +#define BOOT_COP_HOOKS_ENABLE (1) + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N +****************************************************************************************/ +/* A security mechanism can be enabled in the bootloader's XCP module by setting configu- + * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming + * operations can be performed, access to this resource need to be unlocked. + * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that + * implements the unlocking algorithm. The demo programs are configured for the (simple) + * algorithm in "libseednkey.dll". The source code for this DLL is available so it can be + * customized to your needs. + * During the unlock sequence, Microboot requests a seed from the bootloader, which is in + * the format of a byte array. Using this seed the unlock algorithm in the DLL computes + * a key, which is also a byte array, and sends this back to the bootloader. The + * bootloader then verifies this key to determine if programming and erase operations are + * permitted. + * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook() + * are called by the bootloader to obtain the seed and to verify the key, respectively. + */ +#define BOOT_XCP_SEED_KEY_ENABLE (0) + + +#endif /* BLT_CONF_H */ +/*********************************** end of blt_conf.h *********************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox new file mode 100644 index 00000000..e9e14acb --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/boot.dox @@ -0,0 +1,7 @@ +/** +\defgroup Boot_ARMCM4_S32K14_S32K144EVB_IAR Bootloader +\brief Bootloader. +\ingroup ARMCM4_S32K14_S32K144EVB_IAR +*/ + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c new file mode 100644 index 00000000..bed8d469 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c @@ -0,0 +1,307 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/hooks.c +* \brief Bootloader callback source file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* LED driver header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* B A C K D O O R E N T R Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Initializes the backdoor entry option. +** \return none. +** +****************************************************************************************/ +void BackDoorInitHook(void) +{ +} /*** end of BackDoorInitHook ***/ + + +/************************************************************************************//** +** \brief Checks if a backdoor entry is requested. +** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool BackDoorEntryHook(void) +{ + /* default implementation always activates the bootloader after a reset */ + return BLT_TRUE; +} /*** end of BackDoorEntryHook ***/ +#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* C P U D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0) +/************************************************************************************//** +** \brief Callback that gets called when the bootloader is about to exit and +** hand over control to the user program. This is the last moment that +** some final checking can be performed and if necessary prevent the +** bootloader from activiting the user program. +** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep +** keep the bootloader active. +** +****************************************************************************************/ +blt_bool CpuUserProgramStartHook(void) +{ + /* additional and optional backdoor entry through the pushbutton (SW2) on the board. to + * force the bootloader to stay active after reset, keep it pressed during reset. + */ + if ((PTC->PDIR & GPIO_PDIR_PDI(1 << 12U)) != 0U) + { + /* pushbutton pressed, so do not start the user program and keep the + * bootloader active instead. + */ + return BLT_FALSE; + } + + /* clean up the LED driver */ + LedBlinkExit(); + + /* okay to start the user program */ + return BLT_TRUE; +} /*** end of CpuUserProgramStartHook ***/ +#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */ + + +/**************************************************************************************** +* W A T C H D O G D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_COP_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** initialization routine. It can be used to configure and enable the +** watchdog. +** \return none. +** +****************************************************************************************/ +void CopInitHook(void) +{ + /* this function is called upon initialization. might as well use it to initialize + * the LED driver. It is kind of a visual watchdog anyways. + */ + LedBlinkInit(100); +} /*** end of CopInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the internal COP driver +** service routine. This gets called upon initialization and during +** potential long lasting loops and routine. It can be used to service +** the watchdog to prevent a watchdog reset. +** \return none. +** +****************************************************************************************/ +void CopServiceHook(void) +{ + /* run the LED blink task. this is a better place to do it than in the main() program + * loop. certain operations such as flash erase can take a long time, which would cause + * a blink interval to be skipped. this function is also called during such operations, + * so no blink intervals will be skipped when calling the LED blink task here. + */ + LedBlinkTask(); +} /*** end of CopServiceHook ***/ +#endif /* BOOT_COP_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_NVM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Callback that gets called at the start of the internal NVM driver +** initialization routine. +** \return none. +** +****************************************************************************************/ +void NvmInitHook(void) +{ +} /*** end of NvmInitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of a firmware update to reinitialize +** the NVM driver. +** \return none. +** +****************************************************************************************/ +void NvmReinitHook(void) +{ +} /*** end of NvmReinitHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver write +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't +** been written yet. +** \param addr Start address. +** \param len Length in bytes. +** \param data Pointer to the data buffer. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the write +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmWriteHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the start of the NVM driver erase +** routine. It allows additional memory to be operated on. If the address +** is not within the range of the additional memory, then +** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory +** hasn't been erased yet. +** \param addr Start address. +** \param len Length in bytes. +** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is +** not within the supported memory range, or BLT_NVM_ERROR is the erase +** operation failed. +** +****************************************************************************************/ +blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len) +{ + return BLT_NVM_NOT_IN_RANGE; +} /*** end of NvmEraseHook ***/ + + +/************************************************************************************//** +** \brief Callback that gets called at the end of the NVM programming session. +** \return BLT_TRUE is successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmDoneHook(void) +{ + return BLT_TRUE; +} /*** end of NvmDoneHook ***/ +#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */ + + +#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0) +/************************************************************************************//** +** \brief Verifies the checksum, which indicates that a valid user program is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmVerifyChecksumHook(void) +{ + return BLT_TRUE; +} /*** end of NvmVerifyChecksum ***/ + + +/************************************************************************************//** +** \brief Writes a checksum of the user program to non-volatile memory. This is +** performed once the entire user program has been programmed. Through +** the checksum, the bootloader can check if a valid user programming is +** present and can be started. +** \return BLT_TRUE if successful, BLT_FALSE otherwise. +** +****************************************************************************************/ +blt_bool NvmWriteChecksumHook(void) +{ + return BLT_TRUE; +} +#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */ + + +/**************************************************************************************** +* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S +****************************************************************************************/ + +#if (BOOT_XCP_SEED_KEY_ENABLE > 0) +/************************************************************************************//** +** \brief Provides a seed to the XCP master that will be used for the key +** generation when the master attempts to unlock the specified resource. +** Called by the GET_SEED command. +** \param resource Resource that the seed if requested for (XCP_RES_XXX). +** \param seed Pointer to byte buffer wher the seed will be stored. +** \return Length of the seed in bytes. +** +****************************************************************************************/ +blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed) +{ + /* request seed for unlocking ProGraMming resource */ + if ((resource & XCP_RES_PGM) != 0) + { + seed[0] = 0x55; + } + + /* return seed length */ + return 1; +} /*** end of XcpGetSeedHook ***/ + + +/************************************************************************************//** +** \brief Called by the UNLOCK command and checks if the key to unlock the +** specified resource was correct. If so, then the resource protection +** will be removed. +** \param resource resource to unlock (XCP_RES_XXX). +** \param key pointer to the byte buffer holding the key. +** \param len length of the key in bytes. +** \return 1 if the key was correct, 0 otherwise. +** +****************************************************************************************/ +blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len) +{ + /* suppress compiler warning for unused parameter */ + len = len; + + /* the example key algorithm in "libseednkey.dll" works as follows: + * - PGM will be unlocked if key = seed - 1 + */ + + /* check key for unlocking ProGraMming resource */ + if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1))) + { + /* correct key received for unlocking PGM resource */ + return 1; + } + + /* still here so key incorrect */ + return 0; +} /*** end of XcpVerifyKeyHook ***/ +#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */ + + +/*********************************** end of hooks.c ************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep new file mode 100644 index 00000000..3ceeceb4 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.dep @@ -0,0 +1,695 @@ + + + 4 + 684628677 + + Debug + + $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\..\..\..\Source\assert.c + $PROJ_DIR$\..\blt_conf.h + $PROJ_DIR$\..\hooks.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\IAR\cpu_comp.c + $PROJ_DIR$\..\lib\device_registers.h + $PROJ_DIR$\..\startup_S32K144.s + $PROJ_DIR$\..\led.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\can.c + $PROJ_DIR$\..\lib\system_S32K144.c + $PROJ_DIR$\..\lib\S32K144_features.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\cpu.c + $PROJ_DIR$\..\lib\startup.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\flash.c + $PROJ_DIR$\..\led.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\flash.h + $PROJ_DIR$\..\lib\startup.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\rs232.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\timer.c + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\types.h + $PROJ_DIR$\..\lib\S32K144.h + $PROJ_DIR$\..\..\..\..\Source\ARMCM4_S32K14\nvm.c + $PROJ_DIR$\..\lib\devassert.h + $PROJ_DIR$\..\lib\s32_core_cm4.h + $PROJ_DIR$\..\lib\system_S32K144.h + $PROJ_DIR$\..\obj\hooks.__cstat.et + $PROJ_DIR$\..\obj\rs232.__cstat.et + $PROJ_DIR$\..\obj\com.xcl + $PROJ_DIR$\..\obj\nvm.__cstat.et + $PROJ_DIR$\..\obj\cop.__cstat.et + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\..\obj\cpu.xcl + $PROJ_DIR$\..\obj\assert.__cstat.et + $PROJ_DIR$\..\obj\can.__cstat.et + $PROJ_DIR$\..\obj\can.xcl + $PROJ_DIR$\..\obj\nvm.xcl + $PROJ_DIR$\..\obj\cop.xcl + $PROJ_DIR$\..\obj\file.xcl + $PROJ_DIR$\..\obj\cpu_comp.__cstat.et + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\..\obj\backdoor.__cstat.et + $PROJ_DIR$\..\obj\file.__cstat.et + $PROJ_DIR$\..\obj\xcp.__cstat.et + $TOOLKIT_DIR$\inc\c\ctype.h + $PROJ_DIR$\..\obj\can.o + $PROJ_DIR$\..\obj\assert.xcl + $PROJ_DIR$\..\obj\cpu_comp.xcl + $PROJ_DIR$\..\obj\backdoor.xcl + $PROJ_DIR$\..\obj\flash.__cstat.et + $PROJ_DIR$\..\obj\net.__cstat.et + $PROJ_DIR$\..\obj\cpu.__cstat.et + $PROJ_DIR$\..\obj\hooks.xcl + $PROJ_DIR$\..\obj\com.__cstat.et + $PROJ_DIR$\..\obj\hooks.o + $PROJ_DIR$\..\obj\rs232.xcl + $PROJ_DIR$\..\obj\net.xcl + $PROJ_DIR$\..\obj\net.o + $PROJ_DIR$\..\obj\file.o + $PROJ_DIR$\..\obj\cpu_comp.o + $PROJ_DIR$\..\obj\cop.o + $PROJ_DIR$\..\obj\xcp.o + $PROJ_DIR$\..\obj\flash.xcl + $PROJ_DIR$\..\obj\flash.o + $PROJ_DIR$\..\obj\cpu.o + $PROJ_DIR$\..\obj\backdoor.o + $PROJ_DIR$\..\obj\rs232.o + $PROJ_DIR$\..\obj\assert.o + $PROJ_DIR$\..\obj\nvm.o + $PROJ_DIR$\..\obj\com.o + $PROJ_DIR$\..\obj\startup_S32K144.o + $PROJ_DIR$\..\obj\s32k144.pbd + $PROJ_DIR$\..\obj\boot.__cstat.et + $PROJ_DIR$\..\obj\timer.xcl + $PROJ_DIR$\..\obj\boot.xcl + $PROJ_DIR$\..\obj\led.o + $PROJ_DIR$\..\obj\startup.__cstat.et + $PROJ_DIR$\..\bin\openblt_s32k144.out + $PROJ_DIR$\..\obj\xcp.xcl + $PROJ_DIR$\..\obj\timer.o + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\..\timer.c + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\obj\led.xcl + $PROJ_DIR$\..\bin\demoprog_s32k144.srec + $PROJ_DIR$\..\obj\main.xcl + $PROJ_DIR$\..\header.h + $PROJ_DIR$\..\obj\openblt_s32k144.map + $PROJ_DIR$\..\obj\main.o + $PROJ_DIR$\..\S32K144_64_flash.icf + $TOOLKIT_DIR$\inc\c\stdbool.h + $PROJ_DIR$\..\obj\system_S32K144.o + $PROJ_DIR$\..\obj\startup.xcl + $PROJ_DIR$\..\obj\boot.o + $PROJ_DIR$\..\obj\system_S32K144.__cstat.et + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\..\obj\timer.__cstat.et + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\obj\main.__cstat.et + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\boot.c + $PROJ_DIR$\..\..\..\..\Source\com.h + $PROJ_DIR$\..\..\..\..\Source\xcp.c + $PROJ_DIR$\..\..\..\..\Source\cop.c + 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$PROJ_DIR$\..\..\..\..\Source\plausibility.h + + + $PROJ_DIR$\..\..\..\..\Source\rs232.h + + + $PROJ_DIR$\..\..\..\..\Source\timer.h + + + $PROJ_DIR$\..\..\..\..\Source\usb.h + + + $PROJ_DIR$\..\..\..\..\Source\xcp.c + + + $PROJ_DIR$\..\..\..\..\Source\xcp.h + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww new file mode 100644 index 00000000..fcec0790 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/ide/s32k144.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\s32k144.ewp + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c new file mode 100644 index 00000000..df4ca52b --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c @@ -0,0 +1,108 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.c +* \brief LED driver source file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "led.h" /* module header */ +#include "device_registers.h" /* device registers */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Holds the desired LED blink interval time. */ +static blt_int16u ledBlinkIntervalMs; + + +/************************************************************************************//** +** \brief Initializes the LED blink driver. +** \param interval_ms Specifies the desired LED blink interval time in milliseconds. +** \return none. +** +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms) +{ + /* LED GPIO pin configuration. PD0 = GPIO, MUX = ALT1. */ + PORTD->PCR[0] |= PORT_PCR_MUX(1); + /* configure Port D pin 0 GPIO as digital output */ + PTD->PDDR |= GPIO_PDDR_PDD(0x00000001); + /* turn the LED off on Port D pin 0 */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); + /* store the interval time between LED toggles */ + ledBlinkIntervalMs = interval_ms; +} /*** end of LedBlinkInit ***/ + + +/************************************************************************************//** +** \brief Task function for blinking the LED as a fixed timer interval. +** \return none. +** +****************************************************************************************/ +void LedBlinkTask(void) +{ + static blt_bool ledOn = BLT_FALSE; + static blt_int32u nextBlinkEvent = 0; + + /* check for blink event */ + if (TimerGet() >= nextBlinkEvent) + { + /* toggle the LED state */ + if (ledOn == BLT_FALSE) + { + ledOn = BLT_TRUE; + /* Turn the LED on. */ + PTD->PCOR |= GPIO_PCOR_PTCO(0x00000001); + } + else + { + ledOn = BLT_FALSE; + /* Turn the LED off. */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); + } + /* schedule the next blink event */ + nextBlinkEvent = TimerGet() + ledBlinkIntervalMs; + } +} /*** end of LedBlinkTask ***/ + + +/************************************************************************************//** +** \brief Cleans up the LED blink driver. This is intended to be used upon program +** exit. +** \return none. +** +****************************************************************************************/ +void LedBlinkExit(void) +{ + /* Turn the LED off. */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); +} /*** end of LedBlinkExit ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h new file mode 100644 index 00000000..6889ee12 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/led.h +* \brief LED driver header file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedBlinkInit(blt_int16u interval_ms); +void LedBlinkTask(void); +void LedBlinkExit(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h new file mode 100644 index 00000000..ae04b8bb --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/S32K144.h @@ -0,0 +1,11937 @@ +/* +** ################################################################### +** Processor: S32K144 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 4.2, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K144 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-04-09) - Iulian Talpiga +** Initial version. +** - rev. 1.1 (2015-05-19) - Bogdan Nitu +** Updated interrupts table +** Removed SIM_CHIPCTL_DAC2CMP +** Compacted PORT_PCR registers +** Compacted PCC registers +** - rev. 1.2 (2015-06-02) - Bogdan Nitu +** Added 'U' suffix to all integer constants +** Use "" instead of <> for Platform type inclusion +** CNT register from WDOG module is RW +** - rev. 1.3 (2015-08-05) - Iulian Talpiga +** Synchronized with latest RDP +** Removed OSC32 module +** Removed reserved registers +** Incorporated bit band acces macros +** Switched to standard C99 data types +** Added 'u' to constants +** Added size defines for register arrays +** Define peripheral instance count +** - rev. 1.4 (2015-08-10) - Iulian Talpiga +** Compacted TRGMUX registers +** Defined array index offsets for PCC and TRGMUX +** Added FPU registers +** Group FTM channel registers +** Added interrupt information to peripherals +** Renamed CAN interrupts according to the reference manual +** Added author information to revisions +** - rev. 1.5 (2015-09-16) - Iulian Talpiga +** Renamed NVIC and SCB to avoid conflict +** Compacted CAN Wake-up Message buffers +** Added CAN embedded RAM +** Updated interrupts: LPIT, FTFE, LPUART,ACMP +** Corrected ADC_SC1_ADCH_WIDTH +** Compacted PDB registers +** Corrected CAN, FTM, and PDB count defines +** Guarding register acces macro against redefintion +** - rev. 1.6 (2015-09-29) - Iulian Talpiga +** Added WATER and FIFO registers to LPUART. +** - rev. 1.7 (2015-10-21) - Iulian Talpiga +** Updated ADC, AIPS, CMP, LMEM, LPTMR, PMC, PORT, RCM, RTC, SCG, SIM +** Compacted MPU and LPIT +** Added FSL_SysTick +** Updated doxygen documentation grouping +** Updated interrupts: RCM +** - rev. 1.8 (2016-01-06) - Iulian Talpiga +** Updated DMA, compacted TCD registers +** Updated SCG, removed SC2P - SC16P +** Added 8 and 16 bit access to DATA register, CRC module +** - rev. 1.9 (2016-02-15) - Iulian Talpiga +** Updated CRC, renamed DATA union +** Updated PMC, added CLKBIASDIS bitfield +** Added FSL_NVIC registers to SVD +** - rev. 2.0 (2016-04-07) - Iulian Talpiga +** Updated support for Rev2.0 silicon (0N47T) +** Updated ADC, AIPS, DMA, FlexIO, FTM, GPIO, LPI2C, LPIT, LPSPI, MCM, MPU, MSCM, PMC, RTC, RCM, PCC, RTC, SCG, SIM, TRGMUX and WDOG module +** Updated interrupts +** Added EIM and ERM modules +** Added EIM and ERM modules +** - rev. 2.1 (2016-06-10) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: CAN, EIM, LPI2C, MPU, PCC, PMC, RTC, SIM and TRGMUX +** - rev. 2.2 (2016-08-02) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: ADC, CAN, CRC, FTFC, LMEM, LPI2C, MCM, MSCM, PCC, RTC, SIM +** Added CSE_PRAM +** - rev. 2.3 (2016-09-09) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: PCC, FSL_NVIC and FTM +** - rev. 2.4 (2016-09-28) - Iulian Talpiga +** Fix RAMn array size in FlexCAN +** Fix FCSESTAT bit order +** Added CP0CFG0, CP0CFG1,CP0CFG2 and CP0CFG3 in MSCM +** Fixed STIR register in FSL_NVIC +** Fixed SHPR3 and ACTLR registers in FSL_SCB +** - rev. 2.5 (2016-11-25) - Iulian Talpiga +** Fix FRAC bit-field in PCC module +** Removed BITBAND_ACCESS macros +** Added MISRA declarations +** Updated copyright +** Changed prefix of NVIC, SCB and SysTick to S32_ +** - rev. 2.6 (2017-01-09) - Iulian Talpiga +** Fix interrupts for CAN, LPUART, FTFC +** - rev. 2.7 (2017-02-22) - Iulian Talpiga +** Update header as per rev S32K14XRM Rev. 2, 02/2017 +** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM +** - rev. 2.8 (2017-03-27) - Iulian Talpiga +** Synchronized PCC_FlexIO on S32K Family +** - rev. 3.0 (2017-08-04) - Mihai Volmer +** Update header as per rev S32K1XXRM Rev. 4, 06/2017 +** Updated modules CAN, MCM and PORTn +** - rev. 3.1 (2017-09-25) - Andrei Bolojan +** Update NVIC Size of Registers Arrays +** - rev. 4.0 (2018-02-28) - Mihai Volmer +** Updated header as per rev S32K1XXRM Rev. 6, 12/2017 +** Updated modules ERM, I2C, MSCM and SIM +** - rev. 4.1 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** - rev. 4.2 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** +** ################################################################### +*/ + +/*! + * @file S32K144.h + * @version 4.2 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K144 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K144_H_) /* Check if memory map has not been already included */ +#define S32K144_H_ +#define MCU_S32K144 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K144 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0400u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K144 Interrupt vector numbers for S32K144 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 139u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA4_IRQn = 4u, /**< DMA channel 4 transfer complete */ + DMA5_IRQn = 5u, /**< DMA channel 5 transfer complete */ + DMA6_IRQn = 6u, /**< DMA channel 6 transfer complete */ + DMA7_IRQn = 7u, /**< DMA channel 7 transfer complete */ + DMA8_IRQn = 8u, /**< DMA channel 8 transfer complete */ + DMA9_IRQn = 9u, /**< DMA channel 9 transfer complete */ + DMA10_IRQn = 10u, /**< DMA channel 10 transfer complete */ + DMA11_IRQn = 11u, /**< DMA channel 11 transfer complete */ + DMA12_IRQn = 12u, /**< DMA channel 12 transfer complete */ + DMA13_IRQn = 13u, /**< DMA channel 13 transfer complete */ + DMA14_IRQn = 14u, /**< DMA channel 14 transfer complete */ + DMA15_IRQn = 15u, /**< DMA channel 15 transfer complete */ + DMA_Error_IRQn = 16u, /**< DMA error interrupt channels 0-15 */ + MCM_IRQn = 17u, /**< FPU sources */ + FTFC_IRQn = 18u, /**< FTFC Command complete */ + Read_Collision_IRQn = 19u, /**< FTFC Read collision */ + LVD_LVW_IRQn = 20u, /**< PMC Low voltage detect interrupt */ + FTFC_Fault_IRQn = 21u, /**< FTFC Double bit fault detect */ + WDOG_EWM_IRQn = 22u, /**< Single interrupt vector for WDOG and EWM */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_IRQn = 24u, /**< LPI2C0 Master Interrupt */ + LPI2C0_Slave_IRQn = 25u, /**< LPI2C0 Slave Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + LPSPI2_IRQn = 28u, /**< LPSPI2 Interrupt */ + LPUART0_RxTx_IRQn = 31u, /**< LPUART0 Transmit / Receive Interrupt */ + LPUART1_RxTx_IRQn = 33u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART2_RxTx_IRQn = 35u, /**< LPUART2 Transmit / Receive Interrupt */ + ADC0_IRQn = 39u, /**< ADC0 interrupt request. */ + ADC1_IRQn = 40u, /**< ADC1 interrupt request. */ + CMP0_IRQn = 41u, /**< CMP0 interrupt request */ + ERM_single_fault_IRQn = 44u, /**< ERM single bit error correction */ + ERM_double_fault_IRQn = 45u, /**< ERM double bit error non-correctable */ + RTC_IRQn = 46u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 47u, /**< RTC seconds interrupt */ + LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */ + LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */ + LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */ + LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */ + PDB0_IRQn = 52u, /**< PDB0 interrupt */ + SCG_IRQn = 57u, /**< SCG bus interrupt request */ + LPTMR0_IRQn = 58u, /**< LPTIMER interrupt request */ + PORTA_IRQn = 59u, /**< Port A pin detect interrupt */ + PORTB_IRQn = 60u, /**< Port B pin detect interrupt */ + PORTC_IRQn = 61u, /**< Port C pin detect interrupt */ + PORTD_IRQn = 62u, /**< Port D pin detect interrupt */ + PORTE_IRQn = 63u, /**< Port E pin detect interrupt */ + SWI_IRQn = 64u, /**< Software interrupt */ + PDB1_IRQn = 68u, /**< PDB1 interrupt */ + FLEXIO_IRQn = 69u, /**< FlexIO Interrupt */ + CAN0_ORed_IRQn = 78u, /**< CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN0_Error_IRQn = 79u, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */ + CAN0_Wake_Up_IRQn = 80u, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_15_MB_IRQn = 81u, /**< CAN0 OR'ed Message buffer (0-15) */ + CAN0_ORed_16_31_MB_IRQn = 82u, /**< CAN0 OR'ed Message buffer (16-31) */ + CAN1_ORed_IRQn = 85u, /**< CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN1_Error_IRQn = 86u, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */ + CAN1_ORed_0_15_MB_IRQn = 88u, /**< CAN1 OR'ed Interrupt for Message buffer (0-15) */ + CAN2_ORed_IRQn = 92u, /**< CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN2_Error_IRQn = 93u, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus */ + CAN2_ORed_0_15_MB_IRQn = 95u, /**< CAN2 OR'ed Message buffer (0-15) */ + FTM0_Ch0_Ch1_IRQn = 99u, /**< FTM0 Channel 0 and 1 interrupt */ + FTM0_Ch2_Ch3_IRQn = 100u, /**< FTM0 Channel 2 and 3 interrupt */ + FTM0_Ch4_Ch5_IRQn = 101u, /**< FTM0 Channel 4 and 5 interrupt */ + FTM0_Ch6_Ch7_IRQn = 102u, /**< FTM0 Channel 6 and 7 interrupt */ + FTM0_Fault_IRQn = 103u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 104u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_Ch1_IRQn = 105u, /**< FTM1 Channel 0 and 1 interrupt */ + FTM1_Ch2_Ch3_IRQn = 106u, /**< FTM1 Channel 2 and 3 interrupt */ + FTM1_Ch4_Ch5_IRQn = 107u, /**< FTM1 Channel 4 and 5 interrupt */ + FTM1_Ch6_Ch7_IRQn = 108u, /**< FTM1 Channel 6 and 7 interrupt */ + FTM1_Fault_IRQn = 109u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 110u, /**< FTM1 Counter overflow and Reload interrupt */ + FTM2_Ch0_Ch1_IRQn = 111u, /**< FTM2 Channel 0 and 1 interrupt */ + FTM2_Ch2_Ch3_IRQn = 112u, /**< FTM2 Channel 2 and 3 interrupt */ + FTM2_Ch4_Ch5_IRQn = 113u, /**< FTM2 Channel 4 and 5 interrupt */ + FTM2_Ch6_Ch7_IRQn = 114u, /**< FTM2 Channel 6 and 7 interrupt */ + FTM2_Fault_IRQn = 115u, /**< FTM2 Fault interrupt */ + FTM2_Ovf_Reload_IRQn = 116u, /**< FTM2 Counter overflow and Reload interrupt */ + FTM3_Ch0_Ch1_IRQn = 117u, /**< FTM3 Channel 0 and 1 interrupt */ + FTM3_Ch2_Ch3_IRQn = 118u, /**< FTM3 Channel 2 and 3 interrupt */ + FTM3_Ch4_Ch5_IRQn = 119u, /**< FTM3 Channel 4 and 5 interrupt */ + FTM3_Ch6_Ch7_IRQn = 120u, /**< FTM3 Channel 6 and 7 interrupt */ + FTM3_Fault_IRQn = 121u, /**< FTM3 Fault interrupt */ + FTM3_Ovf_Reload_IRQn = 122u /**< FTM3 Counter overflow and Reload interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K144 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K144 Device Peripheral Access Layer for S32K144 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (2u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x40027000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))< 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK, LPUART2_CLK} + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPSPI module features */ + +/* @brief DMA instance used for LPSPI module */ +#define LPSPI_DMA_INSTANCE 0U + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* Interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn) +/* @brief Highest interrupt request number. */ +#define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn) +/**< Number of priority bits implemented in the NVIC */ +#define FEATURE_NVIC_PRIO_BITS (4U) +/* @brief Has software interrupt. */ +#define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u) +/* @brief Has pending interrupt state. */ +#define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u) +/* @brief Has active interrupt state. */ +#define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u) +/* @brief Multicore support for interrupts */ +#define FEATURE_INTERRUPT_MULTICORE_SUPPORT (0u) +/* @brief Registers in which the start of interrupt vector table needs to be configured */ +#define FEATURE_INTERRUPT_INT_VECTORS {&S32_SCB->VTOR} + + +/* System Control Block module features */ + +/* @brief VECTKEY value so that AIRCR register write is not ignored. */ +#define FEATURE_SCB_VECTKEY (0x05FAU) + + +/* SMC module features */ + +/* @brief Has stop option (register bit STOPCTRL[STOPO]). */ +#define FEATURE_SMC_HAS_STOPO (1U) +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FEATURE_SMC_HAS_PSTOPO (0U) +/* @brief Has WAIT and VLPW options. */ +#define FEATURE_SMC_HAS_WAIT_VLPW (0U) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1U) +/* @brief Value of SPLL source clock in the SCG_HCCR register */ +#define FEATURE_SCG_SPLL_VALUE (6U) +/* RCM module feature */ + +/* @brief Has existence of CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_EXISTENCE_CMU_LOSS_OF_CLOCK (0) +/* @brief Has CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK (0) +/* @brief Has sticky CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_STICKY_CMU_LOSS_OF_CLOCK (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K14x). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K14x). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K14x). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (4U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM back door. */ +#define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U) +/* @brief The MPU Slave Port Assignment for SRAM_L front door. */ +#define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U) +/* @brief The MPU Slave Port Assignment for SRAM_U front door. */ +#define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xF0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (28u) +#define FEATURE_MPU_SLAVE_WIDTH (4u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular transfer size: */ +#define FEATURE_DMA_TRANSFER_SIZE_16B +#define FEATURE_DMA_TRANSFER_SIZE_32B + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (16U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ + +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_LPUART2_RX = 6U, + EDMA_REQ_LPUART2_TX = 7U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_LPSPI2_RX = 18U, + EDMA_REQ_LPSPI2_TX = 19U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM2_CHANNEL_0 = 28U, + EDMA_REQ_FTM2_CHANNEL_1 = 29U, + EDMA_REQ_FTM2_CHANNEL_2 = 30U, + EDMA_REQ_FTM2_CHANNEL_3 = 31U, + EDMA_REQ_FTM2_CHANNEL_4 = 32U, + EDMA_REQ_FTM2_CHANNEL_5 = 33U, + EDMA_REQ_FTM2_CHANNEL_6 = 34U, + EDMA_REQ_FTM2_CHANNEL_7 = 35U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_FTM3_OR_CH0_CH7 = 37U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_ADC1 = 43U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_PDB1 = 47U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_FLEXCAN1 = 55U, + EDMA_REQ_FLEXCAN2 = 56U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + +/* LPI2C module features */ + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* FTM module features */ +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (0U) +/*! @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (4U) + +/* EWM module features */ + +/* @brief First byte of the EWM Service key */ +#define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U) +/* @brief Second byte of the EWM Service key */ +#define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU) +/* @brief EWM Compare High register maximum value */ +#define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU) +/* @brief EWM Compare Low register minimum value */ +#define FEATURE_EWM_CMPL_MIN_VALUE (0x00U) + +/* @brief Supports high speed run mode. */ +#define FEATURE_HAS_HIGH_SPEED_RUN_MODE (1U) +/* @brief Supports SPLL clock source. */ +#define FEATURE_HAS_SPLL_CLK (1U) + +/*! @brief Clock names. */ +typedef enum { + + /* Main clocks */ + CORE_CLK = 0u, /*!< Core clock */ + BUS_CLK = 1u, /*!< Bus clock */ + SLOW_CLK = 2u, /*!< Slow clock */ + CLKOUT_CLK = 3u, /*!< CLKOUT clock */ + + /* Other internal clocks used by peripherals. */ + SIRC_CLK = 4u, /*!< SIRC clock */ + FIRC_CLK = 5u, /*!< FIRC clock */ + SOSC_CLK = 6u, /*!< SOSC clock */ + SPLL_CLK = 7u, /*!< SPLL clock */ + RTC_CLKIN_CLK = 8u, /*!< RTC_CLKIN clock */ + SCG_CLKOUT_CLK = 9u, /*!< SCG CLK_OUT clock */ + + SIRCDIV1_CLK = 10u, /*!< SIRCDIV1 functional clock */ + SIRCDIV2_CLK = 11u, /*!< SIRCDIV2 functional clock */ + FIRCDIV1_CLK = 12u, /*!< FIRCDIV1 functional clock */ + FIRCDIV2_CLK = 13u, /*!< FIRCDIV2 functional clock */ + SOSCDIV1_CLK = 14u, /*!< SOSCDIV1 functional clock */ + SOSCDIV2_CLK = 15u, /*!< SOSCDIV2 functional clock */ + SPLLDIV1_CLK = 16u, /*!< SPLLDIV1 functional clock */ + SPLLDIV2_CLK = 17u, /*!< SPLLDIV2 functional clock */ + + SCG_END_OF_CLOCKS = 18u, /*!< End of SCG clocks */ + + /* SIM clocks */ + SIM_FTM0_CLOCKSEL = 21u, /*!< FTM0 External Clock Pin Select */ + SIM_FTM1_CLOCKSEL = 22u, /*!< FTM1 External Clock Pin Select */ + SIM_FTM2_CLOCKSEL = 23u, /*!< FTM2 External Clock Pin Select */ + SIM_FTM3_CLOCKSEL = 24u, /*!< FTM3 External Clock Pin Select */ + SIM_CLKOUTSELL = 25u, /*!< CLKOUT Select */ + SIM_RTCCLK_CLK = 26u, /*!< RTCCLK clock */ + SIM_LPO_CLK = 27u, /*!< LPO clock */ + SIM_LPO_1K_CLK = 28u, /*!< LPO 1KHz clock */ + SIM_LPO_32K_CLK = 29u, /*!< LPO 32KHz clock */ + SIM_LPO_128K_CLK = 30u, /*!< LPO 128KHz clock */ + SIM_EIM_CLK = 31u, /*!< EIM clock source */ + SIM_ERM_CLK = 32u, /*!< ERM clock source */ + SIM_DMA_CLK = 33u, /*!< DMA clock source */ + SIM_MPU_CLK = 34u, /*!< MPU clock source */ + SIM_MSCM_CLK = 35u, /*!< MSCM clock source */ + SIM_END_OF_CLOCKS = 36u, /*!< End of SIM clocks */ + + /* PCC clocks */ + CMP0_CLK = 41u, /*!< CMP0 clock source */ + CRC0_CLK = 42u, /*!< CRC0 clock source */ + DMAMUX0_CLK = 43u, /*!< DMAMUX0 clock source */ + EWM0_CLK = 44u, /*!< EWM0 clock source */ + PORTA_CLK = 45u, /*!< PORTA clock source */ + PORTB_CLK = 46u, /*!< PORTB clock source */ + PORTC_CLK = 47u, /*!< PORTC clock source */ + PORTD_CLK = 48u, /*!< PORTD clock source */ + PORTE_CLK = 49u, /*!< PORTE clock source */ + RTC0_CLK = 50u, /*!< RTC0 clock source */ + PCC_END_OF_BUS_CLOCKS = 51u, /*!< End of BUS clocks */ + FlexCAN0_CLK = 52u, /*!< FlexCAN0 clock source */ + FlexCAN1_CLK = 53u, /*!< FlexCAN1 clock source */ + FlexCAN2_CLK = 54u, /*!< FlexCAN2 clock source */ + PDB0_CLK = 55u, /*!< PDB0 clock source */ + PDB1_CLK = 56u, /*!< PDB1 clock source */ + PCC_END_OF_SYS_CLOCKS = 57u, /*!< End of SYS clocks */ + FTFC0_CLK = 58u, /*!< FTFC0 clock source */ + PCC_END_OF_SLOW_CLOCKS = 59u, /*!< End of SLOW clocks */ + FTM0_CLK = 60u, /*!< FTM0 clock source */ + FTM1_CLK = 61u, /*!< FTM1 clock source */ + FTM2_CLK = 62u, /*!< FTM2 clock source */ + FTM3_CLK = 63u, /*!< FTM3 clock source */ + PCC_END_OF_ASYNCH_DIV1_CLOCKS= 64u, /*!< End of ASYNCH DIV1 clocks */ + ADC0_CLK = 65u, /*!< ADC0 clock source */ + ADC1_CLK = 66u, /*!< ADC1 clock source */ + FLEXIO0_CLK = 67u, /*!< FLEXIO0 clock source */ + LPI2C0_CLK = 68u, /*!< LPI2C0 clock source */ + LPIT0_CLK = 69u, /*!< LPIT0 clock source */ + LPSPI0_CLK = 70u, /*!< LPSPI0 clock source */ + LPSPI1_CLK = 71u, /*!< LPSPI1 clock source */ + LPSPI2_CLK = 72u, /*!< LPSPI2 clock source */ + LPTMR0_CLK = 73u, /*!< LPTMR0 clock source */ + LPUART0_CLK = 74u, /*!< LPUART0 clock source */ + LPUART1_CLK = 75u, /*!< LPUART1 clock source */ + LPUART2_CLK = 76u, /*!< LPUART2 clock source */ + PCC_END_OF_ASYNCH_DIV2_CLOCKS= 77u, /*!< End of ASYNCH DIV2 clocks */ + PCC_END_OF_CLOCKS = 78u, /*!< End of PCC clocks */ + CLOCK_NAME_COUNT = 79u, /*!< The total number of entries */ +} clock_names_t; + +#define PCC_INVALID_INDEX 0 + + /*! @brief PCC clock name mappings + * Mappings between clock names and peripheral clock control indexes. + * If there is no peripheral clock control index for a clock name, + * then the corresponding value is PCC_INVALID_INDEX. + */ +#define PCC_CLOCK_NAME_MAPPINGS \ +{ \ +PCC_INVALID_INDEX, /*!< Core clock 0 */ \ +PCC_INVALID_INDEX, /*!< Bus clock 1 */ \ +PCC_INVALID_INDEX, /*!< Slow clock 2 */ \ +PCC_INVALID_INDEX, /*!< CLKOUT clock 3 */ \ +PCC_INVALID_INDEX, /*!< SIRC clock 4 */ \ +PCC_INVALID_INDEX, /*!< FIRC clock 5 */ \ +PCC_INVALID_INDEX, /*!< SOSC clock 6 */ \ +PCC_INVALID_INDEX, /*!< SPLL clock 7 */ \ +PCC_INVALID_INDEX, /*!< RTC_CLKIN clock 8 */ \ +PCC_INVALID_INDEX, /*!< SCG CLK_OUT clock 9 */ \ +PCC_INVALID_INDEX, /*!< SIRCDIV1 functional clock 10 */ \ +PCC_INVALID_INDEX, /*!< SIRCDIV2 functional clock 11 */ \ +PCC_INVALID_INDEX, /*!< FIRCDIV1 functional clock 12 */ \ +PCC_INVALID_INDEX, /*!< FIRCDIV2 functional clock 13 */ \ +PCC_INVALID_INDEX, /*!< SOSCDIV1 functional clock 14 */ \ +PCC_INVALID_INDEX, /*!< SOSCDIV2 functional clock 15 */ \ +PCC_INVALID_INDEX, /*!< SPLLDIV1 functional clock 16 */ \ +PCC_INVALID_INDEX, /*!< SPLLDIV2 functional clock 17 */ \ +PCC_INVALID_INDEX, /*!< End of SCG clocks 18 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 19 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 20 */ \ +PCC_INVALID_INDEX, /*!< FTM0 External Clock Pin Select 21 */ \ +PCC_INVALID_INDEX, /*!< FTM1 External Clock Pin Select 22 */ \ +PCC_INVALID_INDEX, /*!< FTM2 External Clock Pin Select 23 */ \ +PCC_INVALID_INDEX, /*!< FTM3 External Clock Pin Select 24 */ \ +PCC_INVALID_INDEX, /*!< CLKOUT Select 25 */ \ +PCC_INVALID_INDEX, /*!< CLK32K clock 26 */ \ +PCC_INVALID_INDEX, /*!< LPO clock 27 */ \ +PCC_INVALID_INDEX, /*!< LPO 1KHz clock 28 */ \ +PCC_INVALID_INDEX, /*!< LPO 32KHz clock 29 */ \ +PCC_INVALID_INDEX, /*!< LPO 128KHz clock 30 */ \ +PCC_INVALID_INDEX, /*!< EIM clock source 31 */ \ +PCC_INVALID_INDEX, /*!< ERM clock source 32 */ \ +PCC_INVALID_INDEX, /*!< DMA clock source 33 */ \ +PCC_INVALID_INDEX, /*!< MPU clock source 34 */ \ +PCC_INVALID_INDEX, /*!< MSCM clock source 35 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 36 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 37 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 38 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 39 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 40 */ \ +PCC_CMP0_INDEX, /*!< CMP0 clock source 41 */ \ +PCC_CRC_INDEX, /*!< CRC clock source 42 */ \ +PCC_DMAMUX_INDEX, /*!< DMAMUX clock source 43 */ \ +PCC_EWM_INDEX, /*!< EWM clock source 44 */ \ +PCC_PORTA_INDEX, /*!< PORTA clock source 45 */ \ +PCC_PORTB_INDEX, /*!< PORTB clock source 46 */ \ +PCC_PORTC_INDEX, /*!< PORTC clock source 47 */ \ +PCC_PORTD_INDEX, /*!< PORTD clock source 48 */ \ +PCC_PORTE_INDEX, /*!< PORTE clock source 49 */ \ +PCC_RTC_INDEX, /*!< RTC clock source 50 */ \ +PCC_INVALID_INDEX, /*!< End of BUS clocks 51 */ \ +PCC_FlexCAN0_INDEX, /*!< FlexCAN0 clock source 52 */ \ +PCC_FlexCAN1_INDEX, /*!< FlexCAN1 clock source 53 */ \ +PCC_FlexCAN2_INDEX, /*!< FlexCAN2 clock source 54 */ \ +PCC_PDB0_INDEX, /*!< PDB0 clock source 55 */ \ +PCC_PDB1_INDEX, /*!< PDB1 clock source 56 */ \ +PCC_INVALID_INDEX, /*!< End of SYS clocks 57 */ \ +PCC_FTFC_INDEX, /*!< FTFC clock source 58 */ \ +PCC_INVALID_INDEX, /*!< End of SLOW clocks 59 */ \ +PCC_FTM0_INDEX, /*!< FTM0 clock source 60 */ \ +PCC_FTM1_INDEX, /*!< FTM1 clock source 61 */ \ +PCC_FTM2_INDEX, /*!< FTM2 clock source 62 */ \ +PCC_FTM3_INDEX, /*!< FTM3 clock source 63 */ \ +PCC_INVALID_INDEX, /*!< End of ASYNCH DIV1 clocks 64 */ \ +PCC_ADC0_INDEX, /*!< ADC0 clock source 65 */ \ +PCC_ADC1_INDEX, /*!< ADC1 clock source 66 */ \ +PCC_FlexIO_INDEX, /*!< FLEXIO clock source 67 */ \ +PCC_LPI2C0_INDEX, /*!< LPI2C0 clock source 68 */ \ +PCC_LPIT_INDEX, /*!< LPIT clock source 69 */ \ +PCC_LPSPI0_INDEX, /*!< LPSPI0 clock source 70 */ \ +PCC_LPSPI1_INDEX, /*!< LPSPI1 clock source 71 */ \ +PCC_LPSPI2_INDEX, /*!< LPSPI2 clock source 72 */ \ +PCC_LPTMR0_INDEX, /*!< LPTMR0 clock source 73 */ \ +PCC_LPUART0_INDEX, /*!< LPUART0 clock source 74 */ \ +PCC_LPUART1_INDEX, /*!< LPUART1 clock source 75 */ \ +PCC_LPUART2_INDEX, /*!< LPUART2 clock source 76 */ \ +PCC_INVALID_INDEX, /*!< End of ASYNCH DIV2 clocks 77 */ \ +PCC_INVALID_INDEX, /*!< End of PCC clocks 78 */ \ +} + +/*! @brief Peripheral instance features + * List of features that are supported by a peripheral instance + */ +#define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */ +#define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */ +#define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */ +#define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */ +#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */ +#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */ +#define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */ +#define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */ +#define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */ + +/*! @brief Peripheral features. +* List of features for each clock name. If a clock name is not +* a peripheral, no feature is supported. +*/ +#define PERIPHERAL_FEATURES \ +{ \ +(NO_PERIPHERAL_FEATURE), /*!< Core clock 0 */ \ +(NO_PERIPHERAL_FEATURE), /*!< Bus clock 1 */ \ +(NO_PERIPHERAL_FEATURE), /*!< Slow clock 2 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLKOUT clock 3 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SIRC clock 4 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FIRC clock 5 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SOSC clock 6 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SPLL clock 7 */ \ +(NO_PERIPHERAL_FEATURE), /*!< RTC_CLKIN clock 8 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SCG CLK_OUT clock 9 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SCG clocks 10 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 11 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 12 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 13 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 14 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 15 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 16 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 17 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 18 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 19 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 20 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM0 External Clock Pin Select 21 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM1 External Clock Pin Select 22 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM2 External Clock Pin Select 23 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM3 External Clock Pin Select 24 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLKOUT Select 25 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLK32K clock 26 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO clock 27 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 1KHz clock 28 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 32KHz clock 29 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 128KHz clock 30 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< EIM clock source 31 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< ERM clock source 32 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< DMA clock source 33 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< MPU clock source 34 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< MSCM clock source 35 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 36 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 37 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 38 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 39 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 40 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< CMP0 clock source 41 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< CRC clock source 42 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< DMAMUX clock source 43 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< EWM clock source 44 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTA clock source 45 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTB clock source 46 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTC clock source 47 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTD clock source 48 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTE clock source 49 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< RTC clock source 50 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of BUS clocks 51 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN0 clock source 52 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN1 clock source 53 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN2 clock source 54 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< PDB0 clock source 55 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< PDB1 clock source 56 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SYS clocks 57 */ \ +(HAS_INT_CLOCK_FROM_SLOW_CLOCK), /*!< FTFC clock source 58 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SLOW clocks 59 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM0 clock source 60 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM1 clock source 61 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM2 clock source 62 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM3 clock source 63 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of ASYNCH DIV1 clocks 64 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< ADC0 clock source 65 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< ADC1 clock source 66 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< FLEXIO clock source 67 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPI2C0 clock source 68 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPIT clock source 69 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI0 clock source 70 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI1 clock source 71 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI2 clock source 72 */ \ +(HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPTMR0 clock source 73 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART0 clock source 74 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART1 clock source 75 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART2 clock source 76 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of ASYNCH DIV2 clocks 77 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of PCC clocks 78 */ \ +} + +/* Time to wait for SIRC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SIRC_STABILIZATION_TIMEOUT 100U + +/* Time to wait for FIRC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define FIRC_STABILIZATION_TIMEOUT 20U + +/* Time to wait for SOSC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SOSC_STABILIZATION_TIMEOUT 3205000U; + +/* Time to wait for SPLL to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SPLL_STABILIZATION_TIMEOUT 1000U; + + +/*! @brief Temporary system clock source configurations. + * Each line represents the SYS(CORE), BUS and SLOW(FLASH) dividers + * for SIRC, FIRC, SOSC and SPLL clock sources. + * + * SYS_CLK BUS_CLK SLOW_CLK + * SIRC * * * + * FIRC * * * + * SOSC * * * + * SPLL * * * + */ +#define TMP_SIRC_CLK 0U +#define TMP_FIRC_CLK 1U +#define TMP_SOSC_CLK 2U +#define TMP_SPLL_CLK 3U + +#define TMP_SYS_DIV 0U +#define TMP_BUS_DIV 1U +#define TMP_SLOW_DIV 2U + +#define TMP_SYS_CLK_NO 4U +#define TMP_SYS_DIV_NO 3U + +#define TMP_SYSTEM_CLOCK_CONFIGS \ +{ /* SYS_CLK BUS_CLK SLOW_CLK */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SIRC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, /*!< Dividers for FIRC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SOSC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SPLL */ \ +} + +/* Do not use the old names of the renamed symbols */ +/* #define DO_NOT_USE_DEPRECATED_SYMBOLS */ + +/*! START !DO_NOT_USE_DEPRECATED_SYMBOLS + * These symbols have been renamed. + * The old names (deprecated symbols) + * are defined for backward compatibility. + */ +#if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS) +#define CORE_CLOCK CORE_CLK +#define BUS_CLOCK BUS_CLK +#define SLOW_CLOCK SLOW_CLK +#define CLKOUT_CLOCK CLKOUT_CLK +#define SIRC_CLOCK SIRC_CLK +#define FIRC_CLOCK FIRC_CLK +#define SOSC_CLOCK SOSC_CLK +#define SPLL_CLOCK SPLL_CLK +#define RTC_CLKIN_CLOCK RTC_CLKIN_CLK +#define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK +#define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK +#define SIM_LPO_CLOCK SIM_LPO_CLK +#define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK +#define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK +#define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK +#define SIM_EIM_CLOCK SIM_EIM_CLK +#define SIM_ERM_CLOCK SIM_ERM_CLK +#define SIM_DMA_CLOCK SIM_DMA_CLK +#define SIM_MPU_CLOCK SIM_MPU_CLK +#define SIM_MSCM_CLOCK SIM_MSCM_CLK +#define PCC_DMAMUX0_CLOCK DMAMUX0_CLK +#define PCC_CRC0_CLOCK CRC0_CLK +#define PCC_RTC0_CLOCK RTC0_CLK +#define PCC_PORTA_CLOCK PORTA_CLK +#define PCC_PORTB_CLOCK PORTB_CLK +#define PCC_PORTC_CLOCK PORTC_CLK +#define PCC_PORTD_CLOCK PORTD_CLK +#define PCC_PORTE_CLOCK PORTE_CLK +#define PCC_EWM0_CLOCK EWM0_CLK +#define PCC_CMP0_CLOCK CMP0_CLK +#define PCC_FlexCAN0_CLOCK FlexCAN0_CLK +#define PCC_FlexCAN1_CLOCK FlexCAN1_CLK +#define PCC_FlexCAN2_CLOCK FlexCAN2_CLK +#define PCC_PDB1_CLOCK PDB1_CLK +#define PCC_PDB0_CLOCK PDB0_CLK +#define PCC_FTFC0_CLOCK FTFC0_CLK +#define PCC_FTM0_CLOCK FTM0_CLK +#define PCC_FTM1_CLOCK FTM1_CLK +#define PCC_FTM2_CLOCK FTM2_CLK +#define PCC_FTM3_CLOCK FTM3_CLK +#define PCC_ADC1_CLOCK ADC1_CLK +#define PCC_LPSPI0_CLOCK LPSPI0_CLK +#define PCC_LPSPI1_CLOCK LPSPI1_CLK +#define PCC_LPSPI2_CLOCK LPSPI2_CLK +#define PCC_LPIT0_CLOCK LPIT0_CLK +#define PCC_ADC0_CLOCK ADC0_CLK +#define PCC_LPTMR0_CLOCK LPTMR0_CLK +#define PCC_FLEXIO0_CLOCK FLEXIO0_CLK +#define PCC_LPI2C0_CLOCK LPI2C0_CLK +#define PCC_LPUART0_CLOCK LPUART0_CLK +#define PCC_LPUART1_CLOCK LPUART1_CLK +#define PCC_LPUART2_CLOCK LPUART2_CLK +#endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */ + + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK, ADC1_CLK} + +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (4U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK, LPSPI2_CLK}; + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN10 = 12U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN11 = 13U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_FTM2_INIT_TRIG = 26U, + TRGMUX_TRIG_SOURCE_FTM2_EXT_TRIG = 27U, + TRGMUX_TRIG_SOURCE_FTM3_INIT_TRIG = 28U, + TRGMUX_TRIG_SOURCE_FTM3_EXT_TRIG = 29U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_ADC1_SC1A_COCO = 32U, + TRGMUX_TRIG_SOURCE_ADC1_SC1B_COCO = 33U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_PDB1_CH0_TRIG = 37U, + TRGMUX_TRIG_SOURCE_PDB1_PULSE_OUT = 39U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT6 = 10U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT7 = 11U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA0 = 16U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA1 = 17U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA2 = 18U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA3 = 19U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_FTM2_HWTRIG0 = 48U, + TRGMUX_TARGET_MODULE_FTM2_FAULT0 = 49U, + TRGMUX_TARGET_MODULE_FTM2_FAULT1 = 50U, + TRGMUX_TARGET_MODULE_FTM2_FAULT2 = 51U, + TRGMUX_TARGET_MODULE_FTM3_HWTRIG0 = 52U, + TRGMUX_TARGET_MODULE_FTM3_FAULT0 = 53U, + TRGMUX_TARGET_MODULE_FTM3_FAULT1 = 54U, + TRGMUX_TARGET_MODULE_FTM3_FAULT2 = 55U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_PDB1_TRG_IN = 60U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT6, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT7, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM2_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM3_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_PDB1_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + +/* ISELED Pins */ + +#define ISELED_PIN_0 0 /*PTA10*/ +#define ISELED_PIN_1 1 /*PTD0*/ +#define ISELED_PIN_2 2 /*PTD9*/ +#define ISELED_PIN_3 3 /*PTA11*/ +#define ISELED_PIN_4 4 /*PTD1*/ +#define ISELED_PIN_5 5 /*PTD8*/ +#define ISELED_PIN_6 6 /*PTA0*/ +#define ISELED_PIN_7 7 /*PTE15*/ +#define ISELED_PIN_8 8 /*PTA1*/ +#define ISELED_PIN_9 9 /*PTE16*/ +#define ISELED_PIN_10 10 /*PTA2*/ +#define ISELED_PIN_11 11 /*PTD2*/ +#define ISELED_PIN_12 12 /*PTE10*/ +#define ISELED_PIN_13 13 /*PTA3*/ +#define ISELED_PIN_14 14 /*PTE11*/ +#define ISELED_PIN_15 15 /*PTD3*/ +#define ISELED_PIN_16 16 /*PTA8*/ +#define ISELED_PIN_17 17 /*PTE3*/ +#define ISELED_PIN_18 18 /*PTA9*/ +#define ISELED_PIN_19 19 /*PTE3*/ + +#define ISELED_PIN_20 20 /*PTB2*/ +#define ISELED_PIN_21 21 /*PTB1*/ +#define ISELED_PIN_22 22 /*PTD15*/ +#define ISELED_PIN_23 23 /*PTB4*/ +#define ISELED_PIN_24 24 /*PTE0*/ +#define ISELED_PIN_25 25 /*PTE2*/ +#define ISELED_PIN_26 26 /*PTD0*/ +#define ISELED_PIN_27 27 /*PTD2*/ +#define ISELED_PIN_28 28 /*PTB14*/ +#define ISELED_PIN_29 29 /*PTB16*/ +#define ISELED_PIN_30 30 /*PTE15*/ +#define ISELED_PIN_31 31 /*PTA8*/ +#define ISELED_PIN_32 32 /*PTC15*/ +#define ISELED_PIN_33 33 /*PTC1*/ + +#define ISELED_PIN_34 34 /*PTE1*/ +#define ISELED_PIN_35 35 /*PTB3*/ +#define ISELED_PIN_36 36 /*PTD16*/ +#define ISELED_PIN_37 37 /*PTB15*/ +#define ISELED_PIN_38 38 /*PTD1*/ +#define ISELED_PIN_39 39 /*PTC0*/ + + +#define MAX_NR_OF_STRIPS 13U + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (1) + +#endif /* S32K144_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/devassert.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/device_registers.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/device_registers.h new file mode 100644 index 00000000..f56cf068 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/device_registers.h @@ -0,0 +1,70 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if (defined(CPU_S32K144HFT0VLLT) || defined(CPU_S32K144LFT0MLLT)) + + #define S32K14x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm4.h" + + #define S32K144_SERIES + + /* Register definitions */ + #include "S32K144.h" + /* CPU specific feature definitions */ + #include "S32K144_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/s32_core_cm4.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/s32_core_cm4.h new file mode 100644 index 00000000..aa271645 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/s32_core_cm4.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm4.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION: ARM Compiler + */ + +#if !defined (CORE_CM4_H) +#define CORE_CM4_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#define BKPT_ASM __asm("BKPT #0\n\t") + + +/** \brief Enable FPU + * + * ENABLE_FPU indicates whether SystemInit will enable the Floating point unit (FPU) + */ +#if defined (__GNUC__) || defined (__ARMCC_VERSION) +#if defined (__VFP_FP__) && !defined (__SOFTFP__) +#define ENABLE_FPU +#endif + +#elif defined (__ICCARM__) +#if defined __ARMVFP__ +#define ENABLE_FPU +#endif + +#elif defined (__ghs__) || defined (__DCC__) +#if defined (__VFP__) +#define ENABLE_FPU +#endif +#endif /* if defined (__GNUC__) */ + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#else +#define STANDBY() __asm("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + +/** \brief Reverse byte order in a word. + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\"") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm4 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Section placement. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define PLACE_IN_SECTION(x) __attribute__((section(x))) +#elif defined ( __ICCARM__ ) + #define PLACE_IN_SECTION(x) _Pragma(stringify(section=x)) +#else + /* Keep compatibility with software analysis tools */ + #define PLACE_IN_SECTION(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM4_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.c new file mode 100644 index 00000000..a8e32c84 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2015 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K144.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ + /* FPU ENABLE*/ +/**************************************************************************/ +#ifdef ENABLE_FPU + /* Enable CP10 and CP11 coprocessors */ + S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK); +#ifdef ERRATA_E6940 + /* Disable lazy context save of floating point state by clearing LSPEN bit + * Workaround for errata e6940 */ + S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK); +#endif +#endif /* ENABLE_FPU */ + +/**************************************************************************/ + /* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ + +/**************************************************************************/ + /* ENABLE CACHE */ +/**************************************************************************/ +#if defined(I_CACHE) && (ICACHE_ENABLE == 1) + /* Invalidate and enable code cache */ + LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1); +#endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider, prediv, multi; + bool validSystemClockSource = true; + static const uint32_t fircFreq[] = { + FEATURE_SCG_FIRC_FREQ0, + }; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + + if (regValue != 0U) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + SCGOUTClock= fircFreq[regValue]; + break; + case 0x6: + /* System PLL */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U; + multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U; + SCGOUTClock = SCGOUTClock * multi / (prediv * 2U); + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.h new file mode 100644 index 00000000..c7fcf0a7 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/lib/system_S32K144.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2015 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K144*/ +/*! @{*/ + +/*! + * @file system_S32K144.h + * @brief Device specific configuration file for S32K144 + */ + +#ifndef SYSTEM_S32K144_H_ +#define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Cache enablement */ +#ifndef ICACHE_ENABLE +#define ICACHE_ENABLE 0 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog, enables FPU. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K144_H_) */ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c new file mode 100644 index 00000000..fe8a10cd --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c @@ -0,0 +1,208 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/main.c +* \brief Bootloader application source file. +* \ingroup Boot_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ +#include "device_registers.h" /* device registers */ +#include "system_S32K144.h" /* device sconfiguration */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +int main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader. */ + BootInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Run the bootloader task. */ + BootTask(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; + /* Configure SW2 (PC12) GPIO pin for (optional) backdoor entry input. */ + /* Input GPIO pin configuration. PC12 = GPIO, MUX = ALT1. */ + PORTC->PCR[12] |= PORT_PCR_MUX(1); + /* Disable pull device, as SW2 already has a pull down resistor on the board. */ + PORTC->PCR[12] &= ~PORT_PCR_PE(1); + /* Configure and enable Port C pin 12 GPIO as digital input */ + PTC->PDDR &= ~GPIO_PDDR_PDD(1 << 12U); + PTC->PIDR &= ~GPIO_PIDR_PID(1 << 12U); +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PC6 = UART1 RX, MUX = ALT2. */ + PORTC->PCR[6] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PC7 = UART1 TX, MUX = ALT2. */ + PORTC->PCR[7] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It uses the 8 MHz external crystal as a source for the +** PLL and configures the normal RUN mode for the following clock settings: +** - SPLL_CLK = 160 MHz +** - CORE_CLK = 80 MHz +** - SYS_CLK = 80 MHz +** - BUS_CLK = 40 MHz +** - FLASH_CLK = 26.67 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (8 MHz) ------------------------------------------- */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=2: Medium freq (SOSC betw 1MHz-8MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- SPLL Initialization (160 MHz) ----------------------------------------- */ + /* Ensure SPLLCSR is unlocked. */ + while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK) + { + ; + } + /* SPLLEN=0: SPLL is disabled (default). */ + SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK; + /* SPLLDIV1 divide by 2 and SPLLDIV2 divide by 4. */ + SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(3); + /* PREDIV=0: Divide SOSC_CLK by 0+1=1. + * MULT=24: Multiply sys pll by 4+24=40. + * SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz. + */ + SCG->SPLLCFG = SCG_SPLLCFG_MULT(24); + /* Ensure SPLLCSR is unlocked. */ + while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK) + { + ; + } + /* LK=0: SPLLCSR can be written. + * SPLLCMRE=0: SPLL CLK monitor IRQ if enabled. + * SPLLCM=0: SPLL CLK monitor disabled. + * SPLLSTEN=0: SPLL disabled in Stop modes. + * SPLLEN=1: Enable SPLL. + */ + SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK; + /* Wait for SPLL to become valid. */ + while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) + { + ; + } + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL ------------------ */ + /* Note that flash memory should not be programmed or erased when the microcontroller + * is operating in VLPr or HSRUN mode. Therefore normal RUN mode is configured. + */ + /* Select PLL as clock source. + * DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz. + * DIVBUS=1, div. by 2: bus clock = 40 MHz. + * DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz. + */ + SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) | + SCG_RCCR_DIVSLOW(2); + /* Wait until system clock source is SPLL. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/startup_S32K144.s b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/startup_S32K144.s new file mode 100644 index 00000000..677c5a18 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Boot/startup_S32K144.s @@ -0,0 +1,693 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_S32K144.s +; @purpose: IAR Startup File +; S32K144 +; @version: 2.0 +; @date: 2017-1-10 +; @build: b170107 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; Copyright 2016-2017 NXP +; All rights reserved. +; +; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN main + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete + DCD DMA8_IRQHandler ;DMA channel 8 transfer complete + DCD DMA9_IRQHandler ;DMA channel 9 transfer complete + DCD DMA10_IRQHandler ;DMA channel 10 transfer complete + DCD DMA11_IRQHandler ;DMA channel 11 transfer complete + DCD DMA12_IRQHandler ;DMA channel 12 transfer complete + DCD DMA13_IRQHandler ;DMA channel 13 transfer complete + DCD DMA14_IRQHandler ;DMA channel 14 transfer complete + DCD DMA15_IRQHandler ;DMA channel 15 transfer complete + DCD DMA_Error_IRQHandler ;DMA error interrupt channels 0-15 + DCD MCM_IRQHandler ;FPU sources + DCD FTFC_IRQHandler ;FTFC Command complete + DCD Read_Collision_IRQHandler ;FTFC Read collision + DCD LVD_LVW_IRQHandler ;PMC Low voltage detect interrupt + DCD FTFC_Fault_IRQHandler ;FTFC Double bit fault detect + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM + DCD RCM_IRQHandler ;RCM Asynchronous Interrupt + DCD LPI2C0_Master_IRQHandler ;LPI2C0 Master Interrupt + DCD LPI2C0_Slave_IRQHandler ;LPI2C0 Slave Interrupt + DCD LPSPI0_IRQHandler ;LPSPI0 Interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 Interrupt + DCD LPSPI2_IRQHandler ;LPSPI2 Interrupt + DCD Reserved45_IRQHandler ;Reserved Interrupt 45 + DCD Reserved46_IRQHandler ;Reserved Interrupt 46 + DCD LPUART0_RxTx_IRQHandler ;LPUART0 Transmit / Receive Interrupt + DCD Reserved48_IRQHandler ;Reserved Interrupt 48 + DCD LPUART1_RxTx_IRQHandler ;LPUART1 Transmit / Receive Interrupt + DCD Reserved50_IRQHandler ;Reserved Interrupt 50 + DCD LPUART2_RxTx_IRQHandler ;LPUART2 Transmit / Receive Interrupt + DCD Reserved52_IRQHandler ;Reserved Interrupt 52 + DCD Reserved53_IRQHandler ;Reserved Interrupt 53 + DCD Reserved54_IRQHandler ;Reserved Interrupt 54 + DCD ADC0_IRQHandler ;ADC0 interrupt request. + DCD ADC1_IRQHandler ;ADC1 interrupt request. + DCD CMP0_IRQHandler ;CMP0 interrupt request + DCD Reserved58_IRQHandler ;Reserved Interrupt 58 + DCD Reserved59_IRQHandler ;Reserved Interrupt 59 + DCD ERM_single_fault_IRQHandler ;ERM single bit error correction + DCD ERM_double_fault_IRQHandler ;ERM double bit error non-correctable + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD LPIT0_Ch0_IRQHandler ;LPIT0 channel 0 overflow interrupt + DCD LPIT0_Ch1_IRQHandler ;LPIT0 channel 1 overflow interrupt + DCD LPIT0_Ch2_IRQHandler ;LPIT0 channel 2 overflow interrupt + DCD LPIT0_Ch3_IRQHandler ;LPIT0 channel 3 overflow interrupt + DCD PDB0_IRQHandler ;PDB0 interrupt + DCD Reserved69_IRQHandler ;Reserved Interrupt 69 + DCD Reserved70_IRQHandler ;Reserved Interrupt 70 + DCD Reserved71_IRQHandler ;Reserved Interrupt 71 + DCD Reserved72_IRQHandler ;Reserved Interrupt 72 + DCD SCG_IRQHandler ;SCG bus interrupt request + DCD LPTMR0_IRQHandler ;LPTIMER interrupt request + DCD PORTA_IRQHandler ;Port A pin detect interrupt + DCD PORTB_IRQHandler ;Port B pin detect interrupt + DCD PORTC_IRQHandler ;Port C pin detect interrupt + DCD PORTD_IRQHandler ;Port D pin detect interrupt + DCD PORTE_IRQHandler ;Port E pin detect interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD Reserved81_IRQHandler ;Reserved Interrupt 81 + DCD Reserved82_IRQHandler ;Reserved Interrupt 82 + DCD Reserved83_IRQHandler ;Reserved Interrupt 83 + DCD PDB1_IRQHandler ;PDB1 interrupt + DCD FLEXIO_IRQHandler ;FlexIO Interrupt + DCD Reserved86_IRQHandler ;Reserved Interrupt 86 + DCD Reserved87_IRQHandler ;Reserved Interrupt 87 + DCD Reserved88_IRQHandler ;Reserved Interrupt 88 + DCD Reserved89_IRQHandler ;Reserved Interrupt 89 + DCD Reserved90_IRQHandler ;Reserved Interrupt 90 + DCD Reserved91_IRQHandler ;Reserved Interrupt 91 + DCD Reserved92_IRQHandler ;Reserved Interrupt 92 + DCD Reserved93_IRQHandler ;Reserved Interrupt 93 + DCD CAN0_ORed_IRQHandler ;CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN0_Error_IRQHandler ;CAN0 Interrupt indicating that errors were detected on the CAN bus + DCD CAN0_Wake_Up_IRQHandler ;CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode + DCD CAN0_ORed_0_15_MB_IRQHandler ;CAN0 OR'ed Message buffer (0-15) + DCD CAN0_ORed_16_31_MB_IRQHandler ;CAN0 OR'ed Message buffer (16-31) + DCD Reserved99_IRQHandler ;Reserved Interrupt 99 + DCD Reserved100_IRQHandler ;Reserved Interrupt 100 + DCD CAN1_ORed_IRQHandler ;CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN1_Error_IRQHandler ;CAN1 Interrupt indicating that errors were detected on the CAN bus + DCD Reserved103_IRQHandler ;Reserved Interrupt 103 + DCD CAN1_ORed_0_15_MB_IRQHandler ;CAN1 OR'ed Interrupt for Message buffer (0-15) + DCD Reserved105_IRQHandler ;Reserved Interrupt 105 + DCD Reserved106_IRQHandler ;Reserved Interrupt 106 + DCD Reserved107_IRQHandler ;Reserved Interrupt 107 + DCD CAN2_ORed_IRQHandler ;CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN2_Error_IRQHandler ;CAN2 Interrupt indicating that errors were detected on the CAN bus + DCD Reserved110_IRQHandler ;Reserved Interrupt 110 + DCD CAN2_ORed_0_15_MB_IRQHandler ;CAN2 OR'ed Message buffer (0-15) + DCD Reserved112_IRQHandler ;Reserved Interrupt 112 + DCD Reserved113_IRQHandler ;Reserved Interrupt 113 + DCD Reserved114_IRQHandler ;Reserved Interrupt 114 + DCD FTM0_Ch0_Ch1_IRQHandler ;FTM0 Channel 0 and 1 interrupt + DCD FTM0_Ch2_Ch3_IRQHandler ;FTM0 Channel 2 and 3 interrupt + DCD FTM0_Ch4_Ch5_IRQHandler ;FTM0 Channel 4 and 5 interrupt + DCD FTM0_Ch6_Ch7_IRQHandler ;FTM0 Channel 6 and 7 interrupt + DCD FTM0_Fault_IRQHandler ;FTM0 Fault interrupt + DCD FTM0_Ovf_Reload_IRQHandler ;FTM0 Counter overflow and Reload interrupt + DCD FTM1_Ch0_Ch1_IRQHandler ;FTM1 Channel 0 and 1 interrupt + DCD FTM1_Ch2_Ch3_IRQHandler ;FTM1 Channel 2 and 3 interrupt + DCD FTM1_Ch4_Ch5_IRQHandler ;FTM1 Channel 4 and 5 interrupt + DCD FTM1_Ch6_Ch7_IRQHandler ;FTM1 Channel 6 and 7 interrupt + DCD FTM1_Fault_IRQHandler ;FTM1 Fault interrupt + DCD FTM1_Ovf_Reload_IRQHandler ;FTM1 Counter overflow and Reload interrupt + DCD FTM2_Ch0_Ch1_IRQHandler ;FTM2 Channel 0 and 1 interrupt + DCD FTM2_Ch2_Ch3_IRQHandler ;FTM2 Channel 2 and 3 interrupt + DCD FTM2_Ch4_Ch5_IRQHandler ;FTM2 Channel 4 and 5 interrupt + DCD FTM2_Ch6_Ch7_IRQHandler ;FTM2 Channel 6 and 7 interrupt + DCD FTM2_Fault_IRQHandler ;FTM2 Fault interrupt + DCD FTM2_Ovf_Reload_IRQHandler ;FTM2 Counter overflow and Reload interrupt + DCD FTM3_Ch0_Ch1_IRQHandler ;FTM3 Channel 0 and 1 interrupt + DCD FTM3_Ch2_Ch3_IRQHandler ;FTM3 Channel 2 and 3 interrupt + DCD FTM3_Ch4_Ch5_IRQHandler ;FTM3 Channel 4 and 5 interrupt + DCD FTM3_Ch6_Ch7_IRQHandler ;FTM3 Channel 6 and 7 interrupt + DCD FTM3_Fault_IRQHandler ;FTM3 Fault interrupt + DCD FTM3_Ovf_Reload_IRQHandler ;FTM3 Counter overflow and Reload interrupt + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key + DCD 0xFFFFFFFF ; + DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes + DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + ;; Init the rest of the registers + LDR R1,=0 + LDR R2,=0 + LDR R3,=0 + LDR R4,=0 + LDR R5,=0 + LDR R6,=0 + LDR R7,=0 + MOV R8,R7 + MOV R9,R7 + MOV R10,R7 + MOV R11,R7 + MOV R12,R7 + +#ifdef START_FROM_FLASH + IMPORT __RAM_START, __RAM_END + ;; INIT ECC RAM + + LDR R1, =__RAM_START + LDR R2, =__RAM_END + + SUBS R2, R2, R1 + SUBS R2, #1 + BLE .LC5 + + MOVS R0, #0 + MOVS R3, #4 + .LC4: + STR R0, [R1] + ADD R1, R1, R3 + SUBS R2, #4 + BGE .LC4 + .LC5: +#endif + ;; Initialize the stack pointer + LDR R0, =sfe(CSTACK) + MOV R13,R0 + +#ifndef __NO_SYSTEM_INIT + ;; Call the CMSIS system init routine + LDR R0, =SystemInit + BLX R0 +#endif + + ;; Init .data and .bss sections + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + + BL main +JumpToSelf + B JumpToSelf + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA_Error_IRQHandler + PUBWEAK MCM_IRQHandler + PUBWEAK FTFC_IRQHandler + PUBWEAK Read_Collision_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK FTFC_Fault_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RCM_IRQHandler + PUBWEAK LPI2C0_Master_IRQHandler + PUBWEAK LPI2C0_Slave_IRQHandler + PUBWEAK LPSPI0_IRQHandler + PUBWEAK LPSPI1_IRQHandler + PUBWEAK LPSPI2_IRQHandler + PUBWEAK Reserved45_IRQHandler + PUBWEAK Reserved46_IRQHandler + PUBWEAK LPUART0_RxTx_IRQHandler + PUBWEAK Reserved48_IRQHandler + PUBWEAK LPUART1_RxTx_IRQHandler + PUBWEAK Reserved50_IRQHandler + PUBWEAK LPUART2_RxTx_IRQHandler + PUBWEAK Reserved52_IRQHandler + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved54_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK Reserved58_IRQHandler + PUBWEAK Reserved59_IRQHandler + PUBWEAK ERM_single_fault_IRQHandler + PUBWEAK ERM_double_fault_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK LPIT0_Ch0_IRQHandler + PUBWEAK LPIT0_Ch1_IRQHandler + PUBWEAK LPIT0_Ch2_IRQHandler + PUBWEAK LPIT0_Ch3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK Reserved69_IRQHandler + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK Reserved72_IRQHandler + PUBWEAK SCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK Reserved81_IRQHandler + PUBWEAK Reserved82_IRQHandler + PUBWEAK Reserved83_IRQHandler + PUBWEAK PDB1_IRQHandler + PUBWEAK FLEXIO_IRQHandler + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved87_IRQHandler + PUBWEAK Reserved88_IRQHandler + PUBWEAK Reserved89_IRQHandler + PUBWEAK Reserved90_IRQHandler + PUBWEAK Reserved91_IRQHandler + PUBWEAK Reserved92_IRQHandler + PUBWEAK Reserved93_IRQHandler + PUBWEAK CAN0_ORed_IRQHandler + PUBWEAK CAN0_Error_IRQHandler + PUBWEAK CAN0_Wake_Up_IRQHandler + PUBWEAK CAN0_ORed_0_15_MB_IRQHandler + PUBWEAK CAN0_ORed_16_31_MB_IRQHandler + PUBWEAK Reserved99_IRQHandler + PUBWEAK Reserved100_IRQHandler + PUBWEAK CAN1_ORed_IRQHandler + PUBWEAK CAN1_Error_IRQHandler + PUBWEAK Reserved103_IRQHandler + PUBWEAK CAN1_ORed_0_15_MB_IRQHandler + PUBWEAK Reserved105_IRQHandler + PUBWEAK Reserved106_IRQHandler + PUBWEAK Reserved107_IRQHandler + PUBWEAK CAN2_ORed_IRQHandler + PUBWEAK CAN2_Error_IRQHandler + PUBWEAK Reserved110_IRQHandler + PUBWEAK CAN2_ORed_0_15_MB_IRQHandler + PUBWEAK Reserved112_IRQHandler + PUBWEAK Reserved113_IRQHandler + PUBWEAK Reserved114_IRQHandler + PUBWEAK FTM0_Ch0_Ch1_IRQHandler + PUBWEAK FTM0_Ch2_Ch3_IRQHandler + PUBWEAK FTM0_Ch4_Ch5_IRQHandler + PUBWEAK FTM0_Ch6_Ch7_IRQHandler + PUBWEAK FTM0_Fault_IRQHandler + PUBWEAK FTM0_Ovf_Reload_IRQHandler + PUBWEAK FTM1_Ch0_Ch1_IRQHandler + PUBWEAK FTM1_Ch2_Ch3_IRQHandler + PUBWEAK FTM1_Ch4_Ch5_IRQHandler + PUBWEAK FTM1_Ch6_Ch7_IRQHandler + PUBWEAK FTM1_Fault_IRQHandler + PUBWEAK FTM1_Ovf_Reload_IRQHandler + PUBWEAK FTM2_Ch0_Ch1_IRQHandler + PUBWEAK FTM2_Ch2_Ch3_IRQHandler + PUBWEAK FTM2_Ch4_Ch5_IRQHandler + PUBWEAK FTM2_Ch6_Ch7_IRQHandler + PUBWEAK FTM2_Fault_IRQHandler + PUBWEAK FTM2_Ovf_Reload_IRQHandler + PUBWEAK FTM3_Ch0_Ch1_IRQHandler + PUBWEAK FTM3_Ch2_Ch3_IRQHandler + PUBWEAK FTM3_Ch4_Ch5_IRQHandler + PUBWEAK FTM3_Ch6_Ch7_IRQHandler + PUBWEAK FTM3_Fault_IRQHandler + PUBWEAK FTM3_Ovf_Reload_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA4_IRQHandler +DMA5_IRQHandler +DMA6_IRQHandler +DMA7_IRQHandler +DMA8_IRQHandler +DMA9_IRQHandler +DMA10_IRQHandler +DMA11_IRQHandler +DMA12_IRQHandler +DMA13_IRQHandler +DMA14_IRQHandler +DMA15_IRQHandler +DMA_Error_IRQHandler +MCM_IRQHandler +FTFC_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +FTFC_Fault_IRQHandler +WDOG_EWM_IRQHandler +RCM_IRQHandler +LPI2C0_Master_IRQHandler +LPI2C0_Slave_IRQHandler +LPSPI0_IRQHandler +LPSPI1_IRQHandler +LPSPI2_IRQHandler +Reserved45_IRQHandler +Reserved46_IRQHandler +LPUART0_RxTx_IRQHandler +Reserved48_IRQHandler +LPUART1_RxTx_IRQHandler +Reserved50_IRQHandler +LPUART2_RxTx_IRQHandler +Reserved52_IRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +CMP0_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +ERM_single_fault_IRQHandler +ERM_double_fault_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +LPIT0_Ch0_IRQHandler +LPIT0_Ch1_IRQHandler +LPIT0_Ch2_IRQHandler +LPIT0_Ch3_IRQHandler +PDB0_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +SCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +Reserved81_IRQHandler +Reserved82_IRQHandler +Reserved83_IRQHandler +PDB1_IRQHandler +FLEXIO_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +Reserved88_IRQHandler +Reserved89_IRQHandler +Reserved90_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +CAN0_ORed_IRQHandler +CAN0_Error_IRQHandler +CAN0_Wake_Up_IRQHandler +CAN0_ORed_0_15_MB_IRQHandler +CAN0_ORed_16_31_MB_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +CAN1_ORed_IRQHandler +CAN1_Error_IRQHandler +Reserved103_IRQHandler +CAN1_ORed_0_15_MB_IRQHandler +Reserved105_IRQHandler +Reserved106_IRQHandler +Reserved107_IRQHandler +CAN2_ORed_IRQHandler +CAN2_Error_IRQHandler +Reserved110_IRQHandler +CAN2_ORed_0_15_MB_IRQHandler +Reserved112_IRQHandler +Reserved113_IRQHandler +Reserved114_IRQHandler +FTM0_Ch0_Ch1_IRQHandler +FTM0_Ch2_Ch3_IRQHandler +FTM0_Ch4_Ch5_IRQHandler +FTM0_Ch6_Ch7_IRQHandler +FTM0_Fault_IRQHandler +FTM0_Ovf_Reload_IRQHandler +FTM1_Ch0_Ch1_IRQHandler +FTM1_Ch2_Ch3_IRQHandler +FTM1_Ch4_Ch5_IRQHandler +FTM1_Ch6_Ch7_IRQHandler +FTM1_Fault_IRQHandler +FTM1_Ovf_Reload_IRQHandler +FTM2_Ch0_Ch1_IRQHandler +FTM2_Ch2_Ch3_IRQHandler +FTM2_Ch4_Ch5_IRQHandler +FTM2_Ch6_Ch7_IRQHandler +FTM2_Fault_IRQHandler +FTM2_Ovf_Reload_IRQHandler +FTM3_Ch0_Ch1_IRQHandler +FTM3_Ch2_Ch3_IRQHandler +FTM3_Ch4_Ch5_IRQHandler +FTM3_Ch6_Ch7_IRQHandler +FTM3_Fault_IRQHandler +FTM3_Ovf_Reload_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/S32K144_64_flash.icf b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/S32K144_64_flash.icf new file mode 100644 index 00000000..4e4bc470 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/S32K144_64_flash.icf @@ -0,0 +1,121 @@ +/* +** ################################################################### +** Processor: S32K144 with 64 KB SRAM +** Compiler: IAR ANSI C/C++ Compiler for ARM +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015-2016 Freescale Semiconductor, Inc. +** Copyright 2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* If symbol __flash_vector_table__=1 is defined at link time + * the interrupt vector will not be copied to RAM. + * Warning: Using the interrupt vector from FLASH will not allow + * INT_SYS_InstallHandler because the section is Read Only. + */ +define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x00000400; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000003FF; + +/* Flash */ +define symbol m_interrupts_start = 0x00002000; +define symbol m_interrupts_end = 0x000023FF; + +define symbol m_flash_config_start = 0x00002400; +define symbol m_flash_config_end = 0x0000240F; + +define symbol m_text_start = 0x00002410; +define symbol m_text_end = 0x0007FFFF; + +/* SRAM_L */ +define symbol m_interrupts_ram_start = 0x1FFF8000; +define symbol m_interrupts_ram_end = 0x1FFF8000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +/* SRAM_U */ +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x20006FFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x00000400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x00000400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define exported symbol __RAM_START = m_interrupts_ram_start; +define exported symbol __RAM_END = m_data_2_end; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +/* Custom Section Block that can be used to place data at absolute address. */ +/* Use __attribute__((section (".customSection"))) to place data here. */ +define block customSectionBlock { section .customSection }; + +define block __CODE_ROM { section .textrw_init }; +define block __CODE_RAM { section .textrw }; + +initialize manually { section .textrw }; +initialize manually { section .bss }; +initialize manually { section .customSection }; +initialize manually { section .data }; +initialize manually { section __DLIB_PERTHREAD }; +do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in TEXT_region { block __CODE_ROM }; +place in DATA_region { block RW }; +place in DATA_region { block __CODE_RAM }; +place in DATA_region_2 { first block customSectionBlock }; +place in DATA_region_2 { block ZI }; +place in DATA_region_2 { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.out b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/bin/demoprog_s32k144.out new file mode 100644 index 0000000000000000000000000000000000000000..4d0ea038f8c8aefe5411014e92e08ee0aea1231c GIT binary patch literal 60328 zcmeHw3t$x0x&N7&oylhN+PotPun7SYAR#ZFLYp@UBoLASYEw6_g$*Rxb$5dS1Y*UC zwe`_j+iGoTudUkF7V*)?^+BzA>%Hm)AFa<4TW_^qTcc1+)tdkBJ2SJHoh%@bAiaMk znVtE4-+6rJJKuTEnKL`9>Z%1nVEQ4l97gEQe8zUa!PuKPamXdi!6fj~i0fsJTk{y3 zJ)1En++Bt9YdD|BX+C}r+KU?fWn6EV#n@B0o;%O!;G7NoYuUix;(xSe#B_YTb7W-T zJ~k9H%!b| z)@pM%4(%3gtpZ$RgX26>3isk(?=tUwhlbNC9sMjP?ckwddvgwBLraE*oP`H-K$~|U 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+1,772 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.c +* \brief Demo program bootloader interface source file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +#if (BOOT_COM_RS232_ENABLE > 0) +static void BootComRs232Init(void); +static void BootComRs232CheckActivationRequest(void); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) +static void BootComCanInit(void); +static void BootComCanCheckActivationRequest(void); +#endif + + +/************************************************************************************//** +** \brief Initializes the communication interface. +** \return none. +** +****************************************************************************************/ +void BootComInit(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232Init(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanInit(); +#endif +} /*** end of BootComInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +void BootComCheckActivationRequest(void) +{ +#if (BOOT_COM_RS232_ENABLE > 0) + BootComRs232CheckActivationRequest(); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + BootComCanCheckActivationRequest(); +#endif +} /*** end of BootComCheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Bootloader activation function. +** \return none. +** +****************************************************************************************/ +void BootActivate(void) +{ + /* Activate the bootloader by performing a software reset. */ + SystemSoftwareReset(); +} /*** end of BootActivate ***/ + + +#if (BOOT_COM_RS232_ENABLE > 0) +/**************************************************************************************** +* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout time for the reception of a CTO packet. The timer is started upon + * reception of the first packet byte. + */ +#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u) +/** \brief Set the peripheral LPUART base pointer. */ +#define LPUARTx (LPUART1) +/** \brief Set the PCC index offset for LPUART. */ +#define PCC_LPUARTx_INDEX (PCC_LPUART1_INDEX) + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data); + + +/************************************************************************************//** +** \brief Initializes the UART communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComRs232Init(void) +{ + unsigned long sourceClockFreqHz; + unsigned long div2RegValue; + unsigned short baudrateSbr0_12; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Make sure the UART peripheral clock is disabled before configuring its source + * clock. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK; + /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 + * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. + */ + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; + /* Obtain the DIV2 divider value of the SIRC_CLK. */ + div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; + /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue); + } + /* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If + * SIRC low range is enabled, it is 2 MHz. + */ + sourceClockFreqHz = 8000000U; + if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0)) + { + sourceClockFreqHz = 2000000U; + } + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * UART peripheral source clock. + */ + sourceClockFreqHz /= div2DividerLookup[div2RegValue]; + /* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an + * oversampling of 8 will be configured. Default 8,n,1 format is used. Integer + * rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals + * sourceClockFreqHz / 8 / baudrateSbr0_12. + */ + baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) & + LPUART_BAUD_SBR_MASK; + /* OSR=7: Over sampling ratio = 7+1=8. + * SBNS=0: One stop bit. + * BOTHEDGE=0: receiver samples only on rising edge. + * M10=0: Rx and Tx use 7 to 9 bit data characters. + * RESYNCDIS=0: Resync during rec'd data word supported. + * LBKDIE, RXEDGIE=0: interrupts disable. + * TDMAE, RDMAE, TDMAE=0: DMA requests disabled. + * MAEN1, MAEN2, MATCFG=0: Match disabled. + */ + LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7); + /* Clear the error/interrupt flags */ + LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK; + /* Reset all features/interrupts by default */ + LPUARTx->CTRL = 0x00000000; + /* Reset match addresses */ + LPUARTx->MATCH = 0x00000000; +#if FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Reset IrDA modem features */ + LPUARTx->MODIR = 0x00000000; +#endif +#if FEATURE_LPUART_FIFO_SIZE > 0U + /* Reset FIFO feature */ + LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK; + /* Enable the transmit and receive FIFOs. */ + LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1); + /* Set the reception water mark to 0 and the transmitter water mark to 1. */ + LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0); +#endif + /* Enable transmitter and receiver, no parity, 8 bit char: + * RE=1: Receiver enabled. + * TE=1: Transmitter enabled. + * PE,PT=0: No hw parity generation or checking. + * M7,M,R8T9,R9T8=0: 8-bit data characters. + * DOZEEN=0: LPUART enabled in Doze mode. + * ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ. + * TxDIR=0: TxD pin is input if in single-wire mode. + * TXINV=0: Transmit data not inverted. + * RWU,WAKE=0: normal operation; rcvr not in standby. + * IDLCFG=0: one idle character. + * ILT=0: Idle char bit count starts after start bit. + * SBK=0: Normal transmitter operation - no break char. + * LOOPS,RSRC=0: no loop back. + */ + LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK; +} /*** end of BootComRs232Init ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComRs232CheckActivationRequest(void) +{ + static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1]; + static unsigned char xcpCtoRxLength; + static unsigned char xcpCtoRxInProgress = 0; + static unsigned long xcpCtoRxStartTime = 0; + + /* start of cto packet received? */ + if (xcpCtoRxInProgress == 0) + { + /* store the message length when received */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1) + { + /* check that the length has a valid value. it should not be 0 */ + if ( (xcpCtoReqPacket[0] > 0) && + (xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) ) + { + /* store the start time */ + xcpCtoRxStartTime = TimerGet(); + /* indicate that a cto packet is being received */ + xcpCtoRxInProgress = 1; + /* reset packet data count */ + xcpCtoRxLength = 0; + } + } + } + else + { + /* store the next packet byte */ + if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1) + { + /* increment the packet data count */ + xcpCtoRxLength++; + + /* check to see if the entire packet was received */ + if (xcpCtoRxLength == xcpCtoReqPacket[0]) + { + /* done with cto packet reception */ + xcpCtoRxInProgress = 0; + + /* check if this was an XCP CONNECT command */ + if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } + } + else + { + /* check packet reception timeout */ + if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS)) + { + /* cancel cto packet reception due to timeout. note that this automatically + * discards the already received packet bytes, allowing the host to retry. + */ + xcpCtoRxInProgress = 0; + } + } + } +} /*** end of BootComRs232CheckActivationRequest ***/ + + +/************************************************************************************//** +** \brief Receives a communication interface byte if one is present. +** \param data Pointer to byte where the data is to be stored. +** \return 1 if a byte was received, 0 otherwise. +** +****************************************************************************************/ +static unsigned char Rs232ReceiveByte(unsigned char *data) +{ + unsigned char result = 0; + + /* Check if a new byte was received by means of the RDRF-bit. */ + if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U) + { + /* Retrieve and store the newly received byte. */ + *data = LPUARTx->DATA; + /* Update the result. */ + result = 1; + } + + /* Give the result back to the caller. */ + return result; +} /*** end of Rs232ReceiveByte ***/ +#endif /* BOOT_COM_RS232_ENABLE > 0 */ + + +#if (BOOT_COM_CAN_ENABLE > 0) +/**************************************************************************************** +* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E +****************************************************************************************/ + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */ +#define CAN_INIT_TIMEOUT_MS (250U) + +/** \brief Set the peripheral CAN0 base pointer. */ +#define CANx (CAN0) +/** \brief Set the PCC index offset for CAN0. */ +#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX) +/** \brief Set the number of message boxes supported by CAN0. */ +#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM) + +/** \brief The mailbox used for receiving the XCP command message. */ +#define CAN_RX_MSGBOX_NUM (9U) + + +/**************************************************************************************** +* Type definitions +****************************************************************************************/ +/** \brief Structure type for grouping CAN bus timing related information. */ +typedef struct t_can_bus_timing +{ + unsigned char timeQuanta; /**< Total number of time quanta */ + unsigned char propSeg; /**< CAN propagation segment */ + unsigned char phaseSeg1; /**< CAN phase segment 1 */ + unsigned char phaseSeg2; /**< CAN phase segment 2 */ +} tCanBusTiming; + + +/**************************************************************************************** +* Local constant declarations +****************************************************************************************/ +/** \brief CAN bit timing table for dynamically calculating the bittiming settings. + * \details According to the CAN protocol 1 bit-time can be made up of between 8..25 + * time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC + * always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2) + * * 100%. This array contains possible and valid time quanta configurations + * with a sample point between 68..78%. A visual representation of the TQ in + * a bit is: + * | SYNCSEG | TIME1SEG | TIME2SEG | + * Or with an alternative representation: + * | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG | + * With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG. + * + */ +static const tCanBusTiming canTiming[] = +{ + /* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */ + /* ---------------------------------------------------- */ + { 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */ + { 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */ + { 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */ + { 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */ + { 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */ + { 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */ + { 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */ + { 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */ + { 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */ + { 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */ + { 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */ + { 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */ + { 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */ + { 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */ + { 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */ + { 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */ + { 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */ + { 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */ +}; + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Dummy variable to store the CAN controller's free running timer value in. + * This is needed at the end of a CAN message reception to unlock the mailbox + * again. If this variable is declared locally within the function, it generates + * an unwanted compiler warning about assigning a value and not using it. + * For this reason this dummy variabled is declare here as a module global. + */ +static volatile unsigned long dummyTimerVal; + + +/************************************************************************************//** +** \brief Search algorithm to match the desired baudrate to a possible bus +** timing configuration. +** \param baud The desired baudrate in kbps. Valid values are 10..1000. +** \param prescaler Pointer to where the value for the prescaler will be stored. +** \param busTimingCfg Pointer to where the bus timing values will be stored. +** \return 1 if the CAN bustiming register values were found, 0 otherwise. +** +****************************************************************************************/ +static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler, + tCanBusTiming * busTimingCfg) +{ + unsigned char cnt; + unsigned long canClockFreqkHz; + unsigned long div2RegValue; + unsigned char const div2DividerLookup[] = + { + 0U, /* 0b000. Output disabled. */ + 1U, /* 0b001. Divide by 1. */ + 2U, /* 0b010. Divide by 2. */ + 4U, /* 0b011. Divide by 4. */ + 8U, /* 0b100. Divide by 8. */ + 16U, /* 0b101. Divide by 16. */ + 32U, /* 0b110. Divide by 32. */ + 64U, /* 0b111. Divide by 64. */ + }; + + /* Obtain the DIV2 divider value of the SOSC_CLK. */ + div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT; + /* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is + * currently disabled. + */ + if (div2RegValue == 0U) + { + /* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is + * actually enabled. + */ + div2RegValue = 1U; + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue); + } + /* Determine the SOSC clock frequency. */ + canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ; + /* Now process the configured DIV2 divider factor to get the actual frequency of the + * CAN peripheral source clock. + */ + canClockFreqkHz /= div2DividerLookup[div2RegValue]; + + /* Loop through all possible time quanta configurations to find a match. */ + for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) + { + if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U) + { + /* Compute the prescaler that goes with this TQ configuration. */ + *prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta); + + /* Make sure the prescaler is valid. */ + if ((*prescaler > 0U) && (*prescaler <= 256U)) + { + /* Store the bustiming configuration. */ + *busTimingCfg = canTiming[cnt]; + /* Found a good bus timing configuration. */ + return 1U; + } + } + } + /* Could not find a good bus timing configuration. */ + return 0U; +} /*** end of CanGetSpeedConfig ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in freeze mode. Note that the CAN controller +** can only be placed in freeze mode, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeEnter(void) +{ + unsigned long timeout; + + /* Request to enter freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U); + /* Set timeout time for entering freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeEnter ***/ + + +/************************************************************************************//** +** \brief Leaves the CAN controller's freeze mode. Note that this operation can +** only be done, if it is actually enabled. +** \return none. +** +****************************************************************************************/ +static void CanFreezeModeExit(void) +{ + unsigned long timeout; + + /* Request to leave freeze mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U); + CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U); + /* Set timeout time for leaving freeze mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for non freeze mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of CanFreezeModeExit ***/ + + +/************************************************************************************//** +** \brief Places the CAN controller in disabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeEnter(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently enabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U) + { + /* Request disabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U); + /* Set timeout time for entering disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeEnter ***/ + +/************************************************************************************//** +** \brief Places the CAN controller in enabled mode. +** \return none. +** +****************************************************************************************/ +static void CanDisabledModeExit(void) +{ + unsigned long timeout; + + /* Only continue if the CAN controller is currently disabled. */ + if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U) + { + /* Request enabled mode. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U); + /* Set timeout time for leaving disabled mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for disabled mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } + } +} /*** end of CanDisabledModeExit ***/ + + +/************************************************************************************//** +** \brief Initializes the CAN communication interface. +** \return none. +** +****************************************************************************************/ +static void BootComCanInit(void) +{ + unsigned short prescaler = 0; + tCanBusTiming timingCfg = { 0 }; + unsigned char rjw; + unsigned short idx; + unsigned long timeout; + unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID; + + /* Enable the CAN peripheral clock. */ + PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK; + + /* The source clock needs to be configured first. For this the CAN controller must be + * in disabled mode, but that can only be entered after first entering freeze mode, + * which in turn can only be in enabled mode. So first enable the module, then goto + * freeze mode and finally enter disabled mode. + */ + CanDisabledModeExit(); + CanFreezeModeEnter(); + CanDisabledModeEnter(); + /* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator + * is available, which is typically the case to meet the clock tolerance requirements + * of the CAN 2.0B secification. + */ + CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK; + /* Leave disabled mode. */ + CanDisabledModeExit(); + /* Make sure freeze mode is active to be able to initialize the CAN controller. */ + CanFreezeModeEnter(); + + /* Obtain bittiming configuration information. */ + (void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg); + + /* Reset the current bittiming configuration. */ + CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK | + CAN_CTRL1_SMP_MASK); + /* Configure the baudrate prescaler. */ + CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U); + /* Configure the propagation segment. */ + CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U); + /* Configure the phase segments. */ + CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U); + CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U); + /* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger + * than pseg1. Configure the longest possible value for RJW. + */ + rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4; + CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U); + /* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to + * determine the value of the received bit, instead of the default one. + */ + CANx->CTRL1 |= CAN_CTRL1_SMP(1U); + + /* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */ + for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++) + { + CANx->RAMn[idx] = 0U; + } + /* Clear the reception mask register for each message box. */ + for (idx = 0; idx < CANx_MAX_MB_NUM; idx++) + { + CANx->RXIMR[idx] = 0U; + } + /* Configure the maximum number of message boxes. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U); + /* Disable the self reception feature. */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U); + + /* Enable individual reception masking. This disables the legacy support for the + * global reception mask and the mailbox 14/15 individual reception mask. + */ + CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U); + /* Disable the reception FIFO. This driver only needs to receive one CAN message + * identifier. It is sufficient to use just one dedicated mailbox for this. + */ + CANx->MCR &= ~CAN_MCR_RFEN_MASK; + /* Configure the mask of the invididual message reception mailbox to check all ID bits + * and also the IDE bit. + */ + CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU; + /* Configure the reception mailbox to receive just the CAN message configured with + * BOOT_COM_CAN_RX_MSG_ID. + * EDL, BRS, ESI=0: CANFD not used. + * CODE=0b0100: mailbox set to active and empty. + * IDE=0: 11-bit CAN identifier. + * SRR, RTR, TIME STAMP=0: not applicable. + */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000; + /* Store the message identifier to receive in the mailbox RAM. */ + if ((rxMsgId & 0x80000000U) != 0U) + { + /* It is a 29-bit extended CAN identifier. */ + rxMsgId &= ~0x80000000U; + /* Set the IDE bit to configure the message for a 29-bit identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK; + /* Store the 29-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId); + } + else + { + /* Store the 11-bit CAN identifier. */ + CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U); + } + + /* Disable all message box interrupts. */ + CANx->IMASK1 = 0U; + /* Clear all mesasge box interrupt flags. */ + CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK; + /* Clear all error interrupt flags */ + CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK | + CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK | + CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK; + + /* Switch to normal user mode. */ + CANx->MCR &= ~CAN_MCR_SUPV_MASK; + CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK); + /* Exit freeze mode. */ + CanFreezeModeExit(); + /* Set timeout time for entering normal user mode. */ + timeout = TimerGet() + CAN_INIT_TIMEOUT_MS; + /* Wait for normal user mode acknowledgement. */ + while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U) + { + /* Break loop upon timeout. This would indicate a hardware failure. */ + if (TimerGet() > timeout) + { + break; + } + } +} /*** end of BootComCanInit ***/ + + +/************************************************************************************//** +** \brief Receives the CONNECT request from the host, which indicates that the +** bootloader should be activated and, if so, activates it. +** \return none. +** +****************************************************************************************/ +static void BootComCanCheckActivationRequest(void) +{ + unsigned char * pMsgBoxData; + unsigned char byteIdx; + unsigned char rxMsgData[8]; + unsigned char rxMsgLen; + + /* Check if a message was received in the individual mailbox configured to receive + * the BOOT_COM_CAN_RX_MSG_ID message. + */ + if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U) + { + /* Note that there is no need to verify the identifier of the CAN message because the + * mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start + * by reading out the DLC of the newly received CAN message. + */ + rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT; + /* Read the data bytes of the CAN message from the mailbox RAM. */ + pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]); + for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++) + { + rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))]; + } + /* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */ + CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM); + /* Read the free running timer to unlock the mailbox. */ + dummyTimerVal = CANx->TIMER; + + /* check if this was an XCP CONNECT command */ + if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2)) + { + /* connection request received so start the bootloader */ + BootActivate(); + } + } +} /*** end of BootComCanCheckActivationRequest ***/ +#endif /* BOOT_COM_CAN_ENABLE > 0 */ + + +/*********************************** end of boot.c *************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h new file mode 100644 index 00000000..76b266b2 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h @@ -0,0 +1,40 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/boot.h +* \brief Demo program bootloader interface header file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef BOOT_H +#define BOOT_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void BootComInit(void); +void BootComCheckActivationRequest(void); +void BootActivate(void); + + +#endif /* BOOT_H */ +/*********************************** end of boot.h *************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h new file mode 100644 index 00000000..d5a99970 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h @@ -0,0 +1,42 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/header.h +* \brief Generic header file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef HEADER_H +#define HEADER_H + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "../Boot/blt_conf.h" /* bootloader configuration */ +#include "boot.h" /* bootloader interface driver */ +#include "led.h" /* LED driver */ +#include "timer.h" /* Timer driver */ +#include "device_registers.h" /* Device registers */ +#include "system_S32K144.h" /* Device sconfiguration */ + +#endif /* HEADER_H */ +/*********************************** end of header.h ***********************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.dep b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.dep new file mode 100644 index 00000000..940be701 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.dep @@ -0,0 +1,264 @@ + + + 4 + 3486298355 + + Debug + + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\..\obj\main.o + $PROJ_DIR$\..\obj\led.__cstat.et + $TOOLKIT_DIR$\lib\rt7M_tl.a + $PROJ_DIR$\..\bin\demoprog_s32k144.srec + $PROJ_DIR$\..\lib\S32K144_features.h + $PROJ_DIR$\..\lib\startup.h + $PROJ_DIR$\..\boot.c + $PROJ_DIR$\..\boot.h + $PROJ_DIR$\..\bin\openblt_s32k144.out + $PROJ_DIR$\..\led.h + $PROJ_DIR$\..\obj\timer.o + $PROJ_DIR$\..\lib\startup.c + $PROJ_DIR$\..\lib\system_S32K144.h + $PROJ_DIR$\..\obj\timer.xcl + $PROJ_DIR$\..\lib\system_S32K144.c + $PROJ_DIR$\..\obj\startup.xcl + $PROJ_DIR$\..\startup_S32K144.s + $PROJ_DIR$\..\obj\system_S32K144.xcl + $PROJ_DIR$\..\..\Boot\blt_conf.h + $PROJ_DIR$\..\led.c + $PROJ_DIR$\..\timer.h + $PROJ_DIR$\..\obj\openblt_s32k144.map + $PROJ_DIR$\..\obj\system_S32K144.__cstat.et + $PROJ_DIR$\..\obj\system_S32K144.o + $TOOLKIT_DIR$\lib\dl7M_tln.a + $PROJ_DIR$\..\header.h + $TOOLKIT_DIR$\inc\c\stdint.h + $TOOLKIT_DIR$\lib\m7M_tls.a + $PROJ_DIR$\..\main.c + $PROJ_DIR$\..\timer.c + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\lib\devassert.h + $PROJ_DIR$\..\lib\s32_core_cm4.h + $PROJ_DIR$\..\lib\S32K144.h + $PROJ_DIR$\..\lib\device_registers.h + $PROJ_DIR$\..\obj\main.xcl + $PROJ_DIR$\..\obj\timer.__cstat.et + $TOOLKIT_DIR$\inc\c\stdbool.h + $PROJ_DIR$\..\obj\startup.o + $PROJ_DIR$\..\obj\s32k144.pbd + $PROJ_DIR$\..\obj\boot.__cstat.et + $PROJ_DIR$\..\obj\led.o + $PROJ_DIR$\..\obj\boot.o + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\obj\startup_S32K144.o + $PROJ_DIR$\..\obj\main.__cstat.et + $PROJ_DIR$\..\obj\led.xcl + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\..\obj\boot.xcl + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\..\obj\startup.__cstat.et + $PROJ_DIR$\..\S32K144_64_flash.icf + $PROJ_DIR$\..\obj\demoprog_s32k144.map + $PROJ_DIR$\..\bin\demoprog_s32k144.out + + + [ROOT_NODE] + + + ILINK + 55 54 + + + + + $PROJ_DIR$\..\boot.c + + + ICCARM + 43 + + + BICOMP + 50 + + + __cstat + 41 + + + + + ICCARM + 26 19 8 10 21 35 33 34 27 51 44 45 0 49 5 32 38 13 + + + + + $PROJ_DIR$\..\bin\openblt_s32k144.out + + + OBJCOPY + 4 + + + + + ILINK + 53 43 42 1 39 46 24 11 31 3 28 25 + + + + + $PROJ_DIR$\..\lib\startup.c + + + ICCARM + 39 + + + BICOMP + 16 + + + __cstat + 52 + + + + + ICCARM + 6 27 51 44 45 0 49 35 33 34 5 32 38 + + + + + $PROJ_DIR$\..\lib\system_S32K144.c + + + ICCARM + 24 + + + BICOMP + 18 + + + __cstat + 23 + + + + + ICCARM + 35 33 34 27 51 44 45 0 49 5 32 38 13 + + + + + $PROJ_DIR$\..\startup_S32K144.s + + + AARM + 46 + + + + + $PROJ_DIR$\..\led.c + + + ICCARM + 42 + + + BICOMP + 48 + + + __cstat + 2 + + + + + ICCARM + 26 19 8 10 21 35 33 34 27 51 44 45 0 49 5 32 38 13 + + + + + $PROJ_DIR$\..\main.c + + + ICCARM + 1 + + + BICOMP + 36 + + + __cstat + 47 + + + + + ICCARM + 26 19 8 10 21 35 33 34 27 51 44 45 0 49 5 32 38 13 + + + + + $PROJ_DIR$\..\timer.c + + + ICCARM + 11 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$PROJ_DIR$\..\lib\startup.h + + + $PROJ_DIR$\..\lib\system_S32K144.c + + + $PROJ_DIR$\..\lib\system_S32K144.h + + + + $PROJ_DIR$\..\boot.c + + + $PROJ_DIR$\..\boot.h + + + $PROJ_DIR$\..\header.h + + + $PROJ_DIR$\..\led.c + + + $PROJ_DIR$\..\led.h + + + $PROJ_DIR$\..\main.c + + + $PROJ_DIR$\..\startup_S32K144.s + + + $PROJ_DIR$\..\timer.c + + + $PROJ_DIR$\..\timer.h + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewt b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewt new file mode 100644 index 00000000..9203ceee --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.ewt @@ -0,0 +1,2432 @@ + + + 3 + + Debug + + ARM + + 1 + + C-STAT + 261 + + 261 + + 0 + + 1 + 600 + 1 + 2 + 0 + 1 + 100 + + + 1.5.5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.eww b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.eww new file mode 100644 index 00000000..fcec0790 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/ide/s32k144.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\s32k144.ewp + + + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c new file mode 100644 index 00000000..efd898ef --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c @@ -0,0 +1,96 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.c +* \brief LED driver source file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Macro definitions +****************************************************************************************/ +/** \brief Toggle interval time in milliseconds. */ +#define LED_TOGGLE_MS (500U) + + +/************************************************************************************//** +** \brief Initializes the LED. +** \return none. +** +****************************************************************************************/ +void LedInit(void) +{ + /* LED GPIO pin configuration. PD0 = GPIO, MUX = ALT1. */ + PORTD->PCR[0] |= PORT_PCR_MUX(1); + /* configure Port D pin 0 GPIO as digital output */ + PTD->PDDR |= GPIO_PDDR_PDD(0x00000001); + /* turn the LED off on Port D pin 0 */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); +} /*** end of LedInit ***/ + + +/************************************************************************************//** +** \brief Toggles the LED at a fixed time interval. +** \return none. +** +****************************************************************************************/ +void LedToggle(void) +{ + static unsigned char led_toggle_state = 0; + static unsigned long timer_counter_last = 0; + unsigned long timer_counter_now; + + /* Check if toggle interval time passed. */ + timer_counter_now = TimerGet(); + if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS) + { + /* Not yet time to toggle. */ + return; + } + + /* Determine toggle action. */ + if (led_toggle_state == 0) + { + led_toggle_state = 1; + /* Turn the LED on. */ + PTD->PCOR |= GPIO_PCOR_PTCO(0x00000001); + } + else + { + led_toggle_state = 0; + /* Turn the LED off. */ + PTD->PSOR |= GPIO_PSOR_PTSO(0x00000001); + } + + /* Store toggle time to determine next toggle interval. */ + timer_counter_last = timer_counter_now; +} /*** end of LedToggle ***/ + + +/*********************************** end of led.c **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h new file mode 100644 index 00000000..89aa9a34 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h @@ -0,0 +1,39 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/led.h +* \brief LED driver header file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef LED_H +#define LED_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void LedInit(void); +void LedToggle(void); + + +#endif /* LED_H */ +/*********************************** end of led.h **************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144.h new file mode 100644 index 00000000..ae04b8bb --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/S32K144.h @@ -0,0 +1,11937 @@ +/* +** ################################################################### +** Processor: S32K144 +** Reference manual: S32K1XXRM Rev. 9, 09/2018 +** Version: rev. 4.2, 2019-02-19 +** Build: b190219 +** +** Abstract: +** Peripheral Access Layer for S32K144 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2015-04-09) - Iulian Talpiga +** Initial version. +** - rev. 1.1 (2015-05-19) - Bogdan Nitu +** Updated interrupts table +** Removed SIM_CHIPCTL_DAC2CMP +** Compacted PORT_PCR registers +** Compacted PCC registers +** - rev. 1.2 (2015-06-02) - Bogdan Nitu +** Added 'U' suffix to all integer constants +** Use "" instead of <> for Platform type inclusion +** CNT register from WDOG module is RW +** - rev. 1.3 (2015-08-05) - Iulian Talpiga +** Synchronized with latest RDP +** Removed OSC32 module +** Removed reserved registers +** Incorporated bit band acces macros +** Switched to standard C99 data types +** Added 'u' to constants +** Added size defines for register arrays +** Define peripheral instance count +** - rev. 1.4 (2015-08-10) - Iulian Talpiga +** Compacted TRGMUX registers +** Defined array index offsets for PCC and TRGMUX +** Added FPU registers +** Group FTM channel registers +** Added interrupt information to peripherals +** Renamed CAN interrupts according to the reference manual +** Added author information to revisions +** - rev. 1.5 (2015-09-16) - Iulian Talpiga +** Renamed NVIC and SCB to avoid conflict +** Compacted CAN Wake-up Message buffers +** Added CAN embedded RAM +** Updated interrupts: LPIT, FTFE, LPUART,ACMP +** Corrected ADC_SC1_ADCH_WIDTH +** Compacted PDB registers +** Corrected CAN, FTM, and PDB count defines +** Guarding register acces macro against redefintion +** - rev. 1.6 (2015-09-29) - Iulian Talpiga +** Added WATER and FIFO registers to LPUART. +** - rev. 1.7 (2015-10-21) - Iulian Talpiga +** Updated ADC, AIPS, CMP, LMEM, LPTMR, PMC, PORT, RCM, RTC, SCG, SIM +** Compacted MPU and LPIT +** Added FSL_SysTick +** Updated doxygen documentation grouping +** Updated interrupts: RCM +** - rev. 1.8 (2016-01-06) - Iulian Talpiga +** Updated DMA, compacted TCD registers +** Updated SCG, removed SC2P - SC16P +** Added 8 and 16 bit access to DATA register, CRC module +** - rev. 1.9 (2016-02-15) - Iulian Talpiga +** Updated CRC, renamed DATA union +** Updated PMC, added CLKBIASDIS bitfield +** Added FSL_NVIC registers to SVD +** - rev. 2.0 (2016-04-07) - Iulian Talpiga +** Updated support for Rev2.0 silicon (0N47T) +** Updated ADC, AIPS, DMA, FlexIO, FTM, GPIO, LPI2C, LPIT, LPSPI, MCM, MPU, MSCM, PMC, RTC, RCM, PCC, RTC, SCG, SIM, TRGMUX and WDOG module +** Updated interrupts +** Added EIM and ERM modules +** Added EIM and ERM modules +** - rev. 2.1 (2016-06-10) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: CAN, EIM, LPI2C, MPU, PCC, PMC, RTC, SIM and TRGMUX +** - rev. 2.2 (2016-08-02) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: ADC, CAN, CRC, FTFC, LMEM, LPI2C, MCM, MSCM, PCC, RTC, SIM +** Added CSE_PRAM +** - rev. 2.3 (2016-09-09) - Iulian Talpiga +** Updated to latest RM +** Minor changes to: PCC, FSL_NVIC and FTM +** - rev. 2.4 (2016-09-28) - Iulian Talpiga +** Fix RAMn array size in FlexCAN +** Fix FCSESTAT bit order +** Added CP0CFG0, CP0CFG1,CP0CFG2 and CP0CFG3 in MSCM +** Fixed STIR register in FSL_NVIC +** Fixed SHPR3 and ACTLR registers in FSL_SCB +** - rev. 2.5 (2016-11-25) - Iulian Talpiga +** Fix FRAC bit-field in PCC module +** Removed BITBAND_ACCESS macros +** Added MISRA declarations +** Updated copyright +** Changed prefix of NVIC, SCB and SysTick to S32_ +** - rev. 2.6 (2017-01-09) - Iulian Talpiga +** Fix interrupts for CAN, LPUART, FTFC +** - rev. 2.7 (2017-02-22) - Iulian Talpiga +** Update header as per rev S32K14XRM Rev. 2, 02/2017 +** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM +** - rev. 2.8 (2017-03-27) - Iulian Talpiga +** Synchronized PCC_FlexIO on S32K Family +** - rev. 3.0 (2017-08-04) - Mihai Volmer +** Update header as per rev S32K1XXRM Rev. 4, 06/2017 +** Updated modules CAN, MCM and PORTn +** - rev. 3.1 (2017-09-25) - Andrei Bolojan +** Update NVIC Size of Registers Arrays +** - rev. 4.0 (2018-02-28) - Mihai Volmer +** Updated header as per rev S32K1XXRM Rev. 6, 12/2017 +** Updated modules ERM, I2C, MSCM and SIM +** - rev. 4.1 (2018-07-19) - Dan Nastasa +** Updated the header based on S32K1XXRM Rev. 8, 06/2018. +** - rev. 4.2 (2019-02-19) - Ionut Pavel +** Updated the header based on S32K1XXRM Rev. 9, 09/2018. +** +** ################################################################### +*/ + +/*! + * @file S32K144.h + * @version 4.2 + * @date 2019-02-19 + * @brief Peripheral Access Layer for S32K144 + * + * This file contains register definitions and macros for easy access to their + * bit fields. + * + * This file assumes LITTLE endian system. + */ + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced +* The SoC header defines typedef for all modules. +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced +* The SoC header defines macros for all modules and registers. +* +* @section [global] +* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro +* These are generated macros used for accessing the bit-fields from registers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.1, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.2, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.4, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 5.5, identifier clash +* The supported compilers use more than 31 significant characters for identifiers. +* +* @section [global] +* Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler +* This type qualifier is needed to ensure correct I/O access and addressing. +*/ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(S32K144_H_) /* Check if memory map has not been already included */ +#define S32K144_H_ +#define MCU_S32K144 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error S32K144 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0400u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002u + +/* ---------------------------------------------------------------------------- + -- Generic macros + ---------------------------------------------------------------------------- */ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +* IO Type Qualifiers are used +* \li to specify the access to peripheral variables. +* \li for automatic generation of peripheral register debug information. +*/ +#ifndef __IO +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +/** +* @brief 32 bits memory read macro. +*/ +#if !defined(REG_READ32) + #define REG_READ32(address) (*(volatile uint32_t*)(address)) +#endif + +/** +* @brief 32 bits memory write macro. +*/ +#if !defined(REG_WRITE32) + #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) +#endif + +/** +* @brief 32 bits bits setting macro. +*/ +#if !defined(REG_BIT_SET32) + #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) +#endif + +/** +* @brief 32 bits bits clearing macro. +*/ +#if !defined(REG_BIT_CLEAR32) + #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) +#endif + +/** +* @brief 32 bit clear bits and set with new value +* @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 +*/ +#if !defined(REG_RMW32) + #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) +#endif + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers_S32K144 Interrupt vector numbers for S32K144 + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 139u /**< Number of interrupts in the Vector table */ + +/** + * @brief Defines the Interrupt Numbers definitions + * + * This enumeration is used to configure the interrupts. + * + * Implements : IRQn_Type_Class + */ +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0u, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1u, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2u, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3u, /**< DMA channel 3 transfer complete */ + DMA4_IRQn = 4u, /**< DMA channel 4 transfer complete */ + DMA5_IRQn = 5u, /**< DMA channel 5 transfer complete */ + DMA6_IRQn = 6u, /**< DMA channel 6 transfer complete */ + DMA7_IRQn = 7u, /**< DMA channel 7 transfer complete */ + DMA8_IRQn = 8u, /**< DMA channel 8 transfer complete */ + DMA9_IRQn = 9u, /**< DMA channel 9 transfer complete */ + DMA10_IRQn = 10u, /**< DMA channel 10 transfer complete */ + DMA11_IRQn = 11u, /**< DMA channel 11 transfer complete */ + DMA12_IRQn = 12u, /**< DMA channel 12 transfer complete */ + DMA13_IRQn = 13u, /**< DMA channel 13 transfer complete */ + DMA14_IRQn = 14u, /**< DMA channel 14 transfer complete */ + DMA15_IRQn = 15u, /**< DMA channel 15 transfer complete */ + DMA_Error_IRQn = 16u, /**< DMA error interrupt channels 0-15 */ + MCM_IRQn = 17u, /**< FPU sources */ + FTFC_IRQn = 18u, /**< FTFC Command complete */ + Read_Collision_IRQn = 19u, /**< FTFC Read collision */ + LVD_LVW_IRQn = 20u, /**< PMC Low voltage detect interrupt */ + FTFC_Fault_IRQn = 21u, /**< FTFC Double bit fault detect */ + WDOG_EWM_IRQn = 22u, /**< Single interrupt vector for WDOG and EWM */ + RCM_IRQn = 23u, /**< RCM Asynchronous Interrupt */ + LPI2C0_Master_IRQn = 24u, /**< LPI2C0 Master Interrupt */ + LPI2C0_Slave_IRQn = 25u, /**< LPI2C0 Slave Interrupt */ + LPSPI0_IRQn = 26u, /**< LPSPI0 Interrupt */ + LPSPI1_IRQn = 27u, /**< LPSPI1 Interrupt */ + LPSPI2_IRQn = 28u, /**< LPSPI2 Interrupt */ + LPUART0_RxTx_IRQn = 31u, /**< LPUART0 Transmit / Receive Interrupt */ + LPUART1_RxTx_IRQn = 33u, /**< LPUART1 Transmit / Receive Interrupt */ + LPUART2_RxTx_IRQn = 35u, /**< LPUART2 Transmit / Receive Interrupt */ + ADC0_IRQn = 39u, /**< ADC0 interrupt request. */ + ADC1_IRQn = 40u, /**< ADC1 interrupt request. */ + CMP0_IRQn = 41u, /**< CMP0 interrupt request */ + ERM_single_fault_IRQn = 44u, /**< ERM single bit error correction */ + ERM_double_fault_IRQn = 45u, /**< ERM double bit error non-correctable */ + RTC_IRQn = 46u, /**< RTC alarm interrupt */ + RTC_Seconds_IRQn = 47u, /**< RTC seconds interrupt */ + LPIT0_Ch0_IRQn = 48u, /**< LPIT0 channel 0 overflow interrupt */ + LPIT0_Ch1_IRQn = 49u, /**< LPIT0 channel 1 overflow interrupt */ + LPIT0_Ch2_IRQn = 50u, /**< LPIT0 channel 2 overflow interrupt */ + LPIT0_Ch3_IRQn = 51u, /**< LPIT0 channel 3 overflow interrupt */ + PDB0_IRQn = 52u, /**< PDB0 interrupt */ + SCG_IRQn = 57u, /**< SCG bus interrupt request */ + LPTMR0_IRQn = 58u, /**< LPTIMER interrupt request */ + PORTA_IRQn = 59u, /**< Port A pin detect interrupt */ + PORTB_IRQn = 60u, /**< Port B pin detect interrupt */ + PORTC_IRQn = 61u, /**< Port C pin detect interrupt */ + PORTD_IRQn = 62u, /**< Port D pin detect interrupt */ + PORTE_IRQn = 63u, /**< Port E pin detect interrupt */ + SWI_IRQn = 64u, /**< Software interrupt */ + PDB1_IRQn = 68u, /**< PDB1 interrupt */ + FLEXIO_IRQn = 69u, /**< FlexIO Interrupt */ + CAN0_ORed_IRQn = 78u, /**< CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN0_Error_IRQn = 79u, /**< CAN0 Interrupt indicating that errors were detected on the CAN bus */ + CAN0_Wake_Up_IRQn = 80u, /**< CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ + CAN0_ORed_0_15_MB_IRQn = 81u, /**< CAN0 OR'ed Message buffer (0-15) */ + CAN0_ORed_16_31_MB_IRQn = 82u, /**< CAN0 OR'ed Message buffer (16-31) */ + CAN1_ORed_IRQn = 85u, /**< CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN1_Error_IRQn = 86u, /**< CAN1 Interrupt indicating that errors were detected on the CAN bus */ + CAN1_ORed_0_15_MB_IRQn = 88u, /**< CAN1 OR'ed Interrupt for Message buffer (0-15) */ + CAN2_ORed_IRQn = 92u, /**< CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] */ + CAN2_Error_IRQn = 93u, /**< CAN2 Interrupt indicating that errors were detected on the CAN bus */ + CAN2_ORed_0_15_MB_IRQn = 95u, /**< CAN2 OR'ed Message buffer (0-15) */ + FTM0_Ch0_Ch1_IRQn = 99u, /**< FTM0 Channel 0 and 1 interrupt */ + FTM0_Ch2_Ch3_IRQn = 100u, /**< FTM0 Channel 2 and 3 interrupt */ + FTM0_Ch4_Ch5_IRQn = 101u, /**< FTM0 Channel 4 and 5 interrupt */ + FTM0_Ch6_Ch7_IRQn = 102u, /**< FTM0 Channel 6 and 7 interrupt */ + FTM0_Fault_IRQn = 103u, /**< FTM0 Fault interrupt */ + FTM0_Ovf_Reload_IRQn = 104u, /**< FTM0 Counter overflow and Reload interrupt */ + FTM1_Ch0_Ch1_IRQn = 105u, /**< FTM1 Channel 0 and 1 interrupt */ + FTM1_Ch2_Ch3_IRQn = 106u, /**< FTM1 Channel 2 and 3 interrupt */ + FTM1_Ch4_Ch5_IRQn = 107u, /**< FTM1 Channel 4 and 5 interrupt */ + FTM1_Ch6_Ch7_IRQn = 108u, /**< FTM1 Channel 6 and 7 interrupt */ + FTM1_Fault_IRQn = 109u, /**< FTM1 Fault interrupt */ + FTM1_Ovf_Reload_IRQn = 110u, /**< FTM1 Counter overflow and Reload interrupt */ + FTM2_Ch0_Ch1_IRQn = 111u, /**< FTM2 Channel 0 and 1 interrupt */ + FTM2_Ch2_Ch3_IRQn = 112u, /**< FTM2 Channel 2 and 3 interrupt */ + FTM2_Ch4_Ch5_IRQn = 113u, /**< FTM2 Channel 4 and 5 interrupt */ + FTM2_Ch6_Ch7_IRQn = 114u, /**< FTM2 Channel 6 and 7 interrupt */ + FTM2_Fault_IRQn = 115u, /**< FTM2 Fault interrupt */ + FTM2_Ovf_Reload_IRQn = 116u, /**< FTM2 Counter overflow and Reload interrupt */ + FTM3_Ch0_Ch1_IRQn = 117u, /**< FTM3 Channel 0 and 1 interrupt */ + FTM3_Ch2_Ch3_IRQn = 118u, /**< FTM3 Channel 2 and 3 interrupt */ + FTM3_Ch4_Ch5_IRQn = 119u, /**< FTM3 Channel 4 and 5 interrupt */ + FTM3_Ch6_Ch7_IRQn = 120u, /**< FTM3 Channel 6 and 7 interrupt */ + FTM3_Fault_IRQn = 121u, /**< FTM3 Fault interrupt */ + FTM3_Ovf_Reload_IRQn = 122u /**< FTM3 Counter overflow and Reload interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers_S32K144 */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer for S32K144 + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer_S32K144 Device Peripheral Access Layer for S32K144 + * @{ + */ + +/* @brief This module covers memory mapped registers available on SoC */ + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + + +/** ADC - Size of Registers Arrays */ +#define ADC_SC1_COUNT 16u +#define ADC_R_COUNT 16u +#define ADC_CV_COUNT 2u + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[ADC_SC1_COUNT]; /**< ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x40 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x44 */ + __I uint32_t R[ADC_R_COUNT]; /**< ADC Data Result Registers, array offset: 0x48, array step: 0x4 */ + __IO uint32_t CV[ADC_CV_COUNT]; /**< Compare Value Registers, array offset: 0x88, array step: 0x4 */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x90 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x94 */ + __IO uint32_t BASE_OFS; /**< BASE Offset Register, offset: 0x98 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x9C */ + __IO uint32_t USR_OFS; /**< USER Offset Correction Register, offset: 0xA0 */ + __IO uint32_t XOFS; /**< ADC X Offset Correction Register, offset: 0xA4 */ + __IO uint32_t YOFS; /**< ADC Y Offset Correction Register, offset: 0xA8 */ + __IO uint32_t G; /**< ADC Gain Register, offset: 0xAC */ + __IO uint32_t UG; /**< ADC User Gain Register, offset: 0xB0 */ + __IO uint32_t CLPS; /**< ADC General Calibration Value Register S, offset: 0xB4 */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register 3, offset: 0xB8 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register 2, offset: 0xBC */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register 1, offset: 0xC0 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register 0, offset: 0xC4 */ + __IO uint32_t CLPX; /**< ADC Plus-Side General Calibration Value Register X, offset: 0xC8 */ + __IO uint32_t CLP9; /**< ADC Plus-Side General Calibration Value Register 9, offset: 0xCC */ + __IO uint32_t CLPS_OFS; /**< ADC General Calibration Offset Value Register S, offset: 0xD0 */ + __IO uint32_t CLP3_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 3, offset: 0xD4 */ + __IO uint32_t CLP2_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 2, offset: 0xD8 */ + __IO uint32_t CLP1_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 1, offset: 0xDC */ + __IO uint32_t CLP0_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 0, offset: 0xE0 */ + __IO uint32_t CLPX_OFS; /**< ADC Plus-Side General Calibration Offset Value Register X, offset: 0xE4 */ + __IO uint32_t CLP9_OFS; /**< ADC Plus-Side General Calibration Offset Value Register 9, offset: 0xE8 */ +} ADC_Type, *ADC_MemMapPtr; + + /** Number of instances of the ADC module. */ +#define ADC_INSTANCE_COUNT (2u) + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x40027000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } + /** Number of interrupt vector arrays for the ADC module. */ +#define ADC_IRQS_ARR_COUNT (1u) + /** Number of interrupt channels for the ADC module. */ +#define ADC_IRQS_CH_COUNT (1u) +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* SC1 Bit Fields */ +#define ADC_SC1_ADCH_MASK 0x1Fu +#define ADC_SC1_ADCH_SHIFT 0u +#define ADC_SC1_ADCH_WIDTH 5u +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))< 0u) */ +#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1) +/* @brief Has Self Wake Up mode */ +#define FEATURE_CAN_HAS_SELF_WAKE_UP (0) +/* @brief Has Flexible Data Rate */ +#define FEATURE_CAN_HAS_FD (1) +/* @brief Clock name for the PE oscillator clock source */ +#define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK +/* @bried FlexCAN has Detection And Correction of Memory Errors */ +#define FEATURE_CAN_HAS_MEM_ERR_DET (0) + +/* LPUART module features */ + +/* @brief Has extended data register ED. */ +#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FEATURE_LPUART_FIFO_SIZE (4U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits. */ +#define FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Flag clearance mask for STAT register. */ +#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U) +/* @brief Flag clearance mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U) +/* @brief Reset mask for FIFO register. */ +#define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U) +/* @brief Default oversampling ratio. */ +#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL) +/* @brief Default baud rate modulo divisor. */ +#define FEATURE_LPUART_DEFAULT_SBR (0x04UL) +/* @brief Clock names for LPUART. */ +#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK, LPUART2_CLK} + +/* FlexIO module features */ + +/* @brief Define the maximum number of shifters for any FlexIO instance. */ +#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U) +/* @brief Define DMA request names for Flexio. */ +#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0 +#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1 +#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2 +#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3 + +/* LPSPI module features */ + +/* @brief DMA instance used for LPSPI module */ +#define LPSPI_DMA_INSTANCE 0U + +/* LPI2C module features */ + +/* @brief DMA instance used for LPI2C module */ +#define LPI2C_DMA_INSTANCE 0U + +/* @brief EDMA requests for LPI2C module. */ +#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}} +/* @brief PCC clocks for LPI2C module. */ +#define LPI2C_PCC_CLOCKS {LPI2C0_CLK} + +/* Interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn) +/* @brief Highest interrupt request number. */ +#define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn) +/**< Number of priority bits implemented in the NVIC */ +#define FEATURE_NVIC_PRIO_BITS (4U) +/* @brief Has software interrupt. */ +#define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u) +/* @brief Has pending interrupt state. */ +#define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u) +/* @brief Has active interrupt state. */ +#define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u) +/* @brief Multicore support for interrupts */ +#define FEATURE_INTERRUPT_MULTICORE_SUPPORT (0u) +/* @brief Registers in which the start of interrupt vector table needs to be configured */ +#define FEATURE_INTERRUPT_INT_VECTORS {&S32_SCB->VTOR} + + +/* System Control Block module features */ + +/* @brief VECTKEY value so that AIRCR register write is not ignored. */ +#define FEATURE_SCB_VECTKEY (0x05FAU) + + +/* SMC module features */ + +/* @brief Has stop option (register bit STOPCTRL[STOPO]). */ +#define FEATURE_SMC_HAS_STOPO (1U) +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FEATURE_SMC_HAS_PSTOPO (0U) +/* @brief Has WAIT and VLPW options. */ +#define FEATURE_SMC_HAS_WAIT_VLPW (0U) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1U) +/* @brief Value of SPLL source clock in the SCG_HCCR register */ +#define FEATURE_SCG_SPLL_VALUE (6U) +/* RCM module feature */ + +/* @brief Has existence of CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_EXISTENCE_CMU_LOSS_OF_CLOCK (0) +/* @brief Has CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK (0) +/* @brief Has sticky CMU loss of clock as reset source */ +#define FEATURE_RCM_HAS_STICKY_CMU_LOSS_OF_CLOCK (0) + +/* MPU module features */ + +/* @brief Specifies hardware revision level. */ +#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U) +/* @brief Has process identifier support. */ +#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U) +/* @brief Specifies total number of bus masters. */ +#define FEATURE_MPU_MASTER_COUNT (3U) +/* @brief Specifies maximum number of masters which have separated +privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x). +*/ +#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U) +/* @brief Specifies maximum number of masters which have only +read and write permissions (e.g. master4~7 in S32K14x). +*/ +#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U) + +/* @brief Specifies number of set access control right bits for + masters which have separated privilege rights for user and + supervisor mode accesses (e.g. master0~3 in S32K14x). +*/ +#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U) +/* @brief Specifies number of set access control right bits for + masters which have only read and write permissions(e.g. master4~7 in S32K14x). +*/ +#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U) + +/* @brief The MPU Logical Bus Master Number for core bus master. */ +#define FEATURE_MPU_MASTER_CORE (0U) +/* @brief The MPU Logical Bus Master Number for Debugger master. */ +#define FEATURE_MPU_MASTER_DEBUGGER (1U) +/* @brief The MPU Logical Bus Master Number for DMA master. */ +#define FEATURE_MPU_MASTER_DMA (2U) +/* @brief Specifies master number. */ +#define FEATURE_MPU_MASTER \ +{ \ + FEATURE_MPU_MASTER_CORE, /*!< CORE */ \ + FEATURE_MPU_MASTER_DEBUGGER, /*!< DEBUGGER */ \ + FEATURE_MPU_MASTER_DMA, /*!< DMA */ \ +} + +/* @brief Specifies total number of slave ports. */ +#define FEATURE_MPU_SLAVE_COUNT (4U) +/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */ +#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U) +/* @brief The MPU Slave Port Assignment for SRAM back door. */ +#define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U) +/* @brief The MPU Slave Port Assignment for SRAM_L front door. */ +#define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U) +/* @brief The MPU Slave Port Assignment for SRAM_U front door. */ +#define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U) +/* @brief The MPU Slave Port mask. */ +#define FEATURE_MPU_SLAVE_MASK (0xF0000000U) +#define FEATURE_MPU_SLAVE_SHIFT (28u) +#define FEATURE_MPU_SLAVE_WIDTH (4u) +#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<> (uint32_t)FEATURE_DMA_CH_WIDTH) +/* @brief DMA virtual channel to channel */ +#define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U)) +/* @brief DMA supports the following particular transfer size: */ +#define FEATURE_DMA_TRANSFER_SIZE_16B +#define FEATURE_DMA_TRANSFER_SIZE_32B + +/* DMAMUX module features */ + +/* @brief DMAMUX peripheral is available in silicon. */ +#define FEATURE_DMAMUX_AVAILABLE +/* @brief Number of DMA channels. */ +#define FEATURE_DMAMUX_CHANNELS (16U) +/* @brief Has the periodic trigger capability */ +#define FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Conversion from request source to the actual DMAMUX channel */ +#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x) +/* @brief Mapping between request source and DMAMUX instance */ +#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U) +/* @brief Conversion from eDMA channel index to DMAMUX channel. */ +#define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x) +/* @brief Conversion from DMAMUX channel DMAMUX register index. */ +#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x) +/* @brief Clock names for DMAMUX. */ +#define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK} +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ + +typedef enum { + EDMA_REQ_DISABLED = 0U, + EDMA_REQ_LPUART0_RX = 2U, + EDMA_REQ_LPUART0_TX = 3U, + EDMA_REQ_LPUART1_RX = 4U, + EDMA_REQ_LPUART1_TX = 5U, + EDMA_REQ_LPUART2_RX = 6U, + EDMA_REQ_LPUART2_TX = 7U, + EDMA_REQ_FLEXIO_SHIFTER0 = 10U, + EDMA_REQ_FLEXIO_SHIFTER1 = 11U, + EDMA_REQ_FLEXIO_SHIFTER2 = 12U, + EDMA_REQ_FLEXIO_SHIFTER3 = 13U, + EDMA_REQ_LPSPI0_RX = 14U, + EDMA_REQ_LPSPI0_TX = 15U, + EDMA_REQ_LPSPI1_RX = 16U, + EDMA_REQ_LPSPI1_TX = 17U, + EDMA_REQ_LPSPI2_RX = 18U, + EDMA_REQ_LPSPI2_TX = 19U, + EDMA_REQ_FTM1_CHANNEL_0 = 20U, + EDMA_REQ_FTM1_CHANNEL_1 = 21U, + EDMA_REQ_FTM1_CHANNEL_2 = 22U, + EDMA_REQ_FTM1_CHANNEL_3 = 23U, + EDMA_REQ_FTM1_CHANNEL_4 = 24U, + EDMA_REQ_FTM1_CHANNEL_5 = 25U, + EDMA_REQ_FTM1_CHANNEL_6 = 26U, + EDMA_REQ_FTM1_CHANNEL_7 = 27U, + EDMA_REQ_FTM2_CHANNEL_0 = 28U, + EDMA_REQ_FTM2_CHANNEL_1 = 29U, + EDMA_REQ_FTM2_CHANNEL_2 = 30U, + EDMA_REQ_FTM2_CHANNEL_3 = 31U, + EDMA_REQ_FTM2_CHANNEL_4 = 32U, + EDMA_REQ_FTM2_CHANNEL_5 = 33U, + EDMA_REQ_FTM2_CHANNEL_6 = 34U, + EDMA_REQ_FTM2_CHANNEL_7 = 35U, + EDMA_REQ_FTM0_OR_CH0_CH7 = 36U, + EDMA_REQ_FTM3_OR_CH0_CH7 = 37U, + EDMA_REQ_ADC0 = 42U, + EDMA_REQ_ADC1 = 43U, + EDMA_REQ_LPI2C0_RX = 44U, + EDMA_REQ_LPI2C0_TX = 45U, + EDMA_REQ_PDB0 = 46U, + EDMA_REQ_PDB1 = 47U, + EDMA_REQ_CMP0 = 48U, + EDMA_REQ_PORTA = 49U, + EDMA_REQ_PORTB = 50U, + EDMA_REQ_PORTC = 51U, + EDMA_REQ_PORTD = 52U, + EDMA_REQ_PORTE = 53U, + EDMA_REQ_FLEXCAN0 = 54U, + EDMA_REQ_FLEXCAN1 = 55U, + EDMA_REQ_FLEXCAN2 = 56U, + EDMA_REQ_LPTMR0 = 59U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED0 = 62U, + EDMA_REQ_DMAMUX_ALWAYS_ENABLED1 = 63U +} dma_request_source_t; + +/* LPI2C module features */ + +/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */ +#define LPI2C_HAS_FAST_PLUS_MODE (0U) +#define LPI2C_HAS_HIGH_SPEED_MODE (0U) +#define LPI2C_HAS_ULTRA_FAST_MODE (0U) + +/* FTM module features */ +/* @brief Number of PWM channels */ +#define FEATURE_FTM_CHANNEL_COUNT (8U) +/* @brief Number of fault channels */ +#define FTM_FEATURE_FAULT_CHANNELS (4U) +/* @brief Width of control channel */ +#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U) +/* @brief Output channel offset */ +#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U) +/* @brief Max counter value */ +#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU) +/* @brief Input capture for single shot */ +#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U) +/* @brief Dithering has supported on the generated PWM signals */ +#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (0U) +/*! @brief Number of interrupt vector for channels of the FTM module. */ +#define FEATURE_FTM_HAS_NUM_IRQS_CHANS (4U) + +/* EWM module features */ + +/* @brief First byte of the EWM Service key */ +#define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U) +/* @brief Second byte of the EWM Service key */ +#define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU) +/* @brief EWM Compare High register maximum value */ +#define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU) +/* @brief EWM Compare Low register minimum value */ +#define FEATURE_EWM_CMPL_MIN_VALUE (0x00U) + +/* @brief Supports high speed run mode. */ +#define FEATURE_HAS_HIGH_SPEED_RUN_MODE (1U) +/* @brief Supports SPLL clock source. */ +#define FEATURE_HAS_SPLL_CLK (1U) + +/*! @brief Clock names. */ +typedef enum { + + /* Main clocks */ + CORE_CLK = 0u, /*!< Core clock */ + BUS_CLK = 1u, /*!< Bus clock */ + SLOW_CLK = 2u, /*!< Slow clock */ + CLKOUT_CLK = 3u, /*!< CLKOUT clock */ + + /* Other internal clocks used by peripherals. */ + SIRC_CLK = 4u, /*!< SIRC clock */ + FIRC_CLK = 5u, /*!< FIRC clock */ + SOSC_CLK = 6u, /*!< SOSC clock */ + SPLL_CLK = 7u, /*!< SPLL clock */ + RTC_CLKIN_CLK = 8u, /*!< RTC_CLKIN clock */ + SCG_CLKOUT_CLK = 9u, /*!< SCG CLK_OUT clock */ + + SIRCDIV1_CLK = 10u, /*!< SIRCDIV1 functional clock */ + SIRCDIV2_CLK = 11u, /*!< SIRCDIV2 functional clock */ + FIRCDIV1_CLK = 12u, /*!< FIRCDIV1 functional clock */ + FIRCDIV2_CLK = 13u, /*!< FIRCDIV2 functional clock */ + SOSCDIV1_CLK = 14u, /*!< SOSCDIV1 functional clock */ + SOSCDIV2_CLK = 15u, /*!< SOSCDIV2 functional clock */ + SPLLDIV1_CLK = 16u, /*!< SPLLDIV1 functional clock */ + SPLLDIV2_CLK = 17u, /*!< SPLLDIV2 functional clock */ + + SCG_END_OF_CLOCKS = 18u, /*!< End of SCG clocks */ + + /* SIM clocks */ + SIM_FTM0_CLOCKSEL = 21u, /*!< FTM0 External Clock Pin Select */ + SIM_FTM1_CLOCKSEL = 22u, /*!< FTM1 External Clock Pin Select */ + SIM_FTM2_CLOCKSEL = 23u, /*!< FTM2 External Clock Pin Select */ + SIM_FTM3_CLOCKSEL = 24u, /*!< FTM3 External Clock Pin Select */ + SIM_CLKOUTSELL = 25u, /*!< CLKOUT Select */ + SIM_RTCCLK_CLK = 26u, /*!< RTCCLK clock */ + SIM_LPO_CLK = 27u, /*!< LPO clock */ + SIM_LPO_1K_CLK = 28u, /*!< LPO 1KHz clock */ + SIM_LPO_32K_CLK = 29u, /*!< LPO 32KHz clock */ + SIM_LPO_128K_CLK = 30u, /*!< LPO 128KHz clock */ + SIM_EIM_CLK = 31u, /*!< EIM clock source */ + SIM_ERM_CLK = 32u, /*!< ERM clock source */ + SIM_DMA_CLK = 33u, /*!< DMA clock source */ + SIM_MPU_CLK = 34u, /*!< MPU clock source */ + SIM_MSCM_CLK = 35u, /*!< MSCM clock source */ + SIM_END_OF_CLOCKS = 36u, /*!< End of SIM clocks */ + + /* PCC clocks */ + CMP0_CLK = 41u, /*!< CMP0 clock source */ + CRC0_CLK = 42u, /*!< CRC0 clock source */ + DMAMUX0_CLK = 43u, /*!< DMAMUX0 clock source */ + EWM0_CLK = 44u, /*!< EWM0 clock source */ + PORTA_CLK = 45u, /*!< PORTA clock source */ + PORTB_CLK = 46u, /*!< PORTB clock source */ + PORTC_CLK = 47u, /*!< PORTC clock source */ + PORTD_CLK = 48u, /*!< PORTD clock source */ + PORTE_CLK = 49u, /*!< PORTE clock source */ + RTC0_CLK = 50u, /*!< RTC0 clock source */ + PCC_END_OF_BUS_CLOCKS = 51u, /*!< End of BUS clocks */ + FlexCAN0_CLK = 52u, /*!< FlexCAN0 clock source */ + FlexCAN1_CLK = 53u, /*!< FlexCAN1 clock source */ + FlexCAN2_CLK = 54u, /*!< FlexCAN2 clock source */ + PDB0_CLK = 55u, /*!< PDB0 clock source */ + PDB1_CLK = 56u, /*!< PDB1 clock source */ + PCC_END_OF_SYS_CLOCKS = 57u, /*!< End of SYS clocks */ + FTFC0_CLK = 58u, /*!< FTFC0 clock source */ + PCC_END_OF_SLOW_CLOCKS = 59u, /*!< End of SLOW clocks */ + FTM0_CLK = 60u, /*!< FTM0 clock source */ + FTM1_CLK = 61u, /*!< FTM1 clock source */ + FTM2_CLK = 62u, /*!< FTM2 clock source */ + FTM3_CLK = 63u, /*!< FTM3 clock source */ + PCC_END_OF_ASYNCH_DIV1_CLOCKS= 64u, /*!< End of ASYNCH DIV1 clocks */ + ADC0_CLK = 65u, /*!< ADC0 clock source */ + ADC1_CLK = 66u, /*!< ADC1 clock source */ + FLEXIO0_CLK = 67u, /*!< FLEXIO0 clock source */ + LPI2C0_CLK = 68u, /*!< LPI2C0 clock source */ + LPIT0_CLK = 69u, /*!< LPIT0 clock source */ + LPSPI0_CLK = 70u, /*!< LPSPI0 clock source */ + LPSPI1_CLK = 71u, /*!< LPSPI1 clock source */ + LPSPI2_CLK = 72u, /*!< LPSPI2 clock source */ + LPTMR0_CLK = 73u, /*!< LPTMR0 clock source */ + LPUART0_CLK = 74u, /*!< LPUART0 clock source */ + LPUART1_CLK = 75u, /*!< LPUART1 clock source */ + LPUART2_CLK = 76u, /*!< LPUART2 clock source */ + PCC_END_OF_ASYNCH_DIV2_CLOCKS= 77u, /*!< End of ASYNCH DIV2 clocks */ + PCC_END_OF_CLOCKS = 78u, /*!< End of PCC clocks */ + CLOCK_NAME_COUNT = 79u, /*!< The total number of entries */ +} clock_names_t; + +#define PCC_INVALID_INDEX 0 + + /*! @brief PCC clock name mappings + * Mappings between clock names and peripheral clock control indexes. + * If there is no peripheral clock control index for a clock name, + * then the corresponding value is PCC_INVALID_INDEX. + */ +#define PCC_CLOCK_NAME_MAPPINGS \ +{ \ +PCC_INVALID_INDEX, /*!< Core clock 0 */ \ +PCC_INVALID_INDEX, /*!< Bus clock 1 */ \ +PCC_INVALID_INDEX, /*!< Slow clock 2 */ \ +PCC_INVALID_INDEX, /*!< CLKOUT clock 3 */ \ +PCC_INVALID_INDEX, /*!< SIRC clock 4 */ \ +PCC_INVALID_INDEX, /*!< FIRC clock 5 */ \ +PCC_INVALID_INDEX, /*!< SOSC clock 6 */ \ +PCC_INVALID_INDEX, /*!< SPLL clock 7 */ \ +PCC_INVALID_INDEX, /*!< RTC_CLKIN clock 8 */ \ +PCC_INVALID_INDEX, /*!< SCG CLK_OUT clock 9 */ \ +PCC_INVALID_INDEX, /*!< SIRCDIV1 functional clock 10 */ \ +PCC_INVALID_INDEX, /*!< SIRCDIV2 functional clock 11 */ \ +PCC_INVALID_INDEX, /*!< FIRCDIV1 functional clock 12 */ \ +PCC_INVALID_INDEX, /*!< FIRCDIV2 functional clock 13 */ \ +PCC_INVALID_INDEX, /*!< SOSCDIV1 functional clock 14 */ \ +PCC_INVALID_INDEX, /*!< SOSCDIV2 functional clock 15 */ \ +PCC_INVALID_INDEX, /*!< SPLLDIV1 functional clock 16 */ \ +PCC_INVALID_INDEX, /*!< SPLLDIV2 functional clock 17 */ \ +PCC_INVALID_INDEX, /*!< End of SCG clocks 18 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 19 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 20 */ \ +PCC_INVALID_INDEX, /*!< FTM0 External Clock Pin Select 21 */ \ +PCC_INVALID_INDEX, /*!< FTM1 External Clock Pin Select 22 */ \ +PCC_INVALID_INDEX, /*!< FTM2 External Clock Pin Select 23 */ \ +PCC_INVALID_INDEX, /*!< FTM3 External Clock Pin Select 24 */ \ +PCC_INVALID_INDEX, /*!< CLKOUT Select 25 */ \ +PCC_INVALID_INDEX, /*!< CLK32K clock 26 */ \ +PCC_INVALID_INDEX, /*!< LPO clock 27 */ \ +PCC_INVALID_INDEX, /*!< LPO 1KHz clock 28 */ \ +PCC_INVALID_INDEX, /*!< LPO 32KHz clock 29 */ \ +PCC_INVALID_INDEX, /*!< LPO 128KHz clock 30 */ \ +PCC_INVALID_INDEX, /*!< EIM clock source 31 */ \ +PCC_INVALID_INDEX, /*!< ERM clock source 32 */ \ +PCC_INVALID_INDEX, /*!< DMA clock source 33 */ \ +PCC_INVALID_INDEX, /*!< MPU clock source 34 */ \ +PCC_INVALID_INDEX, /*!< MSCM clock source 35 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 36 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 37 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 38 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 39 */ \ +PCC_INVALID_INDEX, /*!< No clock entry in clock_names_t 40 */ \ +PCC_CMP0_INDEX, /*!< CMP0 clock source 41 */ \ +PCC_CRC_INDEX, /*!< CRC clock source 42 */ \ +PCC_DMAMUX_INDEX, /*!< DMAMUX clock source 43 */ \ +PCC_EWM_INDEX, /*!< EWM clock source 44 */ \ +PCC_PORTA_INDEX, /*!< PORTA clock source 45 */ \ +PCC_PORTB_INDEX, /*!< PORTB clock source 46 */ \ +PCC_PORTC_INDEX, /*!< PORTC clock source 47 */ \ +PCC_PORTD_INDEX, /*!< PORTD clock source 48 */ \ +PCC_PORTE_INDEX, /*!< PORTE clock source 49 */ \ +PCC_RTC_INDEX, /*!< RTC clock source 50 */ \ +PCC_INVALID_INDEX, /*!< End of BUS clocks 51 */ \ +PCC_FlexCAN0_INDEX, /*!< FlexCAN0 clock source 52 */ \ +PCC_FlexCAN1_INDEX, /*!< FlexCAN1 clock source 53 */ \ +PCC_FlexCAN2_INDEX, /*!< FlexCAN2 clock source 54 */ \ +PCC_PDB0_INDEX, /*!< PDB0 clock source 55 */ \ +PCC_PDB1_INDEX, /*!< PDB1 clock source 56 */ \ +PCC_INVALID_INDEX, /*!< End of SYS clocks 57 */ \ +PCC_FTFC_INDEX, /*!< FTFC clock source 58 */ \ +PCC_INVALID_INDEX, /*!< End of SLOW clocks 59 */ \ +PCC_FTM0_INDEX, /*!< FTM0 clock source 60 */ \ +PCC_FTM1_INDEX, /*!< FTM1 clock source 61 */ \ +PCC_FTM2_INDEX, /*!< FTM2 clock source 62 */ \ +PCC_FTM3_INDEX, /*!< FTM3 clock source 63 */ \ +PCC_INVALID_INDEX, /*!< End of ASYNCH DIV1 clocks 64 */ \ +PCC_ADC0_INDEX, /*!< ADC0 clock source 65 */ \ +PCC_ADC1_INDEX, /*!< ADC1 clock source 66 */ \ +PCC_FlexIO_INDEX, /*!< FLEXIO clock source 67 */ \ +PCC_LPI2C0_INDEX, /*!< LPI2C0 clock source 68 */ \ +PCC_LPIT_INDEX, /*!< LPIT clock source 69 */ \ +PCC_LPSPI0_INDEX, /*!< LPSPI0 clock source 70 */ \ +PCC_LPSPI1_INDEX, /*!< LPSPI1 clock source 71 */ \ +PCC_LPSPI2_INDEX, /*!< LPSPI2 clock source 72 */ \ +PCC_LPTMR0_INDEX, /*!< LPTMR0 clock source 73 */ \ +PCC_LPUART0_INDEX, /*!< LPUART0 clock source 74 */ \ +PCC_LPUART1_INDEX, /*!< LPUART1 clock source 75 */ \ +PCC_LPUART2_INDEX, /*!< LPUART2 clock source 76 */ \ +PCC_INVALID_INDEX, /*!< End of ASYNCH DIV2 clocks 77 */ \ +PCC_INVALID_INDEX, /*!< End of PCC clocks 78 */ \ +} + +/*! @brief Peripheral instance features + * List of features that are supported by a peripheral instance + */ +#define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */ +#define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */ +#define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */ +#define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */ +#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */ +#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */ +#define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */ +#define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */ +#define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */ + +/*! @brief Peripheral features. +* List of features for each clock name. If a clock name is not +* a peripheral, no feature is supported. +*/ +#define PERIPHERAL_FEATURES \ +{ \ +(NO_PERIPHERAL_FEATURE), /*!< Core clock 0 */ \ +(NO_PERIPHERAL_FEATURE), /*!< Bus clock 1 */ \ +(NO_PERIPHERAL_FEATURE), /*!< Slow clock 2 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLKOUT clock 3 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SIRC clock 4 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FIRC clock 5 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SOSC clock 6 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SPLL clock 7 */ \ +(NO_PERIPHERAL_FEATURE), /*!< RTC_CLKIN clock 8 */ \ +(NO_PERIPHERAL_FEATURE), /*!< SCG CLK_OUT clock 9 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SCG clocks 10 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 11 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 12 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 13 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 14 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 15 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 16 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 17 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 18 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 19 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 20 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM0 External Clock Pin Select 21 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM1 External Clock Pin Select 22 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM2 External Clock Pin Select 23 */ \ +(NO_PERIPHERAL_FEATURE), /*!< FTM3 External Clock Pin Select 24 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLKOUT Select 25 */ \ +(NO_PERIPHERAL_FEATURE), /*!< CLK32K clock 26 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO clock 27 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 1KHz clock 28 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 32KHz clock 29 */ \ +(NO_PERIPHERAL_FEATURE), /*!< LPO 128KHz clock 30 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< EIM clock source 31 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< ERM clock source 32 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< DMA clock source 33 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< MPU clock source 34 */ \ +(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< MSCM clock source 35 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 36 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 37 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 38 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 39 */ \ +(NO_PERIPHERAL_FEATURE), /*!< No clock entry in clock_names_t 40 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< CMP0 clock source 41 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< CRC clock source 42 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< DMAMUX clock source 43 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< EWM clock source 44 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTA clock source 45 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTB clock source 46 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTC clock source 47 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTD clock source 48 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< PORTE clock source 49 */ \ +(HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< RTC clock source 50 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of BUS clocks 51 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN0 clock source 52 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN1 clock source 53 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FlexCAN2 clock source 54 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< PDB0 clock source 55 */ \ +(HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< PDB1 clock source 56 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SYS clocks 57 */ \ +(HAS_INT_CLOCK_FROM_SLOW_CLOCK), /*!< FTFC clock source 58 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of SLOW clocks 59 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM0 clock source 60 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM1 clock source 61 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM2 clock source 62 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), /*!< FTM3 clock source 63 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of ASYNCH DIV1 clocks 64 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< ADC0 clock source 65 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< ADC1 clock source 66 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< FLEXIO clock source 67 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPI2C0 clock source 68 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPIT clock source 69 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI0 clock source 70 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI1 clock source 71 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPSPI2 clock source 72 */ \ +(HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPTMR0 clock source 73 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART0 clock source 74 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART1 clock source 75 */ \ +(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), /*!< LPUART2 clock source 76 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of ASYNCH DIV2 clocks 77 */ \ +(NO_PERIPHERAL_FEATURE), /*!< End of PCC clocks 78 */ \ +} + +/* Time to wait for SIRC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SIRC_STABILIZATION_TIMEOUT 100U + +/* Time to wait for FIRC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define FIRC_STABILIZATION_TIMEOUT 20U + +/* Time to wait for SOSC to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SOSC_STABILIZATION_TIMEOUT 3205000U; + +/* Time to wait for SPLL to stabilize (number of + * cycles when core runs at maximum speed - 112 MHz */ +#define SPLL_STABILIZATION_TIMEOUT 1000U; + + +/*! @brief Temporary system clock source configurations. + * Each line represents the SYS(CORE), BUS and SLOW(FLASH) dividers + * for SIRC, FIRC, SOSC and SPLL clock sources. + * + * SYS_CLK BUS_CLK SLOW_CLK + * SIRC * * * + * FIRC * * * + * SOSC * * * + * SPLL * * * + */ +#define TMP_SIRC_CLK 0U +#define TMP_FIRC_CLK 1U +#define TMP_SOSC_CLK 2U +#define TMP_SPLL_CLK 3U + +#define TMP_SYS_DIV 0U +#define TMP_BUS_DIV 1U +#define TMP_SLOW_DIV 2U + +#define TMP_SYS_CLK_NO 4U +#define TMP_SYS_DIV_NO 3U + +#define TMP_SYSTEM_CLOCK_CONFIGS \ +{ /* SYS_CLK BUS_CLK SLOW_CLK */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SIRC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, /*!< Dividers for FIRC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SOSC */ \ +{ SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, /*!< Dividers for SPLL */ \ +} + +/* Do not use the old names of the renamed symbols */ +/* #define DO_NOT_USE_DEPRECATED_SYMBOLS */ + +/*! START !DO_NOT_USE_DEPRECATED_SYMBOLS + * These symbols have been renamed. + * The old names (deprecated symbols) + * are defined for backward compatibility. + */ +#if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS) +#define CORE_CLOCK CORE_CLK +#define BUS_CLOCK BUS_CLK +#define SLOW_CLOCK SLOW_CLK +#define CLKOUT_CLOCK CLKOUT_CLK +#define SIRC_CLOCK SIRC_CLK +#define FIRC_CLOCK FIRC_CLK +#define SOSC_CLOCK SOSC_CLK +#define SPLL_CLOCK SPLL_CLK +#define RTC_CLKIN_CLOCK RTC_CLKIN_CLK +#define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK +#define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK +#define SIM_LPO_CLOCK SIM_LPO_CLK +#define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK +#define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK +#define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK +#define SIM_EIM_CLOCK SIM_EIM_CLK +#define SIM_ERM_CLOCK SIM_ERM_CLK +#define SIM_DMA_CLOCK SIM_DMA_CLK +#define SIM_MPU_CLOCK SIM_MPU_CLK +#define SIM_MSCM_CLOCK SIM_MSCM_CLK +#define PCC_DMAMUX0_CLOCK DMAMUX0_CLK +#define PCC_CRC0_CLOCK CRC0_CLK +#define PCC_RTC0_CLOCK RTC0_CLK +#define PCC_PORTA_CLOCK PORTA_CLK +#define PCC_PORTB_CLOCK PORTB_CLK +#define PCC_PORTC_CLOCK PORTC_CLK +#define PCC_PORTD_CLOCK PORTD_CLK +#define PCC_PORTE_CLOCK PORTE_CLK +#define PCC_EWM0_CLOCK EWM0_CLK +#define PCC_CMP0_CLOCK CMP0_CLK +#define PCC_FlexCAN0_CLOCK FlexCAN0_CLK +#define PCC_FlexCAN1_CLOCK FlexCAN1_CLK +#define PCC_FlexCAN2_CLOCK FlexCAN2_CLK +#define PCC_PDB1_CLOCK PDB1_CLK +#define PCC_PDB0_CLOCK PDB0_CLK +#define PCC_FTFC0_CLOCK FTFC0_CLK +#define PCC_FTM0_CLOCK FTM0_CLK +#define PCC_FTM1_CLOCK FTM1_CLK +#define PCC_FTM2_CLOCK FTM2_CLK +#define PCC_FTM3_CLOCK FTM3_CLK +#define PCC_ADC1_CLOCK ADC1_CLK +#define PCC_LPSPI0_CLOCK LPSPI0_CLK +#define PCC_LPSPI1_CLOCK LPSPI1_CLK +#define PCC_LPSPI2_CLOCK LPSPI2_CLK +#define PCC_LPIT0_CLOCK LPIT0_CLK +#define PCC_ADC0_CLOCK ADC0_CLK +#define PCC_LPTMR0_CLOCK LPTMR0_CLK +#define PCC_FLEXIO0_CLOCK FLEXIO0_CLK +#define PCC_LPI2C0_CLOCK LPI2C0_CLK +#define PCC_LPUART0_CLOCK LPUART0_CLK +#define PCC_LPUART1_CLOCK LPUART1_CLK +#define PCC_LPUART2_CLOCK LPUART2_CLK +#endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */ + + +/* CSEc module features */ + +/*! @brief CSE_PRAM offset of the page length parameter used by the following +commands: CMD_ENC_ECB, CMD_ENC_CBC, CMD_DEC_ECB, CMD_DEC_CBC, CMD_MP_COMPRESS */ +#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU) +/*! @brief CSE_PRAM offset of the message length parameter used by the following +commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU) +/*! @brief CSE_PRAM offset of the MAC length parameter used by the following +commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U) +/*! @brief CSE_PRAM offset of the boot size parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU) +/*! @brief CSE_PRAM offset of the boot flavor parameter used by the following +commands: CMD_BOOT_DEFINE */ +#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU) +/*! @brief CSE_PRAM offset of the Flash start address parameter used by the +following commands: CMD_GENERATE_MAC, CMD_VERIFY_MAC (pointer method) */ +#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of the verification status parameter used by the +following commands: CMD_VERIFY_MAC (both copy and pointer methods) */ +#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U) +/*! @brief CSE_PRAM offset of the error bits field contained by all commands */ +#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U) +/*! @brief CSE_PRAM offset of the SREG parameter used by the following commands: +CMD_GET_ID */ +#define FEATURE_CSEC_SREG_OFFSET (0x2FU) + +/*! @brief CSE_PRAM offset of page 0 */ +#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U) +/*! @brief CSE_PRAM offset of page 1 */ +#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U) +/*! @brief CSE_PRAM offset of page 2 */ +#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U) +/*! @brief CSE_PRAM offset of page 3 */ +#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U) +/*! @brief CSE_PRAM offset of page 4 */ +#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U) +/*! @brief CSE_PRAM offset of page 5 */ +#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U) +/*! @brief CSE_PRAM offset of page 6 */ +#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U) +/*! @brief CSE_PRAM offset of page 7 */ +#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U) + + +/* ADC module features */ + +/*! @brief ADC feature flag for extended number of SC1 and R registers, + * generically named 'alias registers' */ +#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0) + +/*! @brief ADC feature flag for defining number of external ADC channels. + * If each ADC instance has different number of external channels, then + * this define is set with the maximum value. */ +#define FEATURE_ADC_MAX_NUM_EXT_CHANS (16) +#define FEATURE_ADC_HAS_CHANNEL_2 (1) +#define FEATURE_ADC_HAS_CHANNEL_8 (1) +#define ADC_CLOCKS {ADC0_CLK, ADC1_CLK} + +/*! @brief ADC number of control channels */ +#if FEATURE_ADC_HAS_EXTRA_NUM_REGS +#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT +#else +#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT +#endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */ + +/*! @brief ADC default Sample Time from RM */ +#define ADC_DEFAULT_SAMPLE_TIME (0x0CU) +/*! @brief ADC default User Gain from RM */ +#define ADC_DEFAULT_USER_GAIN (0x04U) +/* @brief Max of adc clock frequency */ +#define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u) +/* @brief Min of adc clock frequency */ +#define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u) + +/* LPIT module features */ + +/*! @brief Number of interrupt vector for channels of the LPIT module. */ +#define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (4U) +/*! @brief Clock names for LPIT. */ +#define LPIT_CLOCK_NAMES {LPIT0_CLK} + +/* MSCM module features */ + +/* @brief Has interrupt router control registers (IRSPRCn). */ +#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0) +/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */ +#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0) + +/* OSIF module features */ + +#define FEATURE_OSIF_USE_SYSTICK (1) +#define FEATURE_OSIF_USE_PIT (0) +#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */ + +/* LPSPI module features */ +/* @brief Initial value for state structure */ +#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL, NULL} +/* @brief Clock indexes for LPSPI clock */ +#define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK, LPSPI2_CLK}; + +/* LPTMR module features */ + +/* @brief LPTMR pulse counter input options */ +#define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U) + +/* TRGMUX module features */ +/*! + * @brief Enumeration for trigger source module of TRGMUX + * + * Describes all possible inputs (trigger sources) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_trigger_source_e +{ + TRGMUX_TRIG_SOURCE_DISABLED = 0U, + TRGMUX_TRIG_SOURCE_VDD = 1U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN0 = 2U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN1 = 3U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN2 = 4U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN3 = 5U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN4 = 6U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN5 = 7U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN6 = 8U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN7 = 9U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN8 = 10U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN9 = 11U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN10 = 12U, + TRGMUX_TRIG_SOURCE_TRGMUX_IN11 = 13U, + TRGMUX_TRIG_SOURCE_CMP0_OUT = 14U, + TRGMUX_TRIG_SOURCE_LPIT_CH0 = 17U, + TRGMUX_TRIG_SOURCE_LPIT_CH1 = 18U, + TRGMUX_TRIG_SOURCE_LPIT_CH2 = 19U, + TRGMUX_TRIG_SOURCE_LPIT_CH3 = 20U, + TRGMUX_TRIG_SOURCE_LPTMR0 = 21U, + TRGMUX_TRIG_SOURCE_FTM0_INIT_TRIG = 22U, + TRGMUX_TRIG_SOURCE_FTM0_EXT_TRIG = 23U, + TRGMUX_TRIG_SOURCE_FTM1_INIT_TRIG = 24U, + TRGMUX_TRIG_SOURCE_FTM1_EXT_TRIG = 25U, + TRGMUX_TRIG_SOURCE_FTM2_INIT_TRIG = 26U, + TRGMUX_TRIG_SOURCE_FTM2_EXT_TRIG = 27U, + TRGMUX_TRIG_SOURCE_FTM3_INIT_TRIG = 28U, + TRGMUX_TRIG_SOURCE_FTM3_EXT_TRIG = 29U, + TRGMUX_TRIG_SOURCE_ADC0_SC1A_COCO = 30U, + TRGMUX_TRIG_SOURCE_ADC0_SC1B_COCO = 31U, + TRGMUX_TRIG_SOURCE_ADC1_SC1A_COCO = 32U, + TRGMUX_TRIG_SOURCE_ADC1_SC1B_COCO = 33U, + TRGMUX_TRIG_SOURCE_PDB0_CH0_TRIG = 34U, + TRGMUX_TRIG_SOURCE_PDB0_PULSE_OUT = 36U, + TRGMUX_TRIG_SOURCE_PDB1_CH0_TRIG = 37U, + TRGMUX_TRIG_SOURCE_PDB1_PULSE_OUT = 39U, + TRGMUX_TRIG_SOURCE_RTC_ALARM = 43U, + TRGMUX_TRIG_SOURCE_RTC_SECOND = 44U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG0 = 45U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG1 = 46U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG2 = 47U, + TRGMUX_TRIG_SOURCE_FLEXIO_TRIG3 = 48U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_DATA = 49U, + TRGMUX_TRIG_SOURCE_LPUART0_TX_DATA = 50U, + TRGMUX_TRIG_SOURCE_LPUART0_RX_IDLE = 51U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_DATA = 52U, + TRGMUX_TRIG_SOURCE_LPUART1_TX_DATA = 53U, + TRGMUX_TRIG_SOURCE_LPUART1_RX_IDLE = 54U, + TRGMUX_TRIG_SOURCE_LPI2C0_MASTER_TRIG = 55U, + TRGMUX_TRIG_SOURCE_LPI2C0_SLAVE_TRIG = 56U, + TRGMUX_TRIG_SOURCE_LPSPI0_FRAME = 59U, + TRGMUX_TRIG_SOURCE_LPSPI0_RX_DATA = 60U, + TRGMUX_TRIG_SOURCE_LPSPI1_FRAME = 61U, + TRGMUX_TRIG_SOURCE_LPSPI1_RX_DATA = 62U, + TRGMUX_TRIG_SOURCE_SIM_SW_TRIG = 63U +}; + +/*! + * @brief Enumeration for target module of TRGMUX + * + * Describes all possible outputs (target modules) of the TRGMUX IP + * This enumeration depends on the supported instances in device + */ +enum trgmux_target_module_e +{ + TRGMUX_TARGET_MODULE_DMA_CH0 = 0U, + TRGMUX_TARGET_MODULE_DMA_CH1 = 1U, + TRGMUX_TARGET_MODULE_DMA_CH2 = 2U, + TRGMUX_TARGET_MODULE_DMA_CH3 = 3U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT0 = 4U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT1 = 5U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT2 = 6U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT3 = 7U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT4 = 8U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT5 = 9U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT6 = 10U, + TRGMUX_TARGET_MODULE_TRGMUX_OUT7 = 11U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0 = 12U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1 = 13U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2 = 14U, + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3 = 15U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA0 = 16U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA1 = 17U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA2 = 18U, + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA3 = 19U, + TRGMUX_TARGET_MODULE_CMP0_SAMPLE = 28U, + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0 = 40U, + TRGMUX_TARGET_MODULE_FTM0_FAULT0 = 41U, + TRGMUX_TARGET_MODULE_FTM0_FAULT1 = 42U, + TRGMUX_TARGET_MODULE_FTM0_FAULT2 = 43U, + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0 = 44U, + TRGMUX_TARGET_MODULE_FTM1_FAULT0 = 45U, + TRGMUX_TARGET_MODULE_FTM1_FAULT1 = 46U, + TRGMUX_TARGET_MODULE_FTM1_FAULT2 = 47U, + TRGMUX_TARGET_MODULE_FTM2_HWTRIG0 = 48U, + TRGMUX_TARGET_MODULE_FTM2_FAULT0 = 49U, + TRGMUX_TARGET_MODULE_FTM2_FAULT1 = 50U, + TRGMUX_TARGET_MODULE_FTM2_FAULT2 = 51U, + TRGMUX_TARGET_MODULE_FTM3_HWTRIG0 = 52U, + TRGMUX_TARGET_MODULE_FTM3_FAULT0 = 53U, + TRGMUX_TARGET_MODULE_FTM3_FAULT1 = 54U, + TRGMUX_TARGET_MODULE_FTM3_FAULT2 = 55U, + TRGMUX_TARGET_MODULE_PDB0_TRG_IN = 56U, + TRGMUX_TARGET_MODULE_PDB1_TRG_IN = 60U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0 = 68U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1 = 69U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2 = 70U, + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3 = 71U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0 = 72U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1 = 73U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2 = 74U, + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3 = 75U, + TRGMUX_TARGET_MODULE_LPUART0_TRG = 76U, + TRGMUX_TARGET_MODULE_LPUART1_TRG = 80U, + TRGMUX_TARGET_MODULE_LPI2C0_TRG = 84U, + TRGMUX_TARGET_MODULE_LPSPI0_TRG = 92U, + TRGMUX_TARGET_MODULE_LPSPI1_TRG = 96U, + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 = 100U +}; + +/* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */ +#define FEATURE_TRGMUX_TARGET_MODULE \ +{ \ + TRGMUX_TARGET_MODULE_DMA_CH0, \ + TRGMUX_TARGET_MODULE_DMA_CH1, \ + TRGMUX_TARGET_MODULE_DMA_CH2, \ + TRGMUX_TARGET_MODULE_DMA_CH3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT6, \ + TRGMUX_TARGET_MODULE_TRGMUX_OUT7, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA0, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA1, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA2, \ + TRGMUX_TARGET_MODULE_ADC1_ADHWT_TLA3, \ + TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \ + TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM0_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM1_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM2_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM2_FAULT2, \ + TRGMUX_TARGET_MODULE_FTM3_HWTRIG0, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT0, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT1, \ + TRGMUX_TARGET_MODULE_FTM3_FAULT2, \ + TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \ + TRGMUX_TARGET_MODULE_PDB1_TRG_IN, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \ + TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \ + TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \ + TRGMUX_TARGET_MODULE_LPUART0_TRG, \ + TRGMUX_TARGET_MODULE_LPUART1_TRG, \ + TRGMUX_TARGET_MODULE_LPI2C0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI0_TRG, \ + TRGMUX_TARGET_MODULE_LPSPI1_TRG, \ + TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \ +} + +/* ISELED Pins */ + +#define ISELED_PIN_0 0 /*PTA10*/ +#define ISELED_PIN_1 1 /*PTD0*/ +#define ISELED_PIN_2 2 /*PTD9*/ +#define ISELED_PIN_3 3 /*PTA11*/ +#define ISELED_PIN_4 4 /*PTD1*/ +#define ISELED_PIN_5 5 /*PTD8*/ +#define ISELED_PIN_6 6 /*PTA0*/ +#define ISELED_PIN_7 7 /*PTE15*/ +#define ISELED_PIN_8 8 /*PTA1*/ +#define ISELED_PIN_9 9 /*PTE16*/ +#define ISELED_PIN_10 10 /*PTA2*/ +#define ISELED_PIN_11 11 /*PTD2*/ +#define ISELED_PIN_12 12 /*PTE10*/ +#define ISELED_PIN_13 13 /*PTA3*/ +#define ISELED_PIN_14 14 /*PTE11*/ +#define ISELED_PIN_15 15 /*PTD3*/ +#define ISELED_PIN_16 16 /*PTA8*/ +#define ISELED_PIN_17 17 /*PTE3*/ +#define ISELED_PIN_18 18 /*PTA9*/ +#define ISELED_PIN_19 19 /*PTE3*/ + +#define ISELED_PIN_20 20 /*PTB2*/ +#define ISELED_PIN_21 21 /*PTB1*/ +#define ISELED_PIN_22 22 /*PTD15*/ +#define ISELED_PIN_23 23 /*PTB4*/ +#define ISELED_PIN_24 24 /*PTE0*/ +#define ISELED_PIN_25 25 /*PTE2*/ +#define ISELED_PIN_26 26 /*PTD0*/ +#define ISELED_PIN_27 27 /*PTD2*/ +#define ISELED_PIN_28 28 /*PTB14*/ +#define ISELED_PIN_29 29 /*PTB16*/ +#define ISELED_PIN_30 30 /*PTE15*/ +#define ISELED_PIN_31 31 /*PTA8*/ +#define ISELED_PIN_32 32 /*PTC15*/ +#define ISELED_PIN_33 33 /*PTC1*/ + +#define ISELED_PIN_34 34 /*PTE1*/ +#define ISELED_PIN_35 35 /*PTB3*/ +#define ISELED_PIN_36 36 /*PTD16*/ +#define ISELED_PIN_37 37 /*PTB15*/ +#define ISELED_PIN_38 38 /*PTD1*/ +#define ISELED_PIN_39 39 /*PTC0*/ + + +#define MAX_NR_OF_STRIPS 13U + +/* PDB module features */ + +/* @brief PDB has back-to-back at instance level */ +#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK (1) + +#endif /* S32K144_FEATURES_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/devassert.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/devassert.h new file mode 100644 index 00000000..243c8d45 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/devassert.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DEVASSERT_H +#define DEVASSERT_H + +#include + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. + * The macro is defined to be used by drivers to validate input parameters and can be disabled. + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined. + * The macros are used to validate input parameters to driver functions. + * + */ + +/** +\page Error_detection_and_reporting Error detection and reporting + +S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing +a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on +runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important +to use this mechanism during development. + +The validation is performed by using DEV_ASSERT macro. +A default implementation of this macro is provided in this file. However, application developers can provide their own +implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the +project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h") + +The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol: + - When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation + performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is + prevented (application spins in an infinite loop) + This configuration is recommended for development environments, as it prevents further execution and allows investigating + potential problems from the point of error detection. + - When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations. + This configuration can be used to eliminate the overhead of development-time checks. + +It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to +disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks +in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point +to the file containing the custom implementation. +*/ + +#if defined (CUSTOM_DEVASSERT) + /* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */ + #include CUSTOM_DEVASSERT +#elif defined (DEV_ERROR_DETECT) + /* Implement default assert macro */ +static inline void DevAssert(volatile bool x) +{ + if(x) { } else { BKPT_ASM; for(;;) {} } +} + #define DEV_ASSERT(x) DevAssert(x) +#else + /* Assert macro does nothing */ + #define DEV_ASSERT(x) ((void)0) +#endif + +#endif /* DEVASSERT_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/device_registers.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/device_registers.h new file mode 100644 index 00000000..f56cf068 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/device_registers.h @@ -0,0 +1,70 @@ +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** All rights reserved. +** +** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +** THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** ################################################################### +*/ + +#ifndef DEVICE_REGISTERS_H +#define DEVICE_REGISTERS_H + +/** +* @page misra_violations MISRA-C:2012 violations +* +* @section [global] +* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced. +* The macro defines the device currently in use and may be used by components for specific checks. +* +*/ + + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ + +#if (defined(CPU_S32K144HFT0VLLT) || defined(CPU_S32K144LFT0MLLT)) + + #define S32K14x_SERIES + + /* Specific core definitions */ + #include "s32_core_cm4.h" + + #define S32K144_SERIES + + /* Register definitions */ + #include "S32K144.h" + /* CPU specific feature definitions */ + #include "S32K144_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#include "devassert.h" + +#endif /* DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/s32_core_cm4.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/s32_core_cm4.h new file mode 100644 index 00000000..acdd2628 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/s32_core_cm4.h @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + */ +/*! + * @file s32_core_cm4.h + * + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro + * Function-like macros are used instead of inline functions in order to ensure + * that the performance will not be decreased if the functions will not be + * inlined by the compiler. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced. + * The macros defined are used only on some of the drivers, so this might be reported + * when the analysis is made only on one driver. + */ + +/* + * Tool Chains: + * GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION: ARM Compiler + */ + +#if !defined (CORE_CM4_H) +#define CORE_CM4_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief BKPT_ASM + * + * Macro to be used to trigger an debug interrupt + */ +#define BKPT_ASM __asm("BKPT #0\n\t") + + +/** \brief Enable FPU + * + * ENABLE_FPU indicates whether SystemInit will enable the Floating point unit (FPU) + */ +#if defined (__GNUC__) || defined (__ARMCC_VERSION) +#if defined (__VFP_FP__) && !defined (__SOFTFP__) +#define ENABLE_FPU +#endif + +#elif defined (__ICCARM__) +#if defined __ARMVFP__ +#define ENABLE_FPU +#endif + +#elif defined (__ghs__) || defined (__DCC__) +#if defined (__VFP__) +#define ENABLE_FPU +#endif +#endif /* if defined (__GNUC__) */ + +/** \brief Enable interrupts + */ +#if defined (__GNUC__) +#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory"); +#else +#define ENABLE_INTERRUPTS() __asm("cpsie i") +#endif + + +/** \brief Disable interrupts + */ +#if defined (__GNUC__) +#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory"); +#else +#define DISABLE_INTERRUPTS() __asm("cpsid i") +#endif + + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#else +#define STANDBY() __asm("wfi") +#endif + +/** \brief No-op + */ +#define NOP() __asm volatile ("nop") + +/** \brief Reverse byte order in a word. + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Reverse byte order in each halfword independently. + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) +#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \ + | ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U)) +#endif + +/** \brief Places a function in RAM. + */ +#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION) + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram"))); +#elif defined ( __ghs__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far") + #define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\ + _Pragma("ghs callmode=default") +#elif defined ( __ICCARM__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#elif defined ( __DCC__ ) + #define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\"") \ + _Pragma("use_section CODE") + #define END_FUNCTION_DECLARATION_RAMSECTION ; \ + _Pragma("section CODE \".text\"") +#else + /* Keep compatibility with software analysis tools */ + #define START_FUNCTION_DECLARATION_RAMSECTION + #define END_FUNCTION_DECLARATION_RAMSECTION ; +#endif + + /* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when + defining a function, it is enough to specify it at the declaration. This + also enables compatibility with software analysis tools. */ + #define START_FUNCTION_DEFINITION_RAMSECTION + #define END_FUNCTION_DEFINITION_RAMSECTION + +#if defined (__ICCARM__) + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022") + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022") +#else + #define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL + #define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL +#endif + +/** \brief Get Core ID + * + * GET_CORE_ID returns the processor identification number for cm4 + */ +#define GET_CORE_ID() 0U + +/** \brief Data alignment. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define ALIGNED(x) __attribute__((aligned(x))) +#elif defined ( __ICCARM__ ) + #define stringify(s) tostring(s) + #define tostring(s) #s + #define ALIGNED(x) _Pragma(stringify(data_alignment=x)) +#else + /* Keep compatibility with software analysis tools */ + #define ALIGNED(x) +#endif + +/** \brief Section placement. + */ +#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION) + #define PLACE_IN_SECTION(x) __attribute__((section(x))) +#elif defined ( __ICCARM__ ) + #define PLACE_IN_SECTION(x) _Pragma(stringify(section=x)) +#else + /* Keep compatibility with software analysis tools */ + #define PLACE_IN_SECTION(x) +#endif + +/** \brief Endianness. + */ +#define CORE_LITTLE_ENDIAN + +#ifdef __cplusplus +} +#endif + +#endif /* CORE_CM4_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.c new file mode 100644 index 00000000..2d0efc61 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage + * is declared, its size should be explicitly specified. + * The size of the arrays can not be explicitly determined. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable + * code. + * The condition compares two address defined in linker files that can be different. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + * @section [global] + * Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed + * to return int. + * This is an e200 Power Architecture Assembly instruction used to retrieve + * the core number. + * + */ + +#include "startup.h" +#include + + +/******************************************************************************* + * Static Variables + ******************************************************************************/ +static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : init_data_bss + * Description : Make necessary initializations for RAM. + * - Copy the vector table from ROM to RAM. + * - Copy initialized data from ROM to RAM. + * - Copy code that should reside in RAM from ROM + * - Clear the zero-initialized data section. + * + * Tool Chains: + * __GNUC__ : GNU Compiler Collection + * __ghs__ : Green Hills ARM Compiler + * __ICCARM__ : IAR ARM Compiler + * __DCC__ : Wind River Diab Compiler + * __ARMCC_VERSION : ARMC Compiler + * + * Implements : init_data_bss_Activity + *END**************************************************************************/ +void init_data_bss(void) +{ + uint32_t n; + uint8_t coreId; +/* For ARMC we are using the library method of initializing DATA, Custom Section and + * Code RAM sections so the below variables are not needed */ +#if !defined(__ARMCC_VERSION) + /* Declare pointers for various data sections. These pointers + * are initialized using values pulled in from the linker file */ + uint8_t * data_ram; + uint8_t * code_ram; + uint8_t * bss_start; + uint8_t * custom_ram; + const uint8_t * data_rom, * data_rom_end; + const uint8_t * code_rom, * code_rom_end; + const uint8_t * bss_end; + const uint8_t * custom_rom, * custom_rom_end; +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ + +#if defined(__ARMCC_VERSION) + extern uint32_t __RAM_VECTOR_TABLE_SIZE; + extern uint32_t __VECTOR_ROM; + extern uint32_t __VECTOR_RAM; +#else + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#endif + /* Get section information from linker files */ +#if defined(__ICCARM__) + /* Data */ + data_ram = __section_begin(".data"); + data_rom = __section_begin(".data_init"); + data_rom_end = __section_end(".data_init"); + + /* CODE RAM */ + #pragma section = "__CODE_ROM" + #pragma section = "__CODE_RAM" + code_ram = __section_begin("__CODE_RAM"); + code_rom = __section_begin("__CODE_ROM"); + code_rom_end = __section_end("__CODE_ROM"); + + /* BSS */ + bss_start = __section_begin(".bss"); + bss_end = __section_end(".bss"); + + custom_ram = __section_begin(".customSection"); + custom_rom = __section_begin(".customSection_init"); + custom_rom_end = __section_end(".customSection_init"); + +#elif defined (__ARMCC_VERSION) + /* VECTOR TABLE*/ + uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE; + uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM; + uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM; +#else + extern uint32_t __DATA_ROM[]; + extern uint32_t __DATA_RAM[]; + extern uint32_t __DATA_END[]; + + extern uint32_t __CODE_RAM[]; + extern uint32_t __CODE_ROM[]; + extern uint32_t __CODE_END[]; + + extern uint32_t __BSS_START[]; + extern uint32_t __BSS_END[]; + + extern uint32_t __CUSTOM_ROM[]; + extern uint32_t __CUSTOM_END[]; + + /* Data */ + data_ram = (uint8_t *)__DATA_RAM; + data_rom = (uint8_t *)__DATA_ROM; + data_rom_end = (uint8_t *)__DATA_END; + /* CODE RAM */ + code_ram = (uint8_t *)__CODE_RAM; + code_rom = (uint8_t *)__CODE_ROM; + code_rom_end = (uint8_t *)__CODE_END; + /* BSS */ + bss_start = (uint8_t *)__BSS_START; + bss_end = (uint8_t *)__BSS_END; + + /* Custom section */ + custom_ram = CUSTOMSECTION_SECTION_START; + custom_rom = (uint8_t *)__CUSTOM_ROM; + custom_rom_end = (uint8_t *)__CUSTOM_END; + +#endif + +#if !defined(__ARMCC_VERSION) + /* Copy initialized data from ROM to RAM */ + while (data_rom_end != data_rom) + { + *data_ram = *data_rom; + data_ram++; + data_rom++; + } + + /* Copy functions from ROM to RAM */ + while (code_rom_end != code_rom) + { + *code_ram = *code_rom; + code_ram++; + code_rom++; + } + + /* Clear the zero-initialized data section */ + while(bss_end != bss_start) + { + *bss_start = 0; + bss_start++; + } + + /* Copy customsection rom to ram */ + while(custom_rom_end != custom_rom) + { + *custom_ram = *custom_rom; + custom_rom++; + custom_ram++; + } +#endif + coreId = (uint8_t)GET_CORE_ID(); +#if defined (__ARMCC_VERSION) + /* Copy the vector table from ROM to RAM */ + /* Workaround */ + for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++) + { + vector_ram[n] = vector_rom[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t) __VECTOR_RAM; +#else + /* Check if VECTOR_TABLE copy is needed */ + if (__VECTOR_RAM != __VECTOR_TABLE) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_RAM; + } + else + { + /* Point the VTOR to the position of vector table */ + *s_vectors[coreId] = (uint32_t)__VECTOR_TABLE; + } +#endif + +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.h new file mode 100644 index 00000000..8384b7db --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/startup.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef STARTUP_H +#define STARTUP_H + +#include +#include "device_registers.h" +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced. + * The defined macro is used as include guard. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * All variables with this problem are defined in the linker files. + * + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief define symbols that specific start and end addres of some basic sections. + */ +#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES) + #if (defined(__ICCARM__)) + #define INTERRUPTS_SECTION_START __section_begin(".intvec") + #define INTERRUPTS_SECTION_END __section_end(".intvec") + #define BSS_SECTION_START __section_begin(".bss") + #define BSS_SECTION_END __section_end(".bss") + #define DATA_SECTION_START __section_begin(".data") + #define DATA_SECTION_END __section_end(".data") + #define CUSTOMSECTION_SECTION_START __section_begin(".customSection") + #define CUSTOMSECTION_SECTION_END __section_end(".customSection") + #define CODE_RAM_SECTION_START __section_begin("__CODE_RAM") + #define CODE_RAM_SECTION_END __section_end("__CODE_RAM") + #define DATA_INIT_SECTION_START __section_begin(".data_init") + #define DATA_INIT_SECTION_END __section_end(".data_init") + #define CODE_ROM_SECTION_START __section_begin("__CODE_ROM") + #define CODE_ROM_SECTION_END __section_end("__CODE_ROM") + + #elif (defined(__ARMCC_VERSION)) + #define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START + #define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END + #define BSS_SECTION_START (uint8_t *)__BSS_START + #define BSS_SECTION_END (uint8_t *)__BSS_END + #define DATA_SECTION_START (uint8_t *)__DATA_RAM_START + #define DATA_SECTION_END (uint8_t *)__DATA_RAM_END + #define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START + #define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END + #define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START + #define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END + + extern uint32_t __VECTOR_ROM_START; + extern uint32_t __VECTOR_ROM_END; + extern uint32_t __BSS_START; + extern uint32_t __BSS_END; + extern uint32_t __DATA_RAM_START; + extern uint32_t __DATA_RAM_END; + extern uint32_t __CUSTOM_SECTION_START; + extern uint32_t __CUSTOM_SECTION_END; + extern uint32_t __CODE_RAM_START; + extern uint32_t __CODE_RAM_END; + #else + #define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__ + #define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__ + #define BSS_SECTION_START (uint8_t *)&__bss_start__ + #define BSS_SECTION_END (uint8_t *)&__bss_end__ + #define DATA_SECTION_START (uint8_t *)&__data_start__ + #define DATA_SECTION_END (uint8_t *)&__data_end__ + #define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__ + #define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__ + #define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__ + #define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__ + + extern uint32_t __interrupts_start__; + extern uint32_t __interrupts_end__; + extern uint32_t __bss_start__; + extern uint32_t __bss_end__; + extern uint32_t __data_start__; + extern uint32_t __data_end__; + extern uint32_t __customSection_start__; + extern uint32_t __customSection_end__; + extern uint32_t __code_ram_start__; + extern uint32_t __code_ram_end__; + #endif +#endif + +#if (defined(__ICCARM__)) + #pragma section = ".data" + #pragma section = ".data_init" + #pragma section = ".bss" + #pragma section = ".intvec" + #pragma section = ".customSection" + #pragma section = ".customSection_init" + #pragma section = "__CODE_RAM" + #pragma section = "__CODE_ROM" +#endif + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.c new file mode 100644 index 00000000..a8e32c84 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2015 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @page misra_violations MISRA-C:2012 violations + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block + * scope if its identifier only appears in a single function. + * An object with static storage duration declared at block scope cannot be + * accessed directly from outside the block. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed + * between a pointer to object and an integer type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed + * between pointer to void and an arithmetic type. + * The cast is required to initialize a pointer with an unsigned int define, + * representing an address. + * + * @section [global] + * Violates MISRA 2012 Advisory Rule 8.7, External could be made static. + * Function is defined for usage by application code. + * + */ + +#include "device_registers.h" +#include "system_S32K144.h" +#include "stdbool.h" + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/*FUNCTION********************************************************************** + * + * Function Name : SystemInit + * Description : This function disables the watchdog, enables FPU + * and the power mode protection if the corresponding feature macro + * is enabled. SystemInit is called from startup_device file. + * + * Implements : SystemInit_Activity + *END**************************************************************************/ +void SystemInit(void) +{ +/**************************************************************************/ + /* FPU ENABLE*/ +/**************************************************************************/ +#ifdef ENABLE_FPU + /* Enable CP10 and CP11 coprocessors */ + S32_SCB->CPACR |= (S32_SCB_CPACR_CP10_MASK | S32_SCB_CPACR_CP11_MASK); +#ifdef ERRATA_E6940 + /* Disable lazy context save of floating point state by clearing LSPEN bit + * Workaround for errata e6940 */ + S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK); +#endif +#endif /* ENABLE_FPU */ + +/**************************************************************************/ + /* WDOG DISABLE*/ +/**************************************************************************/ + +#if (DISABLE_WDOG) + /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/ + WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE; + /* The dummy read is used in order to make sure that the WDOG registers will be configured only + * after the write of the unlock value was completed. */ + (void)WDOG->CNT; + + /* Initial write of WDOG configuration register: + * enables support for 32-bit refresh/unlock command write words, + * clock select from LPO, update enable, watchdog disabled */ + WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) | + (FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) | + (0U << WDOG_CS_EN_SHIFT) | + (1U << WDOG_CS_UPDATE_SHIFT) ); + + /* Configure timeout */ + WDOG->TOVAL = (uint32_t )0xFFFF; +#endif /* (DISABLE_WDOG) */ + +/**************************************************************************/ + /* ENABLE CACHE */ +/**************************************************************************/ +#if defined(I_CACHE) && (ICACHE_ENABLE == 1) + /* Invalidate and enable code cache */ + LMEM->PCCCR = LMEM_PCCCR_INVW0(1) | LMEM_PCCCR_INVW1(1) | LMEM_PCCCR_GO(1) | LMEM_PCCCR_ENCACHE(1); +#endif /* defined(I_CACHE) && (ICACHE_ENABLE == 1) */ +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemCoreClockUpdate + * Description : This function must be called whenever the core clock is changed + * during program execution. It evaluates the clock register settings and calculates + * the current core clock. + * + * Implements : SystemCoreClockUpdate_Activity + *END**************************************************************************/ +void SystemCoreClockUpdate(void) +{ + uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */ + uint32_t regValue; /* Temporary variable */ + uint32_t divider, prediv, multi; + bool validSystemClockSource = true; + static const uint32_t fircFreq[] = { + FEATURE_SCG_FIRC_FREQ0, + }; + + divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U; + + switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) { + case 0x1: + /* System OSC */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + break; + case 0x2: + /* Slow IRC */ + regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT; + + if (regValue != 0U) + { + SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ; + } + + break; + case 0x3: + /* Fast IRC */ + regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT; + SCGOUTClock= fircFreq[regValue]; + break; + case 0x6: + /* System PLL */ + SCGOUTClock = CPU_XTAL_CLK_HZ; + prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U; + multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U; + SCGOUTClock = SCGOUTClock * multi / (prediv * 2U); + break; + default: + validSystemClockSource = false; + break; + } + + if (validSystemClockSource == true) { + SystemCoreClock = (SCGOUTClock / divider); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : SystemSoftwareReset + * Description : This function is used to initiate a system reset + * + * Implements : SystemSoftwareReset_Activity + *END**************************************************************************/ +void SystemSoftwareReset(void) +{ + uint32_t regValue; + + /* Read Application Interrupt and Reset Control Register */ + regValue = S32_SCB->AIRCR; + + /* Clear register key */ + regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK); + + /* Configure System reset request bit and Register Key */ + regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY); + regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u); + + /* Write computed register value */ + S32_SCB->AIRCR = regValue; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.h new file mode 100644 index 00000000..c7fcf0a7 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/lib/system_S32K144.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2015 Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/*! @addtogroup soc_support_S32K144*/ +/*! @{*/ + +/*! + * @file system_S32K144.h + * @brief Device specific configuration file for S32K144 + */ + +#ifndef SYSTEM_S32K144_H_ +#define SYSTEM_S32K144_H_ /**< Symbol preventing repeated inclusion */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/****************************************************************************** + * CPU Settings. + *****************************************************************************/ + +/* Watchdog disable */ +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Cache enablement */ +#ifndef ICACHE_ENABLE +#define ICACHE_ENABLE 0 +#endif + +/* Value of the external crystal or oscillator clock frequency in Hz */ +#ifndef CPU_XTAL_CLK_HZ + #define CPU_XTAL_CLK_HZ 8000000u +#endif + +/* Value of the fast internal oscillator clock frequency in Hz */ +#ifndef CPU_INT_FAST_CLK_HZ + #define CPU_INT_FAST_CLK_HZ 48000000u +#endif + +/* Default System clock value */ +#ifndef DEFAULT_SYSTEM_CLOCK + #define DEFAULT_SYSTEM_CLOCK 48000000u +#endif + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the SoC. + * + * This function disables the watchdog, enables FPU. + * if the corresponding feature macro is enabled. + * SystemInit is called from startup_device file. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + * This function must be called when user does not want to use clock manager component. + * If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK + * parameter. + * + */ +void SystemCoreClockUpdate(void); + +/** + * @brief Initiates a system reset. + * + * This function is used to initiate a system reset + */ +void SystemSoftwareReset(void); + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif /* #if !defined(SYSTEM_S32K144_H_) */ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c new file mode 100644 index 00000000..4c58110c --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c @@ -0,0 +1,204 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/main.c +* \brief Demo program application source file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +static void Init(void); +static void SystemClockConfig(void); + + +/************************************************************************************//** +** \brief This is the entry point for the bootloader application and is called +** by the reset interrupt vector after the C-startup routines executed. +** \return none. +** +****************************************************************************************/ +void main(void) +{ + /* Initialize the microcontroller. */ + Init(); + /* Initialize the bootloader interface */ + BootComInit(); + + /* Start the infinite program loop. */ + while (1) + { + /* Toggle LED with a fixed frequency. */ + LedToggle(); + /* Check for bootloader activation request */ + BootComCheckActivationRequest(); + } +} /*** end of main ***/ + + +/************************************************************************************//** +** \brief Initializes the microcontroller. +** \return none. +** +****************************************************************************************/ +static void Init(void) +{ + /* Configure the system clock. */ + SystemClockConfig(); + /* Enable the peripheral clock for the ports that are used. */ + PCC->PCCn[PCC_PORTC_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK; +#if (BOOT_COM_RS232_ENABLE > 0) + /* UART RX GPIO pin configuration. PC6 = UART1 RX, MUX = ALT2. */ + PORTC->PCR[6] |= PORT_PCR_MUX(2); + /* UART TX GPIO pin configuration. PC7 = UART1 TX, MUX = ALT2. */ + PORTC->PCR[7] |= PORT_PCR_MUX(2); +#endif +#if (BOOT_COM_CAN_ENABLE > 0) + /* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */ + PORTE->PCR[4] |= PORT_PCR_MUX(5); + /* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */ + PORTE->PCR[5] |= PORT_PCR_MUX(5); +#endif + + /* Initialize the timer driver. */ + TimerInit(); + /* Initialize the led driver. */ + LedInit(); + /* Enable the global interrupts. */ + ENABLE_INTERRUPTS(); +} /*** end of Init ***/ + + +/************************************************************************************//** +** \brief System Clock Configuration. This code was derived from a S32 Design Studio +** example program. It uses the 8 MHz external crystal as a source for the +** PLL and configures the normal RUN mode for the following clock settings: +** - SPLL_CLK = 160 MHz +** - CORE_CLK = 80 MHz +** - SYS_CLK = 80 MHz +** - BUS_CLK = 40 MHz +** - FLASH_CLK = 26.67 MHz +** - SIRCDIV1_CLK = 8 MHz +** - SIRCDIV2_CLK = 8 MHz +** \return none. +** +****************************************************************************************/ +static void SystemClockConfig(void) +{ + /* --------- SOSC Initialization (8 MHz) ------------------------------------------- */ + /* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */ + SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1); + /* Range=2: Medium freq (SOSC betw 1MHz-8MHz). + * HGO=0: Config xtal osc for low power. + * EREFS=1: Input is external XTAL. + */ + SCG->SOSCCFG = SCG_SOSCCFG_RANGE(2) | SCG_SOSCCFG_EREFS_MASK; + /* Ensure SOSCCSR unlocked. */ + while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK) + { + ; + } + /* LK=0: SOSCCSR can be written. + * SOSCCMRE=0: OSC CLK monitor IRQ if enabled. + * SOSCCM=0: OSC CLK monitor disabled. + * SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled. + * SOSCLPEN=0: Sys OSC disabled in VLP modes. + * SOSCSTEN=0: Sys OSC disabled in Stop modes. + * SOSCEN=1: Enable oscillator. + */ + SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK; + /* Wait for system OSC clock to become valid. */ + while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)) + { + ; + } + + /* --------- SPLL Initialization (160 MHz) ----------------------------------------- */ + /* Ensure SPLLCSR is unlocked. */ + while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK) + { + ; + } + /* SPLLEN=0: SPLL is disabled (default). */ + SCG->SPLLCSR &= ~SCG_SPLLCSR_SPLLEN_MASK; + /* SPLLDIV1 divide by 2 and SPLLDIV2 divide by 4. */ + SCG->SPLLDIV |= SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(3); + /* PREDIV=0: Divide SOSC_CLK by 0+1=1. + * MULT=24: Multiply sys pll by 4+24=40. + * SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz. + */ + SCG->SPLLCFG = SCG_SPLLCFG_MULT(24); + /* Ensure SPLLCSR is unlocked. */ + while (SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK) + { + ; + } + /* LK=0: SPLLCSR can be written. + * SPLLCMRE=0: SPLL CLK monitor IRQ if enabled. + * SPLLCM=0: SPLL CLK monitor disabled. + * SPLLSTEN=0: SPLL disabled in Stop modes. + * SPLLEN=1: Enable SPLL. + */ + SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK; + /* Wait for SPLL to become valid. */ + while (!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)) + { + ; + } + + /* --------- SIRC Initialization --------------------------------------------------- */ + /* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and + * SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source. + */ + SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1); + + /* --------- Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL ------------------ */ + /* Select PLL as clock source. + * DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz. + * DIVBUS=1, div. by 2: bus clock = 40 MHz. + * DIVSLOW=2, div. by 2: SCG slow, flash clock= 26 2/3 MHz. + */ + SCG->RCCR= SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) | + SCG_RCCR_DIVSLOW(2); + /* Wait until system clock source is SPLL. */ + while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6U) + { + ; + } + /* Evaluate the clock register settings and calculates the current core clock. This + * function must be called when the clock manager component is not used. + */ + SystemCoreClockUpdate(); +} /*** end of SystemClockConfig ***/ + + +/*********************************** end of main.c *************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/prog.dox b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/prog.dox new file mode 100644 index 00000000..5400cbb6 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/prog.dox @@ -0,0 +1,13 @@ +/** +\defgroup Prog_ARMCM4_S32K14_S32K144EVB_IAR User Program +\ingroup ARMCM4_S32K14_S32K144EVB_IAR +\brief User Program. +\details The intention of the demo user program is two-fold. (1) To test the + bootloader, you need some sort of firmware to see if you can perform a + firmware update with the bootloader. This program can be used for this + purpose. (2) To make firmware programmable by the bootloader, a few + adjustments to the firmware are required. The demo user program serves as an + example for how these adjustments can be implemented. This demo user program + is a template that can be used as a starting point for creating your own + demo user program. +*/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/startup_S32K144.s b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/startup_S32K144.s new file mode 100644 index 00000000..cf4c4ff5 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/startup_S32K144.s @@ -0,0 +1,693 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_S32K144.s +; @purpose: IAR Startup File +; S32K144 +; @version: 2.0 +; @date: 2017-1-10 +; @build: b170107 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; Copyright 2016-2017 NXP +; All rights reserved. +; +; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR +; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN main + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete + DCD DMA8_IRQHandler ;DMA channel 8 transfer complete + DCD DMA9_IRQHandler ;DMA channel 9 transfer complete + DCD DMA10_IRQHandler ;DMA channel 10 transfer complete + DCD DMA11_IRQHandler ;DMA channel 11 transfer complete + DCD DMA12_IRQHandler ;DMA channel 12 transfer complete + DCD DMA13_IRQHandler ;DMA channel 13 transfer complete + DCD DMA14_IRQHandler ;DMA channel 14 transfer complete + DCD DMA15_IRQHandler ;DMA channel 15 transfer complete + DCD DMA_Error_IRQHandler ;DMA error interrupt channels 0-15 + DCD MCM_IRQHandler ;FPU sources + DCD FTFC_IRQHandler ;FTFC Command complete + DCD Read_Collision_IRQHandler ;FTFC Read collision + DCD LVD_LVW_IRQHandler ;PMC Low voltage detect interrupt + DCD FTFC_Fault_IRQHandler ;FTFC Double bit fault detect + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM + DCD RCM_IRQHandler ;RCM Asynchronous Interrupt + DCD LPI2C0_Master_IRQHandler ;LPI2C0 Master Interrupt + DCD LPI2C0_Slave_IRQHandler ;LPI2C0 Slave Interrupt + DCD LPSPI0_IRQHandler ;LPSPI0 Interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 Interrupt + DCD LPSPI2_IRQHandler ;LPSPI2 Interrupt + DCD Reserved45_IRQHandler ;Reserved Interrupt 45 + DCD Reserved46_IRQHandler ;Reserved Interrupt 46 + DCD LPUART0_RxTx_IRQHandler ;LPUART0 Transmit / Receive Interrupt + DCD Reserved48_IRQHandler ;Reserved Interrupt 48 + DCD LPUART1_RxTx_IRQHandler ;LPUART1 Transmit / Receive Interrupt + DCD Reserved50_IRQHandler ;Reserved Interrupt 50 + DCD LPUART2_RxTx_IRQHandler ;LPUART2 Transmit / Receive Interrupt + DCD Reserved52_IRQHandler ;Reserved Interrupt 52 + DCD Reserved53_IRQHandler ;Reserved Interrupt 53 + DCD Reserved54_IRQHandler ;Reserved Interrupt 54 + DCD ADC0_IRQHandler ;ADC0 interrupt request. + DCD ADC1_IRQHandler ;ADC1 interrupt request. + DCD CMP0_IRQHandler ;CMP0 interrupt request + DCD Reserved58_IRQHandler ;Reserved Interrupt 58 + DCD Reserved59_IRQHandler ;Reserved Interrupt 59 + DCD ERM_single_fault_IRQHandler ;ERM single bit error correction + DCD ERM_double_fault_IRQHandler ;ERM double bit error non-correctable + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD LPIT0_Ch0_IRQHandler ;LPIT0 channel 0 overflow interrupt + DCD LPIT0_Ch1_IRQHandler ;LPIT0 channel 1 overflow interrupt + DCD LPIT0_Ch2_IRQHandler ;LPIT0 channel 2 overflow interrupt + DCD LPIT0_Ch3_IRQHandler ;LPIT0 channel 3 overflow interrupt + DCD PDB0_IRQHandler ;PDB0 interrupt + DCD Reserved69_IRQHandler ;Reserved Interrupt 69 + DCD Reserved70_IRQHandler ;Reserved Interrupt 70 + DCD Reserved71_IRQHandler ;Reserved Interrupt 71 + DCD Reserved72_IRQHandler ;Reserved Interrupt 72 + DCD SCG_IRQHandler ;SCG bus interrupt request + DCD LPTMR0_IRQHandler ;LPTIMER interrupt request + DCD PORTA_IRQHandler ;Port A pin detect interrupt + DCD PORTB_IRQHandler ;Port B pin detect interrupt + DCD PORTC_IRQHandler ;Port C pin detect interrupt + DCD PORTD_IRQHandler ;Port D pin detect interrupt + DCD PORTE_IRQHandler ;Port E pin detect interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD Reserved81_IRQHandler ;Reserved Interrupt 81 + DCD Reserved82_IRQHandler ;Reserved Interrupt 82 + DCD Reserved83_IRQHandler ;Reserved Interrupt 83 + DCD PDB1_IRQHandler ;PDB1 interrupt + DCD FLEXIO_IRQHandler ;FlexIO Interrupt + DCD Reserved86_IRQHandler ;Reserved Interrupt 86 + DCD Reserved87_IRQHandler ;Reserved Interrupt 87 + DCD Reserved88_IRQHandler ;Reserved Interrupt 88 + DCD Reserved89_IRQHandler ;Reserved Interrupt 89 + DCD Reserved90_IRQHandler ;Reserved Interrupt 90 + DCD Reserved91_IRQHandler ;Reserved Interrupt 91 + DCD Reserved92_IRQHandler ;Reserved Interrupt 92 + DCD Reserved93_IRQHandler ;Reserved Interrupt 93 + DCD CAN0_ORed_IRQHandler ;CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN0_Error_IRQHandler ;CAN0 Interrupt indicating that errors were detected on the CAN bus + DCD CAN0_Wake_Up_IRQHandler ;CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode + DCD CAN0_ORed_0_15_MB_IRQHandler ;CAN0 OR'ed Message buffer (0-15) + DCD CAN0_ORed_16_31_MB_IRQHandler ;CAN0 OR'ed Message buffer (16-31) + DCD Reserved99_IRQHandler ;Reserved Interrupt 99 + DCD Reserved100_IRQHandler ;Reserved Interrupt 100 + DCD CAN1_ORed_IRQHandler ;CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN1_Error_IRQHandler ;CAN1 Interrupt indicating that errors were detected on the CAN bus + DCD Reserved103_IRQHandler ;Reserved Interrupt 103 + DCD CAN1_ORed_0_15_MB_IRQHandler ;CAN1 OR'ed Interrupt for Message buffer (0-15) + DCD Reserved105_IRQHandler ;Reserved Interrupt 105 + DCD Reserved106_IRQHandler ;Reserved Interrupt 106 + DCD Reserved107_IRQHandler ;Reserved Interrupt 107 + DCD CAN2_ORed_IRQHandler ;CAN2 OR'ed [Bus Off OR Transmit Warning OR Receive Warning] + DCD CAN2_Error_IRQHandler ;CAN2 Interrupt indicating that errors were detected on the CAN bus + DCD Reserved110_IRQHandler ;Reserved Interrupt 110 + DCD CAN2_ORed_0_15_MB_IRQHandler ;CAN2 OR'ed Message buffer (0-15) + DCD Reserved112_IRQHandler ;Reserved Interrupt 112 + DCD Reserved113_IRQHandler ;Reserved Interrupt 113 + DCD Reserved114_IRQHandler ;Reserved Interrupt 114 + DCD FTM0_Ch0_Ch1_IRQHandler ;FTM0 Channel 0 and 1 interrupt + DCD FTM0_Ch2_Ch3_IRQHandler ;FTM0 Channel 2 and 3 interrupt + DCD FTM0_Ch4_Ch5_IRQHandler ;FTM0 Channel 4 and 5 interrupt + DCD FTM0_Ch6_Ch7_IRQHandler ;FTM0 Channel 6 and 7 interrupt + DCD FTM0_Fault_IRQHandler ;FTM0 Fault interrupt + DCD FTM0_Ovf_Reload_IRQHandler ;FTM0 Counter overflow and Reload interrupt + DCD FTM1_Ch0_Ch1_IRQHandler ;FTM1 Channel 0 and 1 interrupt + DCD FTM1_Ch2_Ch3_IRQHandler ;FTM1 Channel 2 and 3 interrupt + DCD FTM1_Ch4_Ch5_IRQHandler ;FTM1 Channel 4 and 5 interrupt + DCD FTM1_Ch6_Ch7_IRQHandler ;FTM1 Channel 6 and 7 interrupt + DCD FTM1_Fault_IRQHandler ;FTM1 Fault interrupt + DCD FTM1_Ovf_Reload_IRQHandler ;FTM1 Counter overflow and Reload interrupt + DCD FTM2_Ch0_Ch1_IRQHandler ;FTM2 Channel 0 and 1 interrupt + DCD FTM2_Ch2_Ch3_IRQHandler ;FTM2 Channel 2 and 3 interrupt + DCD FTM2_Ch4_Ch5_IRQHandler ;FTM2 Channel 4 and 5 interrupt + DCD FTM2_Ch6_Ch7_IRQHandler ;FTM2 Channel 6 and 7 interrupt + DCD FTM2_Fault_IRQHandler ;FTM2 Fault interrupt + DCD FTM2_Ovf_Reload_IRQHandler ;FTM2 Counter overflow and Reload interrupt + DCD FTM3_Ch0_Ch1_IRQHandler ;FTM3 Channel 0 and 1 interrupt + DCD FTM3_Ch2_Ch3_IRQHandler ;FTM3 Channel 2 and 3 interrupt + DCD FTM3_Ch4_Ch5_IRQHandler ;FTM3 Channel 4 and 5 interrupt + DCD FTM3_Ch6_Ch7_IRQHandler ;FTM3 Channel 6 and 7 interrupt + DCD FTM3_Fault_IRQHandler ;FTM3 Fault interrupt + DCD FTM3_Ovf_Reload_IRQHandler ;FTM3 Counter overflow and Reload interrupt + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD 0x55AA11EE ;254 Reserved for OpenBLT checksum + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key + DCD 0xFFFFFFFF ; + DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes + DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + ;; Init the rest of the registers + LDR R1,=0 + LDR R2,=0 + LDR R3,=0 + LDR R4,=0 + LDR R5,=0 + LDR R6,=0 + LDR R7,=0 + MOV R8,R7 + MOV R9,R7 + MOV R10,R7 + MOV R11,R7 + MOV R12,R7 + +#ifdef START_FROM_FLASH + IMPORT __RAM_START, __RAM_END + ;; INIT ECC RAM + + LDR R1, =__RAM_START + LDR R2, =__RAM_END + + SUBS R2, R2, R1 + SUBS R2, #1 + BLE .LC5 + + MOVS R0, #0 + MOVS R3, #4 + .LC4: + STR R0, [R1] + ADD R1, R1, R3 + SUBS R2, #4 + BGE .LC4 + .LC5: +#endif + ;; Initialize the stack pointer + LDR R0, =sfe(CSTACK) + MOV R13,R0 + +#ifndef __NO_SYSTEM_INIT + ;; Call the CMSIS system init routine + LDR R0, =SystemInit + BLX R0 +#endif + + ;; Init .data and .bss sections + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + + BL main +JumpToSelf + B JumpToSelf + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA_Error_IRQHandler + PUBWEAK MCM_IRQHandler + PUBWEAK FTFC_IRQHandler + PUBWEAK Read_Collision_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK FTFC_Fault_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RCM_IRQHandler + PUBWEAK LPI2C0_Master_IRQHandler + PUBWEAK LPI2C0_Slave_IRQHandler + PUBWEAK LPSPI0_IRQHandler + PUBWEAK LPSPI1_IRQHandler + PUBWEAK LPSPI2_IRQHandler + PUBWEAK Reserved45_IRQHandler + PUBWEAK Reserved46_IRQHandler + PUBWEAK LPUART0_RxTx_IRQHandler + PUBWEAK Reserved48_IRQHandler + PUBWEAK LPUART1_RxTx_IRQHandler + PUBWEAK Reserved50_IRQHandler + PUBWEAK LPUART2_RxTx_IRQHandler + PUBWEAK Reserved52_IRQHandler + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved54_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK Reserved58_IRQHandler + PUBWEAK Reserved59_IRQHandler + PUBWEAK ERM_single_fault_IRQHandler + PUBWEAK ERM_double_fault_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK LPIT0_Ch0_IRQHandler + PUBWEAK LPIT0_Ch1_IRQHandler + PUBWEAK LPIT0_Ch2_IRQHandler + PUBWEAK LPIT0_Ch3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK Reserved69_IRQHandler + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK Reserved72_IRQHandler + PUBWEAK SCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK Reserved81_IRQHandler + PUBWEAK Reserved82_IRQHandler + PUBWEAK Reserved83_IRQHandler + PUBWEAK PDB1_IRQHandler + PUBWEAK FLEXIO_IRQHandler + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved87_IRQHandler + PUBWEAK Reserved88_IRQHandler + PUBWEAK Reserved89_IRQHandler + PUBWEAK Reserved90_IRQHandler + PUBWEAK Reserved91_IRQHandler + PUBWEAK Reserved92_IRQHandler + PUBWEAK Reserved93_IRQHandler + PUBWEAK CAN0_ORed_IRQHandler + PUBWEAK CAN0_Error_IRQHandler + PUBWEAK CAN0_Wake_Up_IRQHandler + PUBWEAK CAN0_ORed_0_15_MB_IRQHandler + PUBWEAK CAN0_ORed_16_31_MB_IRQHandler + PUBWEAK Reserved99_IRQHandler + PUBWEAK Reserved100_IRQHandler + PUBWEAK CAN1_ORed_IRQHandler + PUBWEAK CAN1_Error_IRQHandler + PUBWEAK Reserved103_IRQHandler + PUBWEAK CAN1_ORed_0_15_MB_IRQHandler + PUBWEAK Reserved105_IRQHandler + PUBWEAK Reserved106_IRQHandler + PUBWEAK Reserved107_IRQHandler + PUBWEAK CAN2_ORed_IRQHandler + PUBWEAK CAN2_Error_IRQHandler + PUBWEAK Reserved110_IRQHandler + PUBWEAK CAN2_ORed_0_15_MB_IRQHandler + PUBWEAK Reserved112_IRQHandler + PUBWEAK Reserved113_IRQHandler + PUBWEAK Reserved114_IRQHandler + PUBWEAK FTM0_Ch0_Ch1_IRQHandler + PUBWEAK FTM0_Ch2_Ch3_IRQHandler + PUBWEAK FTM0_Ch4_Ch5_IRQHandler + PUBWEAK FTM0_Ch6_Ch7_IRQHandler + PUBWEAK FTM0_Fault_IRQHandler + PUBWEAK FTM0_Ovf_Reload_IRQHandler + PUBWEAK FTM1_Ch0_Ch1_IRQHandler + PUBWEAK FTM1_Ch2_Ch3_IRQHandler + PUBWEAK FTM1_Ch4_Ch5_IRQHandler + PUBWEAK FTM1_Ch6_Ch7_IRQHandler + PUBWEAK FTM1_Fault_IRQHandler + PUBWEAK FTM1_Ovf_Reload_IRQHandler + PUBWEAK FTM2_Ch0_Ch1_IRQHandler + PUBWEAK FTM2_Ch2_Ch3_IRQHandler + PUBWEAK FTM2_Ch4_Ch5_IRQHandler + PUBWEAK FTM2_Ch6_Ch7_IRQHandler + PUBWEAK FTM2_Fault_IRQHandler + PUBWEAK FTM2_Ovf_Reload_IRQHandler + PUBWEAK FTM3_Ch0_Ch1_IRQHandler + PUBWEAK FTM3_Ch2_Ch3_IRQHandler + PUBWEAK FTM3_Ch4_Ch5_IRQHandler + PUBWEAK FTM3_Ch6_Ch7_IRQHandler + PUBWEAK FTM3_Fault_IRQHandler + PUBWEAK FTM3_Ovf_Reload_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +DMA4_IRQHandler +DMA5_IRQHandler +DMA6_IRQHandler +DMA7_IRQHandler +DMA8_IRQHandler +DMA9_IRQHandler +DMA10_IRQHandler +DMA11_IRQHandler +DMA12_IRQHandler +DMA13_IRQHandler +DMA14_IRQHandler +DMA15_IRQHandler +DMA_Error_IRQHandler +MCM_IRQHandler +FTFC_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +FTFC_Fault_IRQHandler +WDOG_EWM_IRQHandler +RCM_IRQHandler +LPI2C0_Master_IRQHandler +LPI2C0_Slave_IRQHandler +LPSPI0_IRQHandler +LPSPI1_IRQHandler +LPSPI2_IRQHandler +Reserved45_IRQHandler +Reserved46_IRQHandler +LPUART0_RxTx_IRQHandler +Reserved48_IRQHandler +LPUART1_RxTx_IRQHandler +Reserved50_IRQHandler +LPUART2_RxTx_IRQHandler +Reserved52_IRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +CMP0_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +ERM_single_fault_IRQHandler +ERM_double_fault_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +LPIT0_Ch0_IRQHandler +LPIT0_Ch1_IRQHandler +LPIT0_Ch2_IRQHandler +LPIT0_Ch3_IRQHandler +PDB0_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +SCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +Reserved81_IRQHandler +Reserved82_IRQHandler +Reserved83_IRQHandler +PDB1_IRQHandler +FLEXIO_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +Reserved88_IRQHandler +Reserved89_IRQHandler +Reserved90_IRQHandler +Reserved91_IRQHandler +Reserved92_IRQHandler +Reserved93_IRQHandler +CAN0_ORed_IRQHandler +CAN0_Error_IRQHandler +CAN0_Wake_Up_IRQHandler +CAN0_ORed_0_15_MB_IRQHandler +CAN0_ORed_16_31_MB_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +CAN1_ORed_IRQHandler +CAN1_Error_IRQHandler +Reserved103_IRQHandler +CAN1_ORed_0_15_MB_IRQHandler +Reserved105_IRQHandler +Reserved106_IRQHandler +Reserved107_IRQHandler +CAN2_ORed_IRQHandler +CAN2_Error_IRQHandler +Reserved110_IRQHandler +CAN2_ORed_0_15_MB_IRQHandler +Reserved112_IRQHandler +Reserved113_IRQHandler +Reserved114_IRQHandler +FTM0_Ch0_Ch1_IRQHandler +FTM0_Ch2_Ch3_IRQHandler +FTM0_Ch4_Ch5_IRQHandler +FTM0_Ch6_Ch7_IRQHandler +FTM0_Fault_IRQHandler +FTM0_Ovf_Reload_IRQHandler +FTM1_Ch0_Ch1_IRQHandler +FTM1_Ch2_Ch3_IRQHandler +FTM1_Ch4_Ch5_IRQHandler +FTM1_Ch6_Ch7_IRQHandler +FTM1_Fault_IRQHandler +FTM1_Ovf_Reload_IRQHandler +FTM2_Ch0_Ch1_IRQHandler +FTM2_Ch2_Ch3_IRQHandler +FTM2_Ch4_Ch5_IRQHandler +FTM2_Ch6_Ch7_IRQHandler +FTM2_Fault_IRQHandler +FTM2_Ovf_Reload_IRQHandler +FTM3_Ch0_Ch1_IRQHandler +FTM3_Ch2_Ch3_IRQHandler +FTM3_Ch4_Ch5_IRQHandler +FTM3_Ch6_Ch7_IRQHandler +FTM3_Fault_IRQHandler +FTM3_Ovf_Reload_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c new file mode 100644 index 00000000..6c79ae7c --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c @@ -0,0 +1,88 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.c +* \brief Timer driver source file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "header.h" /* generic header */ + + +/**************************************************************************************** +* Local data declarations +****************************************************************************************/ +/** \brief Local variable for storing the number of milliseconds that have elapsed since + * startup. + */ +static unsigned long millisecond_counter; + + +/************************************************************************************//** +** \brief Initializes the timer. +** \return none. +** +****************************************************************************************/ +void TimerInit(void) +{ + /* Configure the systick frequency as a 1 ms event generator. */ + S32_SysTick->RVR = (SystemCoreClock / 1000U) - 1U; + /* Reset the current counter value. */ + S32_SysTick->CVR = 0U; + /* Select core clock as source and enable the timer. */ + S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK | + S32_SysTick_CSR_TICKINT_MASK | + S32_SysTick_CSR_CLKSOURCE_MASK; + /* Reset the millisecond counter value. */ + millisecond_counter = 0U; +} /*** end of TimerInit ***/ + + +/************************************************************************************//** +** \brief Obtains the counter value of the millisecond timer. +** \return Current value of the millisecond timer. +** +****************************************************************************************/ +unsigned long TimerGet(void) +{ + /* Read and return the tick counter value. */ + return millisecond_counter; +} /*** end of TimerGet ***/ + + +/************************************************************************************//** +** \brief Interrupt service routine of the timer. +** \return none. +** +****************************************************************************************/ +void SysTick_Handler(void) +{ + /* Increment the millisecond counter. */ + millisecond_counter++; +} /*** end of SysTick_Handler ***/ + + +/*********************************** end of timer.c ************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h new file mode 100644 index 00000000..3e7a33a7 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h @@ -0,0 +1,38 @@ +/************************************************************************************//** +* \file Demo/ARMCM4_S32K14_S32K144EVB_IAR/Prog/timer.h +* \brief Timer driver header file. +* \ingroup Prog_ARMCM4_S32K14_S32K144EVB_IAR +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ +#ifndef TIMER_H +#define TIMER_H + +/**************************************************************************************** +* Function prototypes +****************************************************************************************/ +void TimerInit(void); +unsigned long TimerGet(void); + +#endif /* TIMER_H */ +/*********************************** end of timer.h ************************************/ diff --git a/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/demo.dox b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/demo.dox new file mode 100644 index 00000000..ac9a9108 --- /dev/null +++ b/Target/Demo/ARMCM4_S32K14_S32K144EVB_IAR/demo.dox @@ -0,0 +1,8 @@ +/** +\defgroup ARMCM4_S32K14_S32K144EVB_IAR Demo for S32K144EVB/IAR +\ingroup Demos +\brief Preconfigured programs for the NXP S32K144EVB board and the IAR Embedded + Workbench for ARM. +*/ + + diff --git a/Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c b/Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c new file mode 100644 index 00000000..07c03342 --- /dev/null +++ b/Target/Source/ARMCM4_S32K14/IAR/cpu_comp.c @@ -0,0 +1,59 @@ +/************************************************************************************//** +* \file Source/ARMCM4_S32K14/IAR/cpu_comp.c +* \brief Bootloader cpu module source file. +* \ingroup Target_ARMCM4_S32K14 +* \internal +*---------------------------------------------------------------------------------------- +* C O P Y R I G H T +*---------------------------------------------------------------------------------------- +* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved +* +*---------------------------------------------------------------------------------------- +* L I C E N S E +*---------------------------------------------------------------------------------------- +* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or +* modify it under the terms of the GNU General Public License as published by the Free +* Software Foundation, either version 3 of the License, or (at your option) any later +* version. +* +* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; +* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +* PURPOSE. See the GNU General Public License for more details. +* +* You have received a copy of the GNU General Public License along with OpenBLT. It +* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy. +* +* \endinternal +****************************************************************************************/ + +/**************************************************************************************** +* Include files +****************************************************************************************/ +#include "boot.h" /* bootloader generic header */ + + +/************************************************************************************//** +** \brief Disable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqDisable(void) +{ + /* Disable the global interrupts. */ + __asm("cpsie i"); +} /*** end of CpuIrqDisable ***/ + + +/************************************************************************************//** +** \brief Enable global interrupts. +** \return none. +** +****************************************************************************************/ +void CpuIrqEnable(void) +{ + /* Enable the global interrupts. */ + __asm("cpsie i"); +} /*** end of CpuIrqEnable ***/ + + +/*********************************** end of cpu_comp.c *********************************/ diff --git a/Target/Source/ARMCM4_S32K14/rs232.c b/Target/Source/ARMCM4_S32K14/rs232.c index 6d509d08..08487472 100644 --- a/Target/Source/ARMCM4_S32K14/rs232.c +++ b/Target/Source/ARMCM4_S32K14/rs232.c @@ -105,7 +105,7 @@ void Rs232Init(void) /* Select option 2 as the UART peripheral source clock and enable the clock. Option 2 * is the SIRCDIV2_CLK, which is available on all peripherals and configurations. */ - PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(0b010) | PCC_PCCn_CGC_MASK; + PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK; /* Obtain the DIV2 divider value of the SIRC_CLK. */ div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT; /* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is