diff --git a/Host/MicroBoot.exe b/Host/MicroBoot.exe
index 16957e7f..1b28c229 100644
Binary files a/Host/MicroBoot.exe and b/Host/MicroBoot.exe differ
diff --git a/Host/Source/MainUnit.dfm b/Host/Source/MainUnit.dfm
index 8e824357..fec92210 100644
Binary files a/Host/Source/MainUnit.dfm and b/Host/Source/MainUnit.dfm differ
diff --git a/Host/openblt_uart.ini b/Host/openblt_uart.ini
index 56b278d5..164dac50 100644
--- a/Host/openblt_uart.ini
+++ b/Host/openblt_uart.ini
@@ -1,5 +1,5 @@
[sci]
-port=3
+port=5
baudrate=8
[xcp]
seedkey=
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf
new file mode 100644
index 00000000..7cfc9cc1
Binary files /dev/null and b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf differ
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map
new file mode 100644
index 00000000..47af06a5
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map
@@ -0,0 +1,720 @@
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/hooks.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/hooks.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/hooks.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/main.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/main.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/main.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_abt 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_irq 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_fiq 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_svc 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_und 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .heap 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/flash.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/flash.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/flash.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/can.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/can.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/can.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/cpu.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/cpu.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/cpu.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/nvm.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/nvm.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/nvm.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/timer.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/timer.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/timer.o
+ .text.TimerSet
+ 0x00000000 0x10 ARM Flash Debug/../../obj/timer.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/uart.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/uart.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/uart.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/assert.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/assert.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/assert.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/backdoor.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/backdoor.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/backdoor.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/com.o
+ .text.ComIsConnectEntryState
+ 0x00000000 0x10 ARM Flash Debug/../../obj/com.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/cop.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/cop.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/cop.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/xcp.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/xcp.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/xcp.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+UNPLACED_SECTIONS 0xffffffff 0x00000000 xw
+AHB_Peripherals 0xffe00000 0x00200000 xw
+VPB_Peripherals 0xe0000000 0x00200000 xw
+BANK3 0x83000000 0x01000000 xw
+BANK2 0x82000000 0x01000000 xw
+External_SRAM 0x81000000 0x00100000 xw
+External_FLASH 0x80000000 0x00400000 xr
+SRAM 0x40000200 0x00001ce0 xw
+FLASH 0x00000000 0x00002000 xr
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+ 0xffe00000 __AHB_Peripherals_segment_start__ = 0xffe00000
+ 0x00000000 __AHB_Peripherals_segment_end__ = 0x0
+ 0xe0000000 __VPB_Peripherals_segment_start__ = 0xe0000000
+ 0xe0200000 __VPB_Peripherals_segment_end__ = 0xe0200000
+ 0x83000000 __BANK3_segment_start__ = 0x83000000
+ 0x84000000 __BANK3_segment_end__ = 0x84000000
+ 0x82000000 __BANK2_segment_start__ = 0x82000000
+ 0x83000000 __BANK2_segment_end__ = 0x83000000
+ 0x81000000 __External_SRAM_segment_start__ = 0x81000000
+ 0x81100000 __External_SRAM_segment_end__ = 0x81100000
+ 0x80000000 __External_FLASH_segment_start__ = 0x80000000
+ 0x80400000 __External_FLASH_segment_end__ = 0x80400000
+ 0x40000200 __SRAM_segment_start__ = 0x40000200
+ 0x40001ee0 __SRAM_segment_end__ = 0x40001ee0
+ 0x00000000 __FLASH_segment_start__ = 0x0
+ 0x00002000 __FLASH_segment_end__ = 0x2000
+ 0x00000400 __STACKSIZE__ = 0x400
+ 0x00000100 __STACKSIZE_IRQ__ = 0x100
+ 0x00000100 __STACKSIZE_FIQ__ = 0x100
+ 0x00000000 __STACKSIZE_SVC__ = 0x0
+ 0x00000000 __STACKSIZE_ABT__ = 0x0
+ 0x00000000 __STACKSIZE_UND__ = 0x0
+ 0x00000400 __HEAPSIZE__ = 0x400
+ 0x80000000 __text2_load_start__ = ALIGN (__External_FLASH_segment_start__, 0x4)
+
+.text2 0x80000000 0x0
+ 0x80000000 __text2_start__ = .
+ *(.text2 .text2.*)
+ 0x80000000 __text2_end__ = (__text2_start__ + SIZEOF (.text2))
+ 0x80000000 __text2_load_end__ = __text2_end__
+ 0x00000001 . = ASSERT (((__text2_end__ >= __External_FLASH_segment_start__) && (__text2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .text2 is too large to fit in External_FLASH memory segment)
+ 0x80000000 __rodata2_load_start__ = ALIGN (__text2_end__, 0x4)
+
+.rodata2 0x80000000 0x0
+ 0x80000000 __rodata2_start__ = .
+ *(.rodata2 .rodata2.*)
+ 0x80000000 __rodata2_end__ = (__rodata2_start__ + SIZEOF (.rodata2))
+ 0x80000000 __rodata2_load_end__ = __rodata2_end__
+ 0x00000001 . = ASSERT (((__rodata2_end__ >= __External_FLASH_segment_start__) && (__rodata2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .rodata2 is too large to fit in External_FLASH memory segment)
+ 0x80000000 __data2_load_start__ = ALIGN (__rodata2_end__, 0x4)
+
+.data2 0x81000000 0x0 load address 0x80000000
+ 0x81000000 __data2_start__ = .
+ *(.data2 .data2.*)
+ 0x81000000 __data2_end__ = (__data2_start__ + SIZEOF (.data2))
+ 0x80000000 __data2_load_end__ = (__data2_load_start__ + SIZEOF (.data2))
+ 0x80000000 __External_FLASH_segment_used_end__ = (ALIGN (__rodata2_end__, 0x4) + SIZEOF (.data2))
+ 0x00000001 . = ASSERT ((((__data2_load_start__ + SIZEOF (.data2)) >= __External_FLASH_segment_start__) && ((__data2_load_start__ + SIZEOF (.data2)) <= (__External_FLASH_segment_start__ + 0x400000))), error: .data2 is too large to fit in External_FLASH memory segment)
+
+.data2_run 0x81000000 0x0
+ 0x81000000 __data2_run_start__ = .
+ 0x81000000 . = MAX ((__data2_run_start__ + SIZEOF (.data2)), .)
+ 0x81000000 __data2_run_end__ = (__data2_run_start__ + SIZEOF (.data2_run))
+ 0x81000000 __data2_run_load_end__ = __data2_run_end__
+ 0x00000001 . = ASSERT (((__data2_run_end__ >= __External_SRAM_segment_start__) && (__data2_run_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .data2_run is too large to fit in External_SRAM memory segment)
+ 0x81000000 __bss2_load_start__ = ALIGN (__data2_run_end__, 0x4)
+
+.bss2 0x81000000 0x0
+ 0x81000000 __bss2_start__ = .
+ *(.bss2 .bss2.*)
+ 0x81000000 __bss2_end__ = (__bss2_start__ + SIZEOF (.bss2))
+ 0x81000000 __bss2_load_end__ = __bss2_end__
+ 0x81000000 __External_SRAM_segment_used_end__ = (ALIGN (__data2_run_end__, 0x4) + SIZEOF (.bss2))
+ 0x00000001 . = ASSERT (((__bss2_end__ >= __External_SRAM_segment_start__) && (__bss2_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .bss2 is too large to fit in External_SRAM memory segment)
+ 0x40000200 __vectors_ram_load_start__ = __SRAM_segment_start__
+
+.vectors_ram 0x40000200 0x3c
+ 0x40000200 __vectors_ram_start__ = .
+ *(.vectors_ram .vectors_ram.*)
+ 0x4000023c . = MAX ((__vectors_ram_start__ + 0x3c), .)
+ *fill* 0x40000200 0x3c 00
+ 0x4000023c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram))
+ 0x4000023c __vectors_ram_load_end__ = __vectors_ram_end__
+ 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .vectors_ram is too large to fit in SRAM memory segment)
+ 0x00000000 __vectors_load_start__ = __FLASH_segment_start__
+
+.vectors 0x00000000 0x38
+ 0x00000000 __vectors_start__ = .
+ *(.vectors .vectors.*)
+ .vectors 0x00000000 0x38 ARM Flash Debug/../../obj/cstart.o
+ 0x00000000 _vectors
+ 0x00000038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors))
+ 0x00000038 __vectors_load_end__ = __vectors_end__
+ 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .vectors is too large to fit in FLASH memory segment)
+ 0x00000038 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
+
+.init 0x00000038 0x338
+ 0x00000038 __init_start__ = .
+ *(.init .init.*)
+ *fill* 0x00000038 0x8 00
+ .init 0x00000040 0x330 ARM Flash Debug/../../obj/cstart.o
+ 0x00000040 EntryFromProg
+ 0x00000050 Reset_Handler
+ 0x00000050 __start
+ 0x00000168 exit
+ 0x000002e0 undef_handler
+ 0x000002e4 pabort_handler
+ 0x000002e8 dabort_handler
+ 0x000002ec fiq_handler
+ 0x000002f0 irq_handler
+ 0x00000370 __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x00000370 __init_load_end__ = __init_end__
+ 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .init is too large to fit in FLASH memory segment)
+ 0x00000370 __text_load_start__ = ALIGN (__init_end__, 0x4)
+
+.text 0x00000370 0xef0
+ 0x00000370 __text_start__ = .
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+ .glue_7 0x00000000 0x0 linker stubs
+ .glue_7t 0x00000000 0x0 linker stubs
+ .text.startup.main
+ 0x00000370 0x104 ARM Flash Debug/../../obj/main.o
+ 0x00000370 main
+ .text.FlashGetSector
+ 0x00000474 0x60 ARM Flash Debug/../../obj/flash.o
+ .text.FlashWriteBlock
+ 0x000004d4 0xf0 ARM Flash Debug/../../obj/flash.o
+ .text.FlashSwitchBlock
+ 0x000005c4 0x84 ARM Flash Debug/../../obj/flash.o
+ .text.FlashAddToBlock
+ 0x00000648 0xc8 ARM Flash Debug/../../obj/flash.o
+ .text.FlashInit
+ 0x00000710 0x20 ARM Flash Debug/../../obj/flash.o
+ 0x00000710 FlashInit
+ .text.FlashWrite
+ 0x00000730 0x70 ARM Flash Debug/../../obj/flash.o
+ 0x00000730 FlashWrite
+ .text.FlashErase
+ 0x000007a0 0x108 ARM Flash Debug/../../obj/flash.o
+ 0x000007a0 FlashErase
+ .text.FlashVerifyChecksum
+ 0x000008a8 0x48 ARM Flash Debug/../../obj/flash.o
+ 0x000008a8 FlashVerifyChecksum
+ .text.FlashWriteChecksum
+ 0x000008f0 0x6c ARM Flash Debug/../../obj/flash.o
+ 0x000008f0 FlashWriteChecksum
+ .text.FlashDone
+ 0x0000095c 0x50 ARM Flash Debug/../../obj/flash.o
+ 0x0000095c FlashDone
+ .text.CpuMemCopy
+ 0x000009ac 0x40 ARM Flash Debug/../../obj/cpu.o
+ 0x000009ac CpuMemCopy
+ .text.CpuStartUserProgram
+ 0x000009ec 0x44 ARM Flash Debug/../../obj/cpu.o
+ 0x000009ec CpuStartUserProgram
+ .text.CpuReset
+ 0x00000a30 0x10 ARM Flash Debug/../../obj/cpu.o
+ 0x00000a30 CpuReset
+ .text.NvmInit 0x00000a40 0x10 ARM Flash Debug/../../obj/nvm.o
+ 0x00000a40 NvmInit
+ .text.NvmWrite
+ 0x00000a50 0x10 ARM Flash Debug/../../obj/nvm.o
+ 0x00000a50 NvmWrite
+ .text.NvmErase
+ 0x00000a60 0x10 ARM Flash Debug/../../obj/nvm.o
+ 0x00000a60 NvmErase
+ .text.NvmVerifyChecksum
+ 0x00000a70 0x10 ARM Flash Debug/../../obj/nvm.o
+ 0x00000a70 NvmVerifyChecksum
+ .text.NvmDone 0x00000a80 0x18 ARM Flash Debug/../../obj/nvm.o
+ 0x00000a80 NvmDone
+ .text.TimerInit
+ 0x00000a98 0x48 ARM Flash Debug/../../obj/timer.o
+ 0x00000a98 TimerInit
+ .text.TimerReset
+ 0x00000ae0 0x20 ARM Flash Debug/../../obj/timer.o
+ 0x00000ae0 TimerReset
+ .text.TimerUpdate
+ 0x00000b00 0x38 ARM Flash Debug/../../obj/timer.o
+ 0x00000b00 TimerUpdate
+ .text.TimerGet
+ 0x00000b38 0x1c ARM Flash Debug/../../obj/timer.o
+ 0x00000b38 TimerGet
+ .text.UartInit
+ 0x00000b54 0x40 ARM Flash Debug/../../obj/uart.o
+ 0x00000b54 UartInit
+ .text.UartTransmitPacket
+ 0x00000b94 0xc0 ARM Flash Debug/../../obj/uart.o
+ 0x00000b94 UartTransmitPacket
+ .text.UartReceivePacket
+ 0x00000c54 0xb8 ARM Flash Debug/../../obj/uart.o
+ 0x00000c54 UartReceivePacket
+ .text.AssertFailure
+ 0x00000d0c 0x24 ARM Flash Debug/../../obj/assert.o
+ 0x00000d0c AssertFailure
+ .text.BackDoorCheck
+ 0x00000d30 0x48 ARM Flash Debug/../../obj/backdoor.o
+ 0x00000d30 BackDoorCheck
+ .text.BackDoorInit
+ 0x00000d78 0x20 ARM Flash Debug/../../obj/backdoor.o
+ 0x00000d78 BackDoorInit
+ .text.BootInit
+ 0x00000d98 0x1c ARM Flash Debug/../../obj/boot.o
+ 0x00000d98 BootInit
+ .text.BootTask
+ 0x00000db4 0x18 ARM Flash Debug/../../obj/boot.o
+ 0x00000db4 BootTask
+ .text.ComInit 0x00000dcc 0x3c ARM Flash Debug/../../obj/com.o
+ 0x00000dcc ComInit
+ .text.ComTask 0x00000e08 0x24 ARM Flash Debug/../../obj/com.o
+ 0x00000e08 ComTask
+ .text.ComTransmitPacket
+ 0x00000e2c 0x18 ARM Flash Debug/../../obj/com.o
+ 0x00000e2c ComTransmitPacket
+ .text.ComSetConnectEntryState
+ 0x00000e44 0x14 ARM Flash Debug/../../obj/com.o
+ 0x00000e44 ComSetConnectEntryState
+ .text.ComIsConnected
+ 0x00000e58 0x10 ARM Flash Debug/../../obj/com.o
+ 0x00000e58 ComIsConnected
+ .text.CopInit 0x00000e68 0x4 ARM Flash Debug/../../obj/cop.o
+ 0x00000e68 CopInit
+ .text.CopService
+ 0x00000e6c 0x4 ARM Flash Debug/../../obj/cop.o
+ 0x00000e6c CopService
+ .text.XcpSetCtoError
+ 0x00000e70 0x20 ARM Flash Debug/../../obj/xcp.o
+ .text.XcpInit 0x00000e90 0x28 ARM Flash Debug/../../obj/xcp.o
+ 0x00000e90 XcpInit
+ .text.XcpIsConnected
+ 0x00000eb8 0x18 ARM Flash Debug/../../obj/xcp.o
+ 0x00000eb8 XcpIsConnected
+ .text.XcpPacketTransmitted
+ 0x00000ed0 0x14 ARM Flash Debug/../../obj/xcp.o
+ 0x00000ed0 XcpPacketTransmitted
+ .text.XcpPacketReceived
+ 0x00000ee4 0x37c ARM Flash Debug/../../obj/xcp.o
+ 0x00000ee4 XcpPacketReceived
+ 0x00001260 __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x00001260 __text_load_end__ = __text_end__
+
+.vfp11_veneer 0x00000000 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x00000000 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .text is too large to fit in FLASH memory segment)
+ 0x00001260 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x00001260 0x0
+ 0x00001260 __dtors_start__ = .
+ *(SORT(.dtors.*))
+ *(.dtors)
+ 0x00001260 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x00001260 __dtors_load_end__ = __dtors_end__
+ 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .dtors is too large to fit in FLASH memory segment)
+ 0x00001260 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+
+.ctors 0x00001260 0x0
+ 0x00001260 __ctors_start__ = .
+ *(SORT(.ctors.*))
+ *(.ctors)
+ 0x00001260 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x00001260 __ctors_load_end__ = __ctors_end__
+ 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .ctors is too large to fit in FLASH memory segment)
+ 0x00001260 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+
+.rodata 0x00001260 0x1b8
+ 0x00001260 __rodata_start__ = .
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ .rodata.pll_dividers.850
+ 0x00001260 0x4 ARM Flash Debug/../../obj/main.o
+ .rodata.str1.1
+ 0x00001264 0x67 ARM Flash Debug/../../obj/main.o
+ *fill* 0x000012cb 0x1 00
+ .rodata.flashLayout
+ 0x000012cc 0xc0 ARM Flash Debug/../../obj/flash.o
+ .rodata.str1.1
+ 0x0000138c 0x84 ARM Flash Debug/../../obj/uart.o
+ .rodata.xcpStationId
+ 0x00001410 0x8 ARM Flash Debug/../../obj/xcp.o
+ 0x00001418 __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x00001418 __rodata_load_end__ = __rodata_end__
+ 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .rodata is too large to fit in FLASH memory segment)
+ 0x00001418 __data_load_start__ = ALIGN (__rodata_end__, 0x4)
+
+.data 0x4000023c 0x0 load address 0x00001418
+ 0x4000023c __data_start__ = .
+ *(.data .data.* .gnu.linkonce.d.*)
+ 0x4000023c __data_end__ = (__data_start__ + SIZEOF (.data))
+ 0x00001418 __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x40000))), error: .data is too large to fit in FLASH memory segment)
+
+.data_run 0x4000023c 0x0
+ 0x4000023c __data_run_start__ = .
+ 0x4000023c . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
+ 0x4000023c __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
+ 0x4000023c __data_run_load_end__ = __data_run_end__
+ 0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .data_run is too large to fit in SRAM memory segment)
+ 0x4000023c __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
+
+.bss 0x4000023c 0x4ec
+ 0x4000023c __bss_start__ = .
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ .bss.bootBlockInfo
+ 0x4000023c 0x204 ARM Flash Debug/../../obj/flash.o
+ .bss.blockInfo
+ 0x40000440 0x204 ARM Flash Debug/../../obj/flash.o
+ .bss.millisecond_counter
+ 0x40000644 0x4 ARM Flash Debug/../../obj/timer.o
+ .bss.free_running_counter_last
+ 0x40000648 0x4 ARM Flash Debug/../../obj/timer.o
+ .bss.xcpCtoRxLength.866
+ 0x4000064c 0x1 ARM Flash Debug/../../obj/uart.o
+ .bss.xcpCtoReqPacket.865
+ 0x4000064d 0x41 ARM Flash Debug/../../obj/uart.o
+ .bss.xcpCtoRxInProgress.867
+ 0x4000068e 0x1 ARM Flash Debug/../../obj/uart.o
+ *fill* 0x4000068f 0x1 00
+ .bss.assert_failure_file
+ 0x40000690 0x4 ARM Flash Debug/../../obj/assert.o
+ .bss.assert_failure_line
+ 0x40000694 0x4 ARM Flash Debug/../../obj/assert.o
+ .bss.backdoorOpen
+ 0x40000698 0x1 ARM Flash Debug/../../obj/backdoor.o
+ .bss.comEntryStateConnect
+ 0x40000699 0x1 ARM Flash Debug/../../obj/com.o
+ .bss.xcpCtoReqPacket.855
+ 0x4000069a 0x40 ARM Flash Debug/../../obj/com.o
+ *fill* 0x400006da 0x2 00
+ .bss.xcpInfo 0x400006dc 0x4c ARM Flash Debug/../../obj/xcp.o
+ *(COMMON)
+ 0x40000728 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x40000728 __bss_load_end__ = __bss_end__
+ 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .bss is too large to fit in SRAM memory segment)
+ 0x40000728 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+
+.non_init 0x40000728 0x0
+ 0x40000728 __non_init_start__ = .
+ *(.non_init .non_init.*)
+ 0x40000728 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x40000728 __non_init_load_end__ = __non_init_end__
+ 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .non_init is too large to fit in SRAM memory segment)
+ 0x40000728 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+
+.heap 0x40000728 0x400
+ 0x40000728 __heap_start__ = .
+ *(.heap .heap.*)
+ 0x40000b28 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x40000728 0x400 00
+ 0x40000b28 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x40000b28 __heap_load_end__ = __heap_end__
+ 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .heap is too large to fit in SRAM memory segment)
+ 0x40000b28 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+
+.stack 0x40000b28 0x400
+ 0x40000b28 __stack_start__ = .
+ *(.stack .stack.*)
+ 0x40000f28 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x40000b28 0x400 00
+ 0x40000f28 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x40000f28 __stack_load_end__ = __stack_end__
+ 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack is too large to fit in SRAM memory segment)
+ 0x40000f28 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
+
+.stack_irq 0x40000f28 0x100
+ 0x40000f28 __stack_irq_start__ = .
+ *(.stack_irq .stack_irq.*)
+ 0x40001028 . = ALIGN (MAX ((__stack_irq_start__ + __STACKSIZE_IRQ__), .), 0x4)
+ *fill* 0x40000f28 0x100 00
+ 0x40001028 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
+ 0x40001028 __stack_irq_load_end__ = __stack_irq_end__
+ 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_irq is too large to fit in SRAM memory segment)
+ 0x40001028 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
+
+.stack_fiq 0x40001028 0x100
+ 0x40001028 __stack_fiq_start__ = .
+ *(.stack_fiq .stack_fiq.*)
+ 0x40001128 . = ALIGN (MAX ((__stack_fiq_start__ + __STACKSIZE_FIQ__), .), 0x4)
+ *fill* 0x40001028 0x100 00
+ 0x40001128 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
+ 0x40001128 __stack_fiq_load_end__ = __stack_fiq_end__
+ 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_fiq is too large to fit in SRAM memory segment)
+ 0x40001128 __stack_svc_load_start__ = ALIGN (__stack_fiq_end__, 0x4)
+
+.stack_svc 0x40001128 0x0
+ 0x40001128 __stack_svc_start__ = .
+ *(.stack_svc .stack_svc.*)
+ 0x40001128 . = ALIGN (MAX ((__stack_svc_start__ + __STACKSIZE_SVC__), .), 0x4)
+ 0x40001128 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
+ 0x40001128 __stack_svc_load_end__ = __stack_svc_end__
+ 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_svc is too large to fit in SRAM memory segment)
+ 0x40001128 __stack_abt_load_start__ = ALIGN (__stack_svc_end__, 0x4)
+
+.stack_abt 0x40001128 0x0
+ 0x40001128 __stack_abt_start__ = .
+ *(.stack_abt .stack_abt.*)
+ 0x40001128 . = ALIGN (MAX ((__stack_abt_start__ + __STACKSIZE_ABT__), .), 0x4)
+ 0x40001128 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
+ 0x40001128 __stack_abt_load_end__ = __stack_abt_end__
+ 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_abt is too large to fit in SRAM memory segment)
+ 0x40001128 __stack_und_load_start__ = ALIGN (__stack_abt_end__, 0x4)
+
+.stack_und 0x40001128 0x0
+ 0x40001128 __stack_und_start__ = .
+ *(.stack_und .stack_und.*)
+ 0x40001128 . = ALIGN (MAX ((__stack_und_start__ + __STACKSIZE_UND__), .), 0x4)
+ 0x40001128 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
+ 0x40001128 __stack_und_load_end__ = __stack_und_end__
+ 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_und is too large to fit in SRAM memory segment)
+ 0x00001418 __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+
+.fast 0x40001128 0x0 load address 0x00001418
+ 0x40001128 __fast_start__ = .
+ *(.fast .fast.*)
+ 0x40001128 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
+ 0x00001418 __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x00001418 __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.fast))
+ 0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x40000))), error: .fast is too large to fit in FLASH memory segment)
+
+.fast_run 0x40001128 0x0
+ 0x40001128 __fast_run_start__ = .
+ 0x40001128 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
+ 0x40001128 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
+ 0x40001128 __fast_run_load_end__ = __fast_run_end__
+ 0x40001128 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
+ 0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .fast_run is too large to fit in SRAM memory segment)
+START GROUP
+LOAD ARM Flash Debug/../../obj/hooks.o
+LOAD ARM Flash Debug/../../obj/main.o
+LOAD ARM Flash Debug/../../obj/cstart.o
+LOAD ARM Flash Debug/../../obj/flash.o
+LOAD ARM Flash Debug/../../obj/can.o
+LOAD ARM Flash Debug/../../obj/cpu.o
+LOAD ARM Flash Debug/../../obj/nvm.o
+LOAD ARM Flash Debug/../../obj/timer.o
+LOAD ARM Flash Debug/../../obj/uart.o
+LOAD ARM Flash Debug/../../obj/assert.o
+LOAD ARM Flash Debug/../../obj/backdoor.o
+LOAD ARM Flash Debug/../../obj/boot.o
+LOAD ARM Flash Debug/../../obj/com.o
+LOAD ARM Flash Debug/../../obj/cop.o
+LOAD ARM Flash Debug/../../obj/xcp.o
+LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libcpp_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_targetio_impl_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a
+END GROUP
+OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/../bin/openbtl_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
+
+.debug_info 0x00000000 0x188c
+ .debug_info 0x00000000 0x5a ARM Flash Debug/../../obj/hooks.o
+ .debug_info 0x0000005a 0x111 ARM Flash Debug/../../obj/main.o
+ .debug_info 0x0000016b 0x110 ARM Flash Debug/../../obj/cstart.o
+ .debug_info 0x0000027b 0x5b2 ARM Flash Debug/../../obj/flash.o
+ .debug_info 0x0000082d 0x5a ARM Flash Debug/../../obj/can.o
+ .debug_info 0x00000887 0x13a ARM Flash Debug/../../obj/cpu.o
+ .debug_info 0x000009c1 0x15e ARM Flash Debug/../../obj/nvm.o
+ .debug_info 0x00000b1f 0x143 ARM Flash Debug/../../obj/timer.o
+ .debug_info 0x00000c62 0x232 ARM Flash Debug/../../obj/uart.o
+ .debug_info 0x00000e94 0xe4 ARM Flash Debug/../../obj/assert.o
+ .debug_info 0x00000f78 0xa4 ARM Flash Debug/../../obj/backdoor.o
+ .debug_info 0x0000101c 0x88 ARM Flash Debug/../../obj/boot.o
+ .debug_info 0x000010a4 0x18b ARM Flash Debug/../../obj/com.o
+ .debug_info 0x0000122f 0x86 ARM Flash Debug/../../obj/cop.o
+ .debug_info 0x000012b5 0x5d7 ARM Flash Debug/../../obj/xcp.o
+
+.debug_abbrev 0x00000000 0xa94
+ .debug_abbrev 0x00000000 0x28 ARM Flash Debug/../../obj/hooks.o
+ .debug_abbrev 0x00000028 0xaf ARM Flash Debug/../../obj/main.o
+ .debug_abbrev 0x000000d7 0x12 ARM Flash Debug/../../obj/cstart.o
+ .debug_abbrev 0x000000e9 0x21f ARM Flash Debug/../../obj/flash.o
+ .debug_abbrev 0x00000308 0x28 ARM Flash Debug/../../obj/can.o
+ .debug_abbrev 0x00000330 0xaf ARM Flash Debug/../../obj/cpu.o
+ .debug_abbrev 0x000003df 0xa3 ARM Flash Debug/../../obj/nvm.o
+ .debug_abbrev 0x00000482 0xd9 ARM Flash Debug/../../obj/timer.o
+ .debug_abbrev 0x0000055b 0x139 ARM Flash Debug/../../obj/uart.o
+ .debug_abbrev 0x00000694 0x7c ARM Flash Debug/../../obj/assert.o
+ .debug_abbrev 0x00000710 0x5b ARM Flash Debug/../../obj/backdoor.o
+ .debug_abbrev 0x0000076b 0x3f ARM Flash Debug/../../obj/boot.o
+ .debug_abbrev 0x000007aa 0xe0 ARM Flash Debug/../../obj/com.o
+ .debug_abbrev 0x0000088a 0x3f ARM Flash Debug/../../obj/cop.o
+ .debug_abbrev 0x000008c9 0x1cb ARM Flash Debug/../../obj/xcp.o
+
+.debug_line 0x00000000 0x1277
+ .debug_line 0x00000000 0x1d ARM Flash Debug/../../obj/hooks.o
+ .debug_line 0x0000001d 0x14e ARM Flash Debug/../../obj/main.o
+ .debug_line 0x0000016b 0x19e ARM Flash Debug/../../obj/cstart.o
+ .debug_line 0x00000309 0x2e6 ARM Flash Debug/../../obj/flash.o
+ .debug_line 0x000005ef 0x1d ARM Flash Debug/../../obj/can.o
+ .debug_line 0x0000060c 0xf0 ARM Flash Debug/../../obj/cpu.o
+ .debug_line 0x000006fc 0x110 ARM Flash Debug/../../obj/nvm.o
+ .debug_line 0x0000080c 0x11b ARM Flash Debug/../../obj/timer.o
+ .debug_line 0x00000927 0x16a ARM Flash Debug/../../obj/uart.o
+ .debug_line 0x00000a91 0x139 ARM Flash Debug/../../obj/assert.o
+ .debug_line 0x00000bca 0x156 ARM Flash Debug/../../obj/backdoor.o
+ .debug_line 0x00000d20 0xbf ARM Flash Debug/../../obj/boot.o
+ .debug_line 0x00000ddf 0x192 ARM Flash Debug/../../obj/com.o
+ .debug_line 0x00000f71 0xb7 ARM Flash Debug/../../obj/cop.o
+ .debug_line 0x00001028 0x24f ARM Flash Debug/../../obj/xcp.o
+
+.debug_str 0x00000000 0xdaa
+ .debug_str 0x00000000 0xb1 ARM Flash Debug/../../obj/hooks.o
+ 0xcf (size before relaxing)
+ .debug_str 0x000000b1 0xa4 ARM Flash Debug/../../obj/main.o
+ 0x110 (size before relaxing)
+ .debug_str 0x00000155 0x24d ARM Flash Debug/../../obj/flash.o
+ 0x2d8 (size before relaxing)
+ .debug_str 0x000003a2 0x83 ARM Flash Debug/../../obj/can.o
+ 0xea (size before relaxing)
+ .debug_str 0x00000425 0xc7 ARM Flash Debug/../../obj/cpu.o
+ 0x157 (size before relaxing)
+ .debug_str 0x000004ec 0xb7 ARM Flash Debug/../../obj/nvm.o
+ 0x14f (size before relaxing)
+ .debug_str 0x000005a3 0x10b ARM Flash Debug/../../obj/timer.o
+ 0x17d (size before relaxing)
+ .debug_str 0x000006ae 0x11f ARM Flash Debug/../../obj/uart.o
+ 0x1b4 (size before relaxing)
+ .debug_str 0x000007cd 0xb8 ARM Flash Debug/../../obj/assert.o
+ 0x134 (size before relaxing)
+ .debug_str 0x00000885 0xa3 ARM Flash Debug/../../obj/backdoor.o
+ 0x113 (size before relaxing)
+ .debug_str 0x00000928 0x89 ARM Flash Debug/../../obj/boot.o
+ 0xf0 (size before relaxing)
+ .debug_str 0x000009b1 0x102 ARM Flash Debug/../../obj/com.o
+ 0x19c (size before relaxing)
+ .debug_str 0x00000ab3 0x89 ARM Flash Debug/../../obj/cop.o
+ 0xf0 (size before relaxing)
+ .debug_str 0x00000b3c 0x26e ARM Flash Debug/../../obj/xcp.o
+ 0x312 (size before relaxing)
+
+.comment 0x00000000 0x11
+ .comment 0x00000000 0x11 ARM Flash Debug/../../obj/hooks.o
+ 0x12 (size before relaxing)
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/main.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/flash.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/can.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/cpu.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/nvm.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/timer.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/uart.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/assert.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/backdoor.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/boot.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/com.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/cop.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/xcp.o
+
+.ARM.attributes
+ 0x00000000 0x10
+ .ARM.attributes
+ 0x00000000 0x10 ARM Flash Debug/../../obj/hooks.o
+ .ARM.attributes
+ 0x00000010 0x10 ARM Flash Debug/../../obj/main.o
+ .ARM.attributes
+ 0x00000020 0x10 ARM Flash Debug/../../obj/cstart.o
+ .ARM.attributes
+ 0x00000030 0x10 ARM Flash Debug/../../obj/flash.o
+ .ARM.attributes
+ 0x00000040 0x10 ARM Flash Debug/../../obj/can.o
+ .ARM.attributes
+ 0x00000050 0x10 ARM Flash Debug/../../obj/cpu.o
+ .ARM.attributes
+ 0x00000060 0x10 ARM Flash Debug/../../obj/nvm.o
+ .ARM.attributes
+ 0x00000070 0x10 ARM Flash Debug/../../obj/timer.o
+ .ARM.attributes
+ 0x00000080 0x10 ARM Flash Debug/../../obj/uart.o
+ .ARM.attributes
+ 0x00000090 0x10 ARM Flash Debug/../../obj/assert.o
+ .ARM.attributes
+ 0x000000a0 0x10 ARM Flash Debug/../../obj/backdoor.o
+ .ARM.attributes
+ 0x000000b0 0x10 ARM Flash Debug/../../obj/boot.o
+ .ARM.attributes
+ 0x000000c0 0x10 ARM Flash Debug/../../obj/com.o
+ .ARM.attributes
+ 0x000000d0 0x10 ARM Flash Debug/../../obj/cop.o
+ .ARM.attributes
+ 0x000000e0 0x10 ARM Flash Debug/../../obj/xcp.o
+
+.debug_frame 0x00000000 0x548
+ .debug_frame 0x00000000 0x2c ARM Flash Debug/../../obj/main.o
+ .debug_frame 0x0000002c 0x14c ARM Flash Debug/../../obj/flash.o
+ .debug_frame 0x00000178 0x68 ARM Flash Debug/../../obj/cpu.o
+ .debug_frame 0x000001e0 0x9c ARM Flash Debug/../../obj/nvm.o
+ .debug_frame 0x0000027c 0x6c ARM Flash Debug/../../obj/timer.o
+ .debug_frame 0x000002e8 0x64 ARM Flash Debug/../../obj/uart.o
+ .debug_frame 0x0000034c 0x2c ARM Flash Debug/../../obj/assert.o
+ .debug_frame 0x00000378 0x48 ARM Flash Debug/../../obj/backdoor.o
+ .debug_frame 0x000003c0 0x48 ARM Flash Debug/../../obj/boot.o
+ .debug_frame 0x00000408 0xa0 ARM Flash Debug/../../obj/com.o
+ .debug_frame 0x000004a8 0x30 ARM Flash Debug/../../obj/cop.o
+ .debug_frame 0x000004d8 0x70 ARM Flash Debug/../../obj/xcp.o
+
+.debug_loc 0x00000000 0xb3b
+ .debug_loc 0x00000000 0x99 ARM Flash Debug/../../obj/main.o
+ .debug_loc 0x00000099 0x4e7 ARM Flash Debug/../../obj/flash.o
+ .debug_loc 0x00000580 0xe2 ARM Flash Debug/../../obj/cpu.o
+ .debug_loc 0x00000662 0xff ARM Flash Debug/../../obj/nvm.o
+ .debug_loc 0x00000761 0x20 ARM Flash Debug/../../obj/timer.o
+ .debug_loc 0x00000781 0xd9 ARM Flash Debug/../../obj/uart.o
+ .debug_loc 0x0000085a 0x46 ARM Flash Debug/../../obj/assert.o
+ .debug_loc 0x000008a0 0x40 ARM Flash Debug/../../obj/backdoor.o
+ .debug_loc 0x000008e0 0x40 ARM Flash Debug/../../obj/boot.o
+ .debug_loc 0x00000920 0xa6 ARM Flash Debug/../../obj/com.o
+ .debug_loc 0x000009c6 0x175 ARM Flash Debug/../../obj/xcp.o
+
+.debug_aranges 0x00000000 0x2b0
+ .debug_aranges
+ 0x00000000 0x20 ARM Flash Debug/../../obj/main.o
+ .debug_aranges
+ 0x00000020 0x28 ARM Flash Debug/../../obj/cstart.o
+ .debug_aranges
+ 0x00000048 0x68 ARM Flash Debug/../../obj/flash.o
+ .debug_aranges
+ 0x000000b0 0x30 ARM Flash Debug/../../obj/cpu.o
+ .debug_aranges
+ 0x000000e0 0x40 ARM Flash Debug/../../obj/nvm.o
+ .debug_aranges
+ 0x00000120 0x40 ARM Flash Debug/../../obj/timer.o
+ .debug_aranges
+ 0x00000160 0x30 ARM Flash Debug/../../obj/uart.o
+ .debug_aranges
+ 0x00000190 0x20 ARM Flash Debug/../../obj/assert.o
+ .debug_aranges
+ 0x000001b0 0x28 ARM Flash Debug/../../obj/backdoor.o
+ .debug_aranges
+ 0x000001d8 0x28 ARM Flash Debug/../../obj/boot.o
+ .debug_aranges
+ 0x00000200 0x48 ARM Flash Debug/../../obj/com.o
+ .debug_aranges
+ 0x00000248 0x28 ARM Flash Debug/../../obj/cop.o
+ .debug_aranges
+ 0x00000270 0x40 ARM Flash Debug/../../obj/xcp.o
+
+.debug_ranges 0x00000000 0x308
+ .debug_ranges 0x00000000 0x50 ARM Flash Debug/../../obj/main.o
+ .debug_ranges 0x00000050 0x20 ARM Flash Debug/../../obj/cstart.o
+ .debug_ranges 0x00000070 0x58 ARM Flash Debug/../../obj/flash.o
+ .debug_ranges 0x000000c8 0x20 ARM Flash Debug/../../obj/cpu.o
+ .debug_ranges 0x000000e8 0x30 ARM Flash Debug/../../obj/nvm.o
+ .debug_ranges 0x00000118 0x30 ARM Flash Debug/../../obj/timer.o
+ .debug_ranges 0x00000148 0x90 ARM Flash Debug/../../obj/uart.o
+ .debug_ranges 0x000001d8 0x10 ARM Flash Debug/../../obj/assert.o
+ .debug_ranges 0x000001e8 0x18 ARM Flash Debug/../../obj/backdoor.o
+ .debug_ranges 0x00000200 0x18 ARM Flash Debug/../../obj/boot.o
+ .debug_ranges 0x00000218 0x38 ARM Flash Debug/../../obj/com.o
+ .debug_ranges 0x00000250 0x18 ARM Flash Debug/../../obj/cop.o
+ .debug_ranges 0x00000268 0xa0 ARM Flash Debug/../../obj/xcp.o
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.srec b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.srec
new file mode 100644
index 00000000..2c358d52
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.srec
@@ -0,0 +1,325 @@
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+S113001018F09FE5885F20B9F0FF1FE510F09FE519
+S113002050000000E00200006C010000E402000047
+S10B0030E8020000EC020000EC
+S11300380000000000000000AC029FE50110A0E3EE
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/config.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/config.h
new file mode 100644
index 00000000..57d6bc31
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/config.h
@@ -0,0 +1,128 @@
+/****************************************************************************************
+| Description: bootloader configuration header file
+| File Name: config.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef CONFIG_H
+#define CONFIG_H
+
+/****************************************************************************************
+* C P U D R I V E R C O N F I G U R A T I O N
+****************************************************************************************/
+/* To properly initialize the baudrate clocks of the communication interface, typically
+ * the speed of the crystal oscillator and/or the speed at which the system runs is
+ * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
+ * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
+ * not dependent on the targets architecture, the byte ordering needs to be known.
+ * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects
+ * big endian mode.
+ */
+#define BOOT_CPU_XTAL_SPEED_KHZ (20000)
+#define BOOT_CPU_SYSTEM_SPEED_KHZ (60000)
+#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
+
+
+/****************************************************************************************
+* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
+****************************************************************************************/
+/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
+ * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
+ * in bits/second. Two CAN messages are reserved for communication with the host. The
+ * message identifier for sending data from the target to the host is configured with
+ * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
+ * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
+ * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
+ * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
+ * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
+ * CAN controller channel.
+ *
+ */
+#define BOOT_COM_CAN_ENABLE (0)
+#define BOOT_COM_CAN_BAUDRATE (500000)
+#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
+#define BOOT_COM_CAN_TX_MAX_DATA (8)
+#define BOOT_COM_CAN_RX_MSG_ID (0x667)
+#define BOOT_COM_CAN_RX_MAX_DATA (8)
+#define BOOT_COM_CAN_CHANNEL_INDEX (0)
+
+/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
+ * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
+ * in bits/second. The maximum amount of data bytes in a message for data transmission
+ * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
+ * respectively. It is common for a microcontroller to have more than 1 UART interface
+ * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
+ *
+ */
+#define BOOT_COM_UART_ENABLE (1)
+#define BOOT_COM_UART_BAUDRATE (57600)
+#define BOOT_COM_UART_TX_MAX_DATA (64)
+#define BOOT_COM_UART_RX_MAX_DATA (64)
+#define BOOT_COM_UART_CHANNEL_INDEX (0)
+
+
+/****************************************************************************************
+* B A C K D O O R E N T R Y C O N F I G U R A T I O N
+****************************************************************************************/
+/* It is possible to implement an application specific method to force the bootloader to
+ * stay active after a reset. Such a backdoor entry into the bootloader is desired in
+ * situations where the user program does not run properly and therefore cannot
+ * reactivate the bootloader. By enabling these hook functions, the application can
+ * implement the backdoor, which overrides the default backdoor entry that is programmed
+ * into the bootloader. When desired for security purposes, these hook functions can
+ * also be implemented in a way that disables the backdoor entry altogether.
+ */
+#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
+
+
+/****************************************************************************************
+* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
+****************************************************************************************/
+/* The NVM driver typically supports erase and program operations of the internal memory
+ * present on the microcontroller. Through these hook functions the NVM driver can be
+ * extended to support additional memory types such as external flash memory and serial
+ * eeproms. The size of the internal memory in kilobytes is specified with configurable
+ * BOOT_NVM_SIZE_KB.
+ */
+#define BOOT_NVM_HOOKS_ENABLE (0)
+#define BOOT_NVM_SIZE_KB (256)
+
+
+/****************************************************************************************
+* W A T C H D O G D R I V E R C O N F I G U R A T I O N
+****************************************************************************************/
+/* The COP driver cannot be configured internally in the bootloader, because its use
+ * and configuration is application specific. The bootloader does need to service the
+ * watchdog in case it is used. When the application requires the use of a watchdog,
+ * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
+ * hook functions.
+ */
+#define BOOT_COP_HOOKS_ENABLE (0)
+
+
+#endif /* CONFIG_H */
+/*********************************** end of config.h ***********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c
new file mode 100644
index 00000000..e46906ec
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/hooks.c
@@ -0,0 +1,187 @@
+/****************************************************************************************
+| Description: bootloader callback source file
+| File Name: hooks.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+#include "lpc2294.h" /* CPU register definitions */
+
+
+/****************************************************************************************
+* B A C K D O O R E N T R Y H O O K F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
+/****************************************************************************************
+** NAME: BackDoorInitHook
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the backdoor entry option.
+**
+****************************************************************************************/
+void BackDoorInitHook(void)
+{
+ /* configure the button connected to P0.16 as a digital input */
+ IO0DIR &= ~(1<<16);
+} /*** end of BackDoorInitHook ***/
+
+
+/****************************************************************************************
+** NAME: BackDoorEntryHook
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
+** DESCRIPTION: Checks if a backdoor entry is requested.
+**
+****************************************************************************************/
+blt_bool BackDoorEntryHook(void)
+{
+ /* button P0.16 has a pullup, so will read high by default. enter backdoor only when
+ * this button is pressed. this is the case when it reads low */
+ if ((IO0PIN & (1<<16)) == 0)
+ {
+ return BLT_TRUE;
+ }
+ return BLT_FALSE;
+} /*** end of BackDoorEntryHook ***/
+#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_NVM_HOOKS_ENABLE > 0)
+/****************************************************************************************
+** NAME: NvmInitHook
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Callback that gets called at the start of the internal NVM driver
+** initialization routine.
+**
+****************************************************************************************/
+void NvmInitHook(void)
+{
+} /*** end of NvmInitHook ***/
+
+
+/****************************************************************************************
+** NAME: NvmWriteHook
+** PARAMETER: addr start address
+** len length in bytes
+** data pointer to the data buffer.
+** RETURN VALUE: BTL_NVM_OKAY if successful, BTL_NVM_NOT_IN_RANGE if the address is
+** not within the supported memory range, or BTL_NVM_ERROR is the write
+** operation failed.
+** DESCRIPTION: Callback that gets called at the start of the NVM driver write
+** routine. It allows additional memory to be operated on. If the address
+** is not within the range of the additional memory, then
+** BTL_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
+** been written yet.
+**
+**
+****************************************************************************************/
+blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+ return BTL_NVM_NOT_IN_RANGE;
+} /*** end of NvmWriteHook ***/
+
+
+/****************************************************************************************
+** NAME: NvmEraseHook
+** PARAMETER: addr start address
+** len length in bytes
+** RETURN VALUE: BTL_NVM_OKAY if successful, BTL_NVM_NOT_IN_RANGE if the address is
+** not within the supported memory range, or BTL_NVM_ERROR is the erase
+** operation failed.
+** DESCRIPTION: Callback that gets called at the start of the NVM driver erase
+** routine. It allows additional memory to be operated on. If the address
+** is not within the range of the additional memory, then
+** BTL_NVM_NOT_IN_RANGE must be returned to indicate that the memory
+** hasn't been erased yet.
+**
+****************************************************************************************/
+blt_bool NvmEraseHook(blt_addr addr, blt_int32u len)
+{
+ return BTL_NVM_NOT_IN_RANGE;
+} /*** end of NvmEraseHook ***/
+
+
+/****************************************************************************************
+** NAME: NvmDoneHook
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BLT_FALSE otherwise.
+** DESCRIPTION: Callback that gets called at the end of the NVM programming session.
+**
+****************************************************************************************/
+blt_bool NvmDoneHook(void)
+{
+ return BLT_TRUE;
+} /*** end of NvmDoneHook ***/
+#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
+
+
+/****************************************************************************************
+* W A T C H D O G D R I V E R H O O K F U N C T I O N S
+****************************************************************************************/
+
+#if (BOOT_COP_HOOKS_ENABLE > 0)
+/****************************************************************************************
+** NAME: CopInitHook
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Callback that gets called at the end of the internal COP driver
+** initialization routine. It can be used to configure and enable the
+** watchdog.
+**
+****************************************************************************************/
+void CopInitHook(void)
+{
+} /*** end of CopInitHook ***/
+
+
+/****************************************************************************************
+** NAME: CopServiceHook
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Callback that gets called at the end of the internal COP driver
+** service routine. This gets called upon initialization and during
+** potential long lasting loops and routine. It can be used to service
+** the watchdog to prevent a watchdog reset.
+**
+****************************************************************************************/
+void CopServiceHook(void)
+{
+} /*** end of CopServiceHook ***/
+#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
+
+
+/*********************************** end of hooks.c ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp
new file mode 100644
index 00000000..cfbf6ba6
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzp
@@ -0,0 +1,64 @@
+
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs
new file mode 100644
index 00000000..d6c8b5dd
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/lpc2294_crossworks.hzs
@@ -0,0 +1,60 @@
+
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt
new file mode 100644
index 00000000..87eb22da
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/ide/readme.txt
@@ -0,0 +1,4 @@
+Integrated Development Environment
+----------------------------------
+Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
+the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h
new file mode 100644
index 00000000..209015fb
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/lpc2294.h
@@ -0,0 +1,409 @@
+/****************************************************************************************
+| Description: NXP LPC2294 register definitions
+| File Name: lpc2294.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef LPC2294_H
+#define LPC2294_H
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/* EXTERNAL MEMORY CONTROLLER (EMC) */
+#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
+#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
+#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
+#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
+
+/* External Interrupts */
+#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
+#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
+#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
+#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
+
+/* SMemory mapping control. */
+#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
+
+/* Phase Locked Loop (PLL) */
+#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
+#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
+#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
+#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
+
+/* Power Control */
+#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
+#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
+
+/* VPB Divider */
+#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
+
+/* Memory Accelerator Module (MAM) */
+#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
+#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
+
+/* Vectored Interrupt Controller (VIC) */
+#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
+#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
+#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
+#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
+#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
+#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
+#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
+#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
+#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
+#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
+#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
+#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
+#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
+#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
+#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
+#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
+#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
+#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
+#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
+#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
+#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
+#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
+#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
+#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
+#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
+#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
+#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
+#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
+#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
+#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
+#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
+#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
+#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
+#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
+#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
+#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
+#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
+#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
+#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
+#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
+#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
+#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
+#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
+
+/* Pin Connect Block */
+#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
+#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
+#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
+
+/* General Purpose Input/Output (GPIO) */
+#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
+#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
+#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
+#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
+
+#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
+#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
+#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
+#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
+
+#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
+#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
+#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
+#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
+
+#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
+#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
+#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
+#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
+
+#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
+#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
+#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
+#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
+
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
+#define U0RBR (*((volatile unsigned char *) 0xE000C000))
+#define U0THR (*((volatile unsigned char *) 0xE000C000))
+#define U0IER (*((volatile unsigned char *) 0xE000C004))
+#define U0IIR (*((volatile unsigned char *) 0xE000C008))
+#define U0FCR (*((volatile unsigned char *) 0xE000C008))
+#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
+#define U0LSR (*((volatile unsigned char *) 0xE000C014))
+#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
+#define U0DLL (*((volatile unsigned char *) 0xE000C000))
+#define U0DLM (*((volatile unsigned char *) 0xE000C004))
+
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
+#define U1RBR (*((volatile unsigned char *) 0xE0010000))
+#define U1THR (*((volatile unsigned char *) 0xE0010000))
+#define U1IER (*((volatile unsigned char *) 0xE0010004))
+#define U1IIR (*((volatile unsigned char *) 0xE0010008))
+#define U1FCR (*((volatile unsigned char *) 0xE0010008))
+#define U1LCR (*((volatile unsigned char *) 0xE001000C))
+#define U1MCR (*((volatile unsigned char *) 0xE0010010))
+#define U1LSR (*((volatile unsigned char *) 0xE0010014))
+#define U1MSR (*((volatile unsigned char *) 0xE0010018))
+#define U1SCR (*((volatile unsigned char *) 0xE001001C))
+#define U1DLL (*((volatile unsigned char *) 0xE0010000))
+#define U1DLM (*((volatile unsigned char *) 0xE0010004))
+
+/* I2C (8/16 bit data bus) */
+#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
+#define I2STAT (*((volatile unsigned long *) 0xE001C004))
+#define I2DAT (*((volatile unsigned long *) 0xE001C008))
+#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
+#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
+#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
+#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
+
+/* SPI (Serial Peripheral Interface) */
+ /* only for lpc210x*/
+#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
+#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
+#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
+#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
+#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
+
+#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
+#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
+#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
+#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
+#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
+
+#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
+#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
+#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
+#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
+#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
+
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
+#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
+#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
+#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
+#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
+#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
+#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
+#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
+#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
+#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
+#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
+#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
+#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
+#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
+#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
+#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
+#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
+#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
+#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
+#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
+#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
+#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
+#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
+#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
+#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
+
+#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
+#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
+#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
+#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
+#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
+#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
+#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
+#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
+#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
+#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
+#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
+#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
+#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
+#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
+#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
+#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
+#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
+#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
+#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
+#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
+#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
+#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
+#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
+#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
+
+#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
+#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
+#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
+#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
+#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
+#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
+#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
+#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
+#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
+#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
+#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
+#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
+#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
+#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
+#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
+#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
+#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
+#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
+#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
+#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
+#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
+
+#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
+#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
+#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
+#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
+#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
+#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
+#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
+#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
+#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
+#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
+#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
+#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
+#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
+#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
+#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
+#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
+#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
+#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
+#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
+#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
+#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
+
+
+#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
+#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
+#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
+
+#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
+#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
+#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
+#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
+#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
+#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
+#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
+#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
+
+
+/* Timer 0 */
+#define T0IR (*((volatile unsigned long *) 0xE0004000))
+#define T0TCR (*((volatile unsigned long *) 0xE0004004))
+#define T0TC (*((volatile unsigned long *) 0xE0004008))
+#define T0PR (*((volatile unsigned long *) 0xE000400C))
+#define T0PC (*((volatile unsigned long *) 0xE0004010))
+#define T0MCR (*((volatile unsigned long *) 0xE0004014))
+#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
+#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
+#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
+#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
+#define T0CCR (*((volatile unsigned long *) 0xE0004028))
+#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
+#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
+#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
+#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
+#define T0EMR (*((volatile unsigned long *) 0xE000403C))
+
+/* Timer 1 */
+#define T1IR (*((volatile unsigned long *) 0xE0008000))
+#define T1TCR (*((volatile unsigned long *) 0xE0008004))
+#define T1TC (*((volatile unsigned long *) 0xE0008008))
+#define T1PR (*((volatile unsigned long *) 0xE000800C))
+#define T1PC (*((volatile unsigned long *) 0xE0008010))
+#define T1MCR (*((volatile unsigned long *) 0xE0008014))
+#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
+#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
+#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
+#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
+#define T1CCR (*((volatile unsigned long *) 0xE0008028))
+#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
+#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
+#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
+#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
+#define T1EMR (*((volatile unsigned long *) 0xE000803C))
+
+/* Pulse Width Modulator (PWM) */
+#define PWMIR (*((volatile unsigned long *) 0xE0014000))
+#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
+#define PWMTC (*((volatile unsigned long *) 0xE0014008))
+#define PWMPR (*((volatile unsigned long *) 0xE001400C))
+#define PWMPC (*((volatile unsigned long *) 0xE0014010))
+#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
+#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
+#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
+#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
+#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
+#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
+#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
+#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
+#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
+#define PWMLER (*((volatile unsigned long *) 0xE0014050))
+
+/* A/D CONVERTER */
+#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
+#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
+
+/* Real Time Clock */
+#define ILR (*((volatile unsigned char *) 0xE0024000))
+#define CTC (*((volatile unsigned short*) 0xE0024004))
+#define CCR (*((volatile unsigned char *) 0xE0024008))
+#define CIIR (*((volatile unsigned char *) 0xE002400C))
+#define AMR (*((volatile unsigned char *) 0xE0024010))
+#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
+#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
+#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
+#define SEC (*((volatile unsigned char *) 0xE0024020))
+#define MIN (*((volatile unsigned char *) 0xE0024024))
+#define HOUR (*((volatile unsigned char *) 0xE0024028))
+#define DOM (*((volatile unsigned char *) 0xE002402C))
+#define DOW (*((volatile unsigned char *) 0xE0024030))
+#define DOY (*((volatile unsigned short*) 0xE0024034))
+#define MONTH (*((volatile unsigned char *) 0xE0024038))
+#define YEAR (*((volatile unsigned short*) 0xE002403C))
+#define ALSEC (*((volatile unsigned char *) 0xE0024060))
+#define ALMIN (*((volatile unsigned char *) 0xE0024064))
+#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
+#define ALDOM (*((volatile unsigned char *) 0xE002406C))
+#define ALDOW (*((volatile unsigned char *) 0xE0024070))
+#define ALDOY (*((volatile unsigned short*) 0xE0024074))
+#define ALMON (*((volatile unsigned char *) 0xE0024078))
+#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
+#define PREINT (*((volatile unsigned short*) 0xE0024080))
+#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
+
+/* Watchdog */
+#define WDMOD (*((volatile unsigned char *) 0xE0000000))
+#define WDTC (*((volatile unsigned long *) 0xE0000004))
+#define WDFEED (*((volatile unsigned char *) 0xE0000008))
+#define WDTV (*((volatile unsigned long *) 0xE000000C))
+
+#endif /* LPC2294_H */
+/*********************************** end of lpc2294.h **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c
new file mode 100644
index 00000000..52da4617
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Boot/main.c
@@ -0,0 +1,158 @@
+/****************************************************************************************
+| Description: bootloader application source file
+| File Name: main.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+#include "lpc2294.h" /* CPU register definitions */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+
+
+/****************************************************************************************
+** NAME: main
+** PARAMETER: none
+** RETURN VALUE: program return code
+** DESCRIPTION: This is the entry point for the bootloader application and is called
+** by the reset interrupt vector after the C-startup routines executed.
+**
+****************************************************************************************/
+int main(void)
+{
+ /* initialize the microcontroller */
+ Init();
+ /* initialize the bootloader */
+ BootInit();
+ /* start the infinite program loop */
+ while (1)
+ {
+ /* run the bootloader task */
+ BootTask();
+ }
+
+ /* program should never get here */
+ return 0;
+} /*** end of main ***/
+
+
+/****************************************************************************************
+** NAME: Init
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
+** configured equal to Fpll. The GPIO pin of the status LED is configured
+** as digital output.
+**
+****************************************************************************************/
+static void Init(void)
+{
+ blt_int8u m_sel; /* pll multiplier register value */
+ static blt_int8u pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
+ blt_int8u p_sel_cnt; /* loop counter to find p_sel */
+ blt_int32u f_cco; /* current controller oscillator */
+
+ /* check that pll multiplier value will be in the range 1..32 */
+ ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
+ BOOT_CPU_XTAL_SPEED_KHZ >= 1);
+
+ ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
+ BOOT_CPU_XTAL_SPEED_KHZ <= 32);
+
+ /* calculate MSEL: M = round(Fcclk / Fosc) */
+ m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
+ BOOT_CPU_XTAL_SPEED_KHZ;
+ /* value for the PLLCFG register is -1 */
+ m_sel--;
+
+ /* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
+ for (p_sel_cnt=0; p_sel_cnt= 156000) && (f_cco <= 320000) )
+ {
+ /* found a valid pll divider value */
+ break;
+ }
+ }
+ /* check that a valid value was found */
+ ASSERT_RT(p_sel_cnt < (sizeof(pll_dividers)/sizeof(pll_dividers[0])));
+
+ /* set multiplier and divider values */
+ PLLCFG = (p_sel_cnt << 5) | m_sel;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* enable the PLL */
+ PLLCON = 0x1;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* wait for the PLL to lock to set frequency */
+ while(!(PLLSTAT & 0x400)) { ; }
+ /* connect the PLL as the clock source */
+ PLLCON = 0x3;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
+ * Fcclk >= 60 MHz: 4 clock cycles
+ * Fcclk >= 40 MHz: 3 clock cycles
+ * Fcclk >= 20 MHz: 2 clock cycles
+ * Fcclk < 20 MHz: 1 clock cycle
+ */
+ MAMCR = 0x0;
+#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60)
+ MAMTIM = 4;
+#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40)
+ MAMTIM = 3;
+#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20)
+ MAMTIM = 2;
+#else
+ MAMTIM = 1;
+#endif
+ MAMCR = 0x2;
+ /* setting peripheral Clock (pclk) to System Clock (cclk) */
+ VPBDIV = 0x1;
+#if (BOOT_COM_UART_ENABLE > 0)
+ /* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
+ PINSEL0 |= 0x05;
+#endif
+#if (BOOT_COM_CAN_ENABLE > 0)
+ /* configure P0.25 for CAN1 Rx functionality */
+ PINSEL1 |= 0x00040000L;
+#endif
+} /*** end of Init ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf
new file mode 100644
index 00000000..acbbbf4c
Binary files /dev/null and b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.elf differ
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
new file mode 100644
index 00000000..0c1b218b
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.map
@@ -0,0 +1,1403 @@
+Archive member included because of file (symbol)
+
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2_asm.o)
+ ARM Flash Debug/../../obj/main.o (memcpy)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ (__vfprintf_int)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ (__vfscanf_int)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o) (__getc)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o) (__umoddi3)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ (__do_debug_operation_dcc)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o) (__errno)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o) (libarm_dcc_write)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o) (libarm_run_dcc_port_server)
+C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a(libm_asm.o)
+ C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o) (__floatsisf)
+
+Discarded input sections
+
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/boot.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_abt 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_irq 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_fiq 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_svc 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .stack_und 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .heap 0x00000000 0x0 ARM Flash Debug/../../obj/cstart.o
+ .text 0x00000000 0x0 ARM Flash Debug/../../obj/irq.o
+ .data 0x00000000 0x0 ARM Flash Debug/../../obj/irq.o
+ .bss 0x00000000 0x0 ARM Flash Debug/../../obj/irq.o
+ .bss.oldInterruptStatus
+ 0x00000000 0x4 ARM Flash Debug/../../obj/irq.o
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+ 0x80000000 __External_FLASH_segment_start__ = 0x80000000
+ 0x80400000 __External_FLASH_segment_end__ = 0x80400000
+ 0x40002000 __SRAM_segment_start__ = 0x40002000
+ 0x40003ee0 __SRAM_segment_end__ = 0x40003ee0
+ 0x00002000 __FLASH_segment_start__ = 0x2000
+ 0x00040000 __FLASH_segment_end__ = 0x40000
+ 0x00000400 __STACKSIZE__ = 0x400
+ 0x00000100 __STACKSIZE_IRQ__ = 0x100
+ 0x00000100 __STACKSIZE_FIQ__ = 0x100
+ 0x00000100 __STACKSIZE_SVC__ = 0x100
+ 0x00000100 __STACKSIZE_ABT__ = 0x100
+ 0x00000100 __STACKSIZE_UND__ = 0x100
+ 0x00000400 __HEAPSIZE__ = 0x400
+ 0x80000000 __text2_load_start__ = ALIGN (__External_FLASH_segment_start__, 0x4)
+
+.text2 0x80000000 0x0
+ 0x80000000 __text2_start__ = .
+ *(.text2 .text2.*)
+ 0x80000000 __text2_end__ = (__text2_start__ + SIZEOF (.text2))
+ 0x80000000 __text2_load_end__ = __text2_end__
+ 0x00000001 . = ASSERT (((__text2_end__ >= __External_FLASH_segment_start__) && (__text2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .text2 is too large to fit in External_FLASH memory segment)
+ 0x80000000 __rodata2_load_start__ = ALIGN (__text2_end__, 0x4)
+
+.rodata2 0x80000000 0x0
+ 0x80000000 __rodata2_start__ = .
+ *(.rodata2 .rodata2.*)
+ 0x80000000 __rodata2_end__ = (__rodata2_start__ + SIZEOF (.rodata2))
+ 0x80000000 __rodata2_load_end__ = __rodata2_end__
+ 0x00000001 . = ASSERT (((__rodata2_end__ >= __External_FLASH_segment_start__) && (__rodata2_end__ <= (__External_FLASH_segment_start__ + 0x400000))), error: .rodata2 is too large to fit in External_FLASH memory segment)
+ 0x80000000 __data2_load_start__ = ALIGN (__rodata2_end__, 0x4)
+
+.data2 0x81000000 0x0 load address 0x80000000
+ 0x81000000 __data2_start__ = .
+ *(.data2 .data2.*)
+ 0x81000000 __data2_end__ = (__data2_start__ + SIZEOF (.data2))
+ 0x80000000 __data2_load_end__ = (__data2_load_start__ + SIZEOF (.data2))
+ 0x80000000 __External_FLASH_segment_used_end__ = (ALIGN (__rodata2_end__, 0x4) + SIZEOF (.data2))
+ 0x00000001 . = ASSERT ((((__data2_load_start__ + SIZEOF (.data2)) >= __External_FLASH_segment_start__) && ((__data2_load_start__ + SIZEOF (.data2)) <= (__External_FLASH_segment_start__ + 0x400000))), error: .data2 is too large to fit in External_FLASH memory segment)
+
+.data2_run 0x81000000 0x0
+ 0x81000000 __data2_run_start__ = .
+ 0x81000000 . = MAX ((__data2_run_start__ + SIZEOF (.data2)), .)
+ 0x81000000 __data2_run_end__ = (__data2_run_start__ + SIZEOF (.data2_run))
+ 0x81000000 __data2_run_load_end__ = __data2_run_end__
+ 0x00000001 . = ASSERT (((__data2_run_end__ >= __External_SRAM_segment_start__) && (__data2_run_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .data2_run is too large to fit in External_SRAM memory segment)
+ 0x81000000 __bss2_load_start__ = ALIGN (__data2_run_end__, 0x4)
+
+.bss2 0x81000000 0x0
+ 0x81000000 __bss2_start__ = .
+ *(.bss2 .bss2.*)
+ 0x81000000 __bss2_end__ = (__bss2_start__ + SIZEOF (.bss2))
+ 0x81000000 __bss2_load_end__ = __bss2_end__
+ 0x81000000 __External_SRAM_segment_used_end__ = (ALIGN (__data2_run_end__, 0x4) + SIZEOF (.bss2))
+ 0x00000001 . = ASSERT (((__bss2_end__ >= __External_SRAM_segment_start__) && (__bss2_end__ <= (__External_SRAM_segment_start__ + 0x100000))), error: .bss2 is too large to fit in External_SRAM memory segment)
+ 0x40002000 __vectors_ram_load_start__ = __SRAM_segment_start__
+
+.vectors_ram 0x40002000 0x3c
+ 0x40002000 __vectors_ram_start__ = .
+ *(.vectors_ram .vectors_ram.*)
+ 0x4000203c . = MAX ((__vectors_ram_start__ + 0x3c), .)
+ *fill* 0x40002000 0x3c 00
+ 0x4000203c __vectors_ram_end__ = (__vectors_ram_start__ + SIZEOF (.vectors_ram))
+ 0x4000203c __vectors_ram_load_end__ = __vectors_ram_end__
+ 0x00000001 . = ASSERT (((__vectors_ram_end__ >= __SRAM_segment_start__) && (__vectors_ram_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .vectors_ram is too large to fit in SRAM memory segment)
+ 0x00002000 __vectors_load_start__ = __FLASH_segment_start__
+
+.vectors 0x00002000 0x38
+ 0x00002000 __vectors_start__ = .
+ *(.vectors .vectors.*)
+ .vectors 0x00002000 0x38 ARM Flash Debug/../../obj/cstart.o
+ 0x00002000 _vectors
+ 0x00002038 __vectors_end__ = (__vectors_start__ + SIZEOF (.vectors))
+ 0x00002038 __vectors_load_end__ = __vectors_end__
+ 0x00000001 . = ASSERT (((__vectors_end__ >= __FLASH_segment_start__) && (__vectors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .vectors is too large to fit in FLASH memory segment)
+ 0x00002038 __init_load_start__ = ALIGN (__vectors_end__, 0x4)
+
+.init 0x00002038 0x218
+ 0x00002038 __init_start__ = .
+ *(.init .init.*)
+ *fill* 0x00002038 0x8 00
+ .init 0x00002040 0x210 ARM Flash Debug/../../obj/cstart.o
+ 0x00002040 undef_handler
+ 0x00002044 swi_handler
+ 0x00002048 pabort_handler
+ 0x0000204c dabort_handler
+ 0x00002050 fiq_handler
+ 0x00002054 irq_handler
+ 0x00002060 _start
+ 0x00002060 __start
+ 0x00002178 exit
+ 0x00002250 __init_end__ = (__init_start__ + SIZEOF (.init))
+ 0x00002250 __init_load_end__ = __init_end__
+ 0x00000001 . = ASSERT (((__init_end__ >= __FLASH_segment_start__) && (__init_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .init is too large to fit in FLASH memory segment)
+ 0x00002250 __text_load_start__ = ALIGN (__init_end__, 0x4)
+
+.text 0x00002250 0x1ca8
+ 0x00002250 __text_start__ = .
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+ .glue_7 0x00000000 0x0 linker stubs
+ .glue_7t 0x00000000 0x0 linker stubs
+ .text.BootActivate
+ 0x00002250 0x2c ARM Flash Debug/../../obj/boot.o
+ .text.BootComInit
+ 0x0000227c 0xb8 ARM Flash Debug/../../obj/boot.o
+ 0x0000227c BootComInit
+ .text.BootComCheckActivationRequest
+ 0x00002334 0xe8 ARM Flash Debug/../../obj/boot.o
+ 0x00002334 BootComCheckActivationRequest
+ .text.UartReceiveByte
+ 0x0000241c 0x64 ARM Flash Debug/../../obj/boot.o
+ .text.IrqGetCPSR
+ 0x00002480 0x28 ARM Flash Debug/../../obj/irq.o
+ .text.IrqSetCPSR
+ 0x000024a8 0x24 ARM Flash Debug/../../obj/irq.o
+ .text.IrqInterruptEnable
+ 0x000024cc 0x30 ARM Flash Debug/../../obj/irq.o
+ 0x000024cc IrqInterruptEnable
+ .text.LedInit 0x000024fc 0x3c ARM Flash Debug/../../obj/led.o
+ 0x000024fc LedInit
+ .text.LedToggle
+ 0x00002538 0xa8 ARM Flash Debug/../../obj/led.o
+ 0x00002538 LedToggle
+ .text.main 0x000025e0 0x1c ARM Flash Debug/../../obj/main.o
+ 0x000025e0 main
+ .text.Init 0x000025fc 0x1e8 ARM Flash Debug/../../obj/main.o
+ .text.TimerInit
+ 0x000027e4 0x84 ARM Flash Debug/../../obj/timer.o
+ 0x000027e4 TimerInit
+ .text.TimerUpdate
+ 0x00002868 0x2c ARM Flash Debug/../../obj/timer.o
+ 0x00002868 TimerUpdate
+ .text.TimerSet
+ 0x00002894 0x2c ARM Flash Debug/../../obj/timer.o
+ 0x00002894 TimerSet
+ .text.TimerGet
+ 0x000028c0 0x24 ARM Flash Debug/../../obj/timer.o
+ 0x000028c0 TimerGet
+ .text.TIMER0_ISR
+ 0x000028e4 0x38 ARM Flash Debug/../../obj/vectors.o
+ 0x000028e4 TIMER0_ISR
+ *fill* 0x0000291c 0x4 00
+ .text.libc.memcpy
+ 0x00002920 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2_asm.o)
+ 0x00002920 memcpy
+ .text.libc.strlen
+ 0x00002980 0x90 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2_asm.o)
+ 0x00002980 strlen
+ .text.libc.__vfprintf_int
+ 0x00002a10 0x8c0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ 0x00002a10 __vfprintf_int
+ .text.libc.__ungetc
+ 0x000032d0 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .text.libc.rd_int
+ 0x00003310 0x1cc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .text.libc.__vfscanf_int
+ 0x000034dc 0x5a4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ 0x000034dc __vfscanf_int
+ .text.libc.__getc
+ 0x00003a80 0x4c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003a80 __getc
+ .text.libc.__putc
+ 0x00003acc 0x6c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003acc __putc
+ .text.libc.__print_padding
+ 0x00003b38 0x3c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003b38 __print_padding
+ .text.libc.__pre_padding
+ 0x00003b74 0x28 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003b74 __pre_padding
+ .text.libc.isupper
+ 0x00003b9c 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003b9c isupper
+ .text.libc.islower
+ 0x00003bb0 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003bb0 islower
+ .text.libc.isdigit
+ 0x00003bc4 0x14 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003bc4 isdigit
+ .text.libc.__digit
+ 0x00003bd8 0x54 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003bd8 __digit
+ .text.libc.isspace
+ 0x00003c2c 0x18 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003c2c isspace
+ .text.libdebugio.__do_debug_operation_dcc
+ 0x00003c44 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ 0x00003c44 __do_debug_operation_dcc
+ .text.libc.__debug_io_lock
+ 0x00003c84 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ 0x00003c84 __debug_io_lock
+ .text.libc.__debug_io_unlock
+ 0x00003c88 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ 0x00003c88 __debug_io_unlock
+ *fill* 0x00003c8c 0x4 00
+ .text.libdebugio_dcc.libarm_dcc_read
+ 0x00003c90 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm.o)
+ 0x00003c90 libarm_dcc_read
+ .text.libdebugio_dcc.libarm_dcc_write
+ 0x00003cb0 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm.o)
+ 0x00003cb0 libarm_dcc_write
+ .text.libarm.libarm_run_dcc_port_server
+ 0x00003cd0 0x228 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+ 0x00003cd0 libarm_run_dcc_port_server
+ 0x00003ef8 __text_end__ = (__text_start__ + SIZEOF (.text))
+ 0x00003ef8 __text_load_end__ = __text_end__
+
+.vfp11_veneer 0x00000000 0x0
+ .vfp11_veneer 0x00000000 0x0 linker stubs
+
+.v4_bx 0x00000000 0x0
+ .v4_bx 0x00000000 0x0 linker stubs
+ 0x00000001 . = ASSERT (((__text_end__ >= __FLASH_segment_start__) && (__text_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .text is too large to fit in FLASH memory segment)
+ 0x00003ef8 __dtors_load_start__ = ALIGN (__text_end__, 0x4)
+
+.dtors 0x00003ef8 0x0
+ 0x00003ef8 __dtors_start__ = .
+ *(SORT(.dtors.*))
+ *(.dtors)
+ 0x00003ef8 __dtors_end__ = (__dtors_start__ + SIZEOF (.dtors))
+ 0x00003ef8 __dtors_load_end__ = __dtors_end__
+ 0x00000001 . = ASSERT (((__dtors_end__ >= __FLASH_segment_start__) && (__dtors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .dtors is too large to fit in FLASH memory segment)
+ 0x00003ef8 __ctors_load_start__ = ALIGN (__dtors_end__, 0x4)
+
+.ctors 0x00003ef8 0x0
+ 0x00003ef8 __ctors_start__ = .
+ *(SORT(.ctors.*))
+ *(.ctors)
+ 0x00003ef8 __ctors_end__ = (__ctors_start__ + SIZEOF (.ctors))
+ 0x00003ef8 __ctors_load_end__ = __ctors_end__
+ 0x00000001 . = ASSERT (((__ctors_end__ >= __FLASH_segment_start__) && (__ctors_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .ctors is too large to fit in FLASH memory segment)
+ 0x00003ef8 __rodata_load_start__ = ALIGN (__ctors_end__, 0x4)
+
+.rodata 0x00003ef8 0x24
+ 0x00003ef8 __rodata_start__ = .
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ .rodata 0x00003ef8 0x4 ARM Flash Debug/../../obj/main.o
+ .rodata.libc.__hex_lc
+ 0x00003efc 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003efc __hex_lc
+ .rodata.libc.__hex_uc
+ 0x00003f0c 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x00003f0c __hex_uc
+ 0x00003f1c __rodata_end__ = (__rodata_start__ + SIZEOF (.rodata))
+ 0x00003f1c __rodata_load_end__ = __rodata_end__
+ 0x00000001 . = ASSERT (((__rodata_end__ >= __FLASH_segment_start__) && (__rodata_end__ <= (__FLASH_segment_start__ + 0x40000))), error: .rodata is too large to fit in FLASH memory segment)
+ 0x00003f1c __data_load_start__ = ALIGN (__rodata_end__, 0x4)
+
+.data 0x4000203c 0x0 load address 0x00003f1c
+ 0x4000203c __data_start__ = .
+ *(.data .data.* .gnu.linkonce.d.*)
+ 0x4000203c __data_end__ = (__data_start__ + SIZEOF (.data))
+ 0x00003f1c __data_load_end__ = (__data_load_start__ + SIZEOF (.data))
+ 0x00000001 . = ASSERT ((((__data_load_start__ + SIZEOF (.data)) >= __FLASH_segment_start__) && ((__data_load_start__ + SIZEOF (.data)) <= (__FLASH_segment_start__ + 0x40000))), error: .data is too large to fit in FLASH memory segment)
+
+.data_run 0x4000203c 0x0
+ 0x4000203c __data_run_start__ = .
+ 0x4000203c . = MAX ((__data_run_start__ + SIZEOF (.data)), .)
+ 0x4000203c __data_run_end__ = (__data_run_start__ + SIZEOF (.data_run))
+ 0x4000203c __data_run_load_end__ = __data_run_end__
+ 0x00000001 . = ASSERT (((__data_run_end__ >= __SRAM_segment_start__) && (__data_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .data_run is too large to fit in SRAM memory segment)
+ 0x4000203c __bss_load_start__ = ALIGN (__data_run_end__, 0x4)
+
+.bss 0x4000203c 0x5c
+ 0x4000203c __bss_start__ = .
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ .bss.xcpCtoRxInProgress.785
+ 0x4000203c 0x1 ARM Flash Debug/../../obj/boot.o
+ *fill* 0x4000203d 0x3 00
+ .bss.xcpCtoReqPacket.783
+ 0x40002040 0x44 ARM Flash Debug/../../obj/boot.o
+ .bss.xcpCtoRxLength.784
+ 0x40002084 0x1 ARM Flash Debug/../../obj/boot.o
+ *fill* 0x40002085 0x3 00
+ .bss.timer_counter_last.776
+ 0x40002088 0x4 ARM Flash Debug/../../obj/led.o
+ .bss.led_toggle_state.775
+ 0x4000208c 0x1 ARM Flash Debug/../../obj/led.o
+ *fill* 0x4000208d 0x3 00
+ .bss.millisecond_counter
+ 0x40002090 0x4 ARM Flash Debug/../../obj/timer.o
+ .bss.libc.__format_extender
+ 0x40002094 0x4 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x40002094 __format_extender
+ *(COMMON)
+ 0x40002098 __bss_end__ = (__bss_start__ + SIZEOF (.bss))
+ 0x40002098 __bss_load_end__ = __bss_end__
+ 0x00000001 . = ASSERT (((__bss_end__ >= __SRAM_segment_start__) && (__bss_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .bss is too large to fit in SRAM memory segment)
+ 0x40002098 __non_init_load_start__ = ALIGN (__bss_end__, 0x4)
+
+.non_init 0x40002098 0x0
+ 0x40002098 __non_init_start__ = .
+ *(.non_init .non_init.*)
+ 0x40002098 __non_init_end__ = (__non_init_start__ + SIZEOF (.non_init))
+ 0x40002098 __non_init_load_end__ = __non_init_end__
+ 0x00000001 . = ASSERT (((__non_init_end__ >= __SRAM_segment_start__) && (__non_init_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .non_init is too large to fit in SRAM memory segment)
+ 0x40002098 __heap_load_start__ = ALIGN (__non_init_end__, 0x4)
+
+.heap 0x40002098 0x400
+ 0x40002098 __heap_start__ = .
+ *(.heap .heap.*)
+ 0x40002498 . = ALIGN (MAX ((__heap_start__ + __HEAPSIZE__), .), 0x4)
+ *fill* 0x40002098 0x400 00
+ 0x40002498 __heap_end__ = (__heap_start__ + SIZEOF (.heap))
+ 0x40002498 __heap_load_end__ = __heap_end__
+ 0x00000001 . = ASSERT (((__heap_end__ >= __SRAM_segment_start__) && (__heap_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .heap is too large to fit in SRAM memory segment)
+ 0x40002498 __stack_load_start__ = ALIGN (__heap_end__, 0x4)
+
+.stack 0x40002498 0x400
+ 0x40002498 __stack_start__ = .
+ *(.stack .stack.*)
+ 0x40002898 . = ALIGN (MAX ((__stack_start__ + __STACKSIZE__), .), 0x4)
+ *fill* 0x40002498 0x400 00
+ 0x40002898 __stack_end__ = (__stack_start__ + SIZEOF (.stack))
+ 0x40002898 __stack_load_end__ = __stack_end__
+ 0x00000001 . = ASSERT (((__stack_end__ >= __SRAM_segment_start__) && (__stack_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack is too large to fit in SRAM memory segment)
+ 0x40002898 __stack_irq_load_start__ = ALIGN (__stack_end__, 0x4)
+
+.stack_irq 0x40002898 0x100
+ 0x40002898 __stack_irq_start__ = .
+ *(.stack_irq .stack_irq.*)
+ 0x40002998 . = ALIGN (MAX ((__stack_irq_start__ + __STACKSIZE_IRQ__), .), 0x4)
+ *fill* 0x40002898 0x100 00
+ 0x40002998 __stack_irq_end__ = (__stack_irq_start__ + SIZEOF (.stack_irq))
+ 0x40002998 __stack_irq_load_end__ = __stack_irq_end__
+ 0x00000001 . = ASSERT (((__stack_irq_end__ >= __SRAM_segment_start__) && (__stack_irq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_irq is too large to fit in SRAM memory segment)
+ 0x40002998 __stack_fiq_load_start__ = ALIGN (__stack_irq_end__, 0x4)
+
+.stack_fiq 0x40002998 0x100
+ 0x40002998 __stack_fiq_start__ = .
+ *(.stack_fiq .stack_fiq.*)
+ 0x40002a98 . = ALIGN (MAX ((__stack_fiq_start__ + __STACKSIZE_FIQ__), .), 0x4)
+ *fill* 0x40002998 0x100 00
+ 0x40002a98 __stack_fiq_end__ = (__stack_fiq_start__ + SIZEOF (.stack_fiq))
+ 0x40002a98 __stack_fiq_load_end__ = __stack_fiq_end__
+ 0x00000001 . = ASSERT (((__stack_fiq_end__ >= __SRAM_segment_start__) && (__stack_fiq_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_fiq is too large to fit in SRAM memory segment)
+ 0x40002a98 __stack_svc_load_start__ = ALIGN (__stack_fiq_end__, 0x4)
+
+.stack_svc 0x40002a98 0x100
+ 0x40002a98 __stack_svc_start__ = .
+ *(.stack_svc .stack_svc.*)
+ 0x40002b98 . = ALIGN (MAX ((__stack_svc_start__ + __STACKSIZE_SVC__), .), 0x4)
+ *fill* 0x40002a98 0x100 00
+ 0x40002b98 __stack_svc_end__ = (__stack_svc_start__ + SIZEOF (.stack_svc))
+ 0x40002b98 __stack_svc_load_end__ = __stack_svc_end__
+ 0x00000001 . = ASSERT (((__stack_svc_end__ >= __SRAM_segment_start__) && (__stack_svc_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_svc is too large to fit in SRAM memory segment)
+ 0x40002b98 __stack_abt_load_start__ = ALIGN (__stack_svc_end__, 0x4)
+
+.stack_abt 0x40002b98 0x100
+ 0x40002b98 __stack_abt_start__ = .
+ *(.stack_abt .stack_abt.*)
+ 0x40002c98 . = ALIGN (MAX ((__stack_abt_start__ + __STACKSIZE_ABT__), .), 0x4)
+ *fill* 0x40002b98 0x100 00
+ 0x40002c98 __stack_abt_end__ = (__stack_abt_start__ + SIZEOF (.stack_abt))
+ 0x40002c98 __stack_abt_load_end__ = __stack_abt_end__
+ 0x00000001 . = ASSERT (((__stack_abt_end__ >= __SRAM_segment_start__) && (__stack_abt_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_abt is too large to fit in SRAM memory segment)
+ 0x40002c98 __stack_und_load_start__ = ALIGN (__stack_abt_end__, 0x4)
+
+.stack_und 0x40002c98 0x100
+ 0x40002c98 __stack_und_start__ = .
+ *(.stack_und .stack_und.*)
+ 0x40002d98 . = ALIGN (MAX ((__stack_und_start__ + __STACKSIZE_UND__), .), 0x4)
+ *fill* 0x40002c98 0x100 00
+ 0x40002d98 __stack_und_end__ = (__stack_und_start__ + SIZEOF (.stack_und))
+ 0x40002d98 __stack_und_load_end__ = __stack_und_end__
+ 0x00000001 . = ASSERT (((__stack_und_end__ >= __SRAM_segment_start__) && (__stack_und_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .stack_und is too large to fit in SRAM memory segment)
+ 0x00003f1c __fast_load_start__ = ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4)
+
+.fast 0x40002d98 0x0 load address 0x00003f1c
+ 0x40002d98 __fast_start__ = .
+ *(.fast .fast.*)
+ 0x40002d98 __fast_end__ = (__fast_start__ + SIZEOF (.fast))
+ 0x00003f1c __fast_load_end__ = (__fast_load_start__ + SIZEOF (.fast))
+ 0x00003f1c __FLASH_segment_used_end__ = (ALIGN ((__data_load_start__ + SIZEOF (.data)), 0x4) + SIZEOF (.fast))
+ 0x00000001 . = ASSERT ((((__fast_load_start__ + SIZEOF (.fast)) >= __FLASH_segment_start__) && ((__fast_load_start__ + SIZEOF (.fast)) <= (__FLASH_segment_start__ + 0x40000))), error: .fast is too large to fit in FLASH memory segment)
+
+.fast_run 0x40002d98 0x0
+ 0x40002d98 __fast_run_start__ = .
+ 0x40002d98 . = MAX ((__fast_run_start__ + SIZEOF (.fast)), .)
+ 0x40002d98 __fast_run_end__ = (__fast_run_start__ + SIZEOF (.fast_run))
+ 0x40002d98 __fast_run_load_end__ = __fast_run_end__
+ 0x40002d98 __SRAM_segment_used_end__ = (ALIGN (__stack_und_end__, 0x4) + SIZEOF (.fast_run))
+ 0x00000001 . = ASSERT (((__fast_run_end__ >= __SRAM_segment_start__) && (__fast_run_end__ <= (__SRAM_segment_start__ + 0x4000))), error: .fast_run is too large to fit in SRAM memory segment)
+START GROUP
+LOAD ARM Flash Debug/../../obj/boot.o
+LOAD ARM Flash Debug/../../obj/cstart.o
+LOAD ARM Flash Debug/../../obj/irq.o
+LOAD ARM Flash Debug/../../obj/led.o
+LOAD ARM Flash Debug/../../obj/main.o
+LOAD ARM Flash Debug/../../obj/timer.o
+LOAD ARM Flash Debug/../../obj/vectors.o
+LOAD C:/Users/voorburg/AppData/Local/Rowley Associates Limited/CrossWorks for ARM/packages/lib/liblpc2000_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libcpp_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_targetio_impl_v4t_a_le.a
+LOAD C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a
+END GROUP
+OUTPUT(D:/usr/feaser/software/OpenBLT/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/../bin/demoprog_olimex_lpc_l2294_20mhz.elf elf32-littlearm)
+
+.debug_frame 0x00000000 0x2974
+ .debug_frame 0x00000000 0x98 ARM Flash Debug/../../obj/boot.o
+ .debug_frame 0x00000098 0xc0 ARM Flash Debug/../../obj/irq.o
+ .debug_frame 0x00000158 0x54 ARM Flash Debug/../../obj/led.o
+ .debug_frame 0x000001ac 0x58 ARM Flash Debug/../../obj/main.o
+ .debug_frame 0x00000204 0x94 ARM Flash Debug/../../obj/timer.o
+ .debug_frame 0x00000298 0x40 ARM Flash Debug/../../obj/vectors.o
+ .debug_frame 0x000002d8 0x100 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2_asm.o)
+ .debug_frame 0x000003d8 0x40 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_frame 0x00000418 0x88 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_frame 0x000004a0 0x1148 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_frame 0x000015e8 0x260 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc_asm.o)
+ .debug_frame 0x00001848 0x794 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_frame 0x00001fdc 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_frame 0x0000207c 0x2c0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm.o)
+ .debug_frame 0x0000233c 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+ .debug_frame 0x00002374 0x600 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a(libm_asm.o)
+
+.debug_info 0x00000000 0x17f4
+ .debug_info 0x00000000 0x119 ARM Flash Debug/../../obj/boot.o
+ .debug_info 0x00000119 0xe8 ARM Flash Debug/../../obj/cstart.o
+ .debug_info 0x00000201 0x127 ARM Flash Debug/../../obj/irq.o
+ .debug_info 0x00000328 0x93 ARM Flash Debug/../../obj/led.o
+ .debug_info 0x000003bb 0xb5 ARM Flash Debug/../../obj/main.o
+ .debug_info 0x00000470 0xa9 ARM Flash Debug/../../obj/timer.o
+ .debug_info 0x00000519 0x3b ARM Flash Debug/../../obj/vectors.o
+ .debug_info 0x00000554 0x36 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_info 0x0000058a 0x65 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_info 0x000005ef 0xbcf C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_info 0x000011be 0x533 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_info 0x000016f1 0xcd C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_info 0x000017be 0x36 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_abbrev 0x00000000 0x438
+ .debug_abbrev 0x00000000 0xa2 ARM Flash Debug/../../obj/boot.o
+ .debug_abbrev 0x000000a2 0x12 ARM Flash Debug/../../obj/cstart.o
+ .debug_abbrev 0x000000b4 0x80 ARM Flash Debug/../../obj/irq.o
+ .debug_abbrev 0x00000134 0x5a ARM Flash Debug/../../obj/led.o
+ .debug_abbrev 0x0000018e 0x77 ARM Flash Debug/../../obj/main.o
+ .debug_abbrev 0x00000205 0x80 ARM Flash Debug/../../obj/timer.o
+ .debug_abbrev 0x00000285 0x29 ARM Flash Debug/../../obj/vectors.o
+ .debug_abbrev 0x000002ae 0x25 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_abbrev 0x000002d3 0x43 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_abbrev 0x00000316 0xa0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_abbrev 0x000003b6 0x38 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_abbrev 0x000003ee 0x25 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_abbrev 0x00000413 0x25 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_loc 0x00000000 0x1a69
+ .debug_loc 0x00000000 0xb0 ARM Flash Debug/../../obj/boot.o
+ .debug_loc 0x000000b0 0xdc ARM Flash Debug/../../obj/irq.o
+ .debug_loc 0x0000018c 0x58 ARM Flash Debug/../../obj/led.o
+ .debug_loc 0x000001e4 0x58 ARM Flash Debug/../../obj/main.o
+ .debug_loc 0x0000023c 0xb0 ARM Flash Debug/../../obj/timer.o
+ .debug_loc 0x000002ec 0x2c ARM Flash Debug/../../obj/vectors.o
+ .debug_loc 0x00000318 0x2c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_loc 0x00000344 0x6c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_loc 0x000003b0 0xe79 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_loc 0x00001229 0x820 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_loc 0x00001a49 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_aranges 0x00000000 0x908
+ .debug_aranges
+ 0x00000000 0x38 ARM Flash Debug/../../obj/boot.o
+ .debug_aranges
+ 0x00000038 0x28 ARM Flash Debug/../../obj/cstart.o
+ .debug_aranges
+ 0x00000060 0x40 ARM Flash Debug/../../obj/irq.o
+ .debug_aranges
+ 0x000000a0 0x28 ARM Flash Debug/../../obj/led.o
+ .debug_aranges
+ 0x000000c8 0x28 ARM Flash Debug/../../obj/main.o
+ .debug_aranges
+ 0x000000f0 0x38 ARM Flash Debug/../../obj/timer.o
+ .debug_aranges
+ 0x00000128 0x20 ARM Flash Debug/../../obj/vectors.o
+ .debug_aranges
+ 0x00000148 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_aranges
+ 0x00000168 0x30 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_aranges
+ 0x00000198 0x4d0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_aranges
+ 0x00000668 0x220 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_aranges
+ 0x00000888 0x60 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_aranges
+ 0x000008e8 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_ranges 0x00000000 0x840
+ .debug_ranges 0x00000000 0x28 ARM Flash Debug/../../obj/boot.o
+ .debug_ranges 0x00000028 0x20 ARM Flash Debug/../../obj/cstart.o
+ .debug_ranges 0x00000048 0x30 ARM Flash Debug/../../obj/irq.o
+ .debug_ranges 0x00000078 0x18 ARM Flash Debug/../../obj/led.o
+ .debug_ranges 0x00000090 0x18 ARM Flash Debug/../../obj/main.o
+ .debug_ranges 0x000000a8 0x28 ARM Flash Debug/../../obj/timer.o
+ .debug_ranges 0x000000d0 0x10 ARM Flash Debug/../../obj/vectors.o
+ .debug_ranges 0x000000e0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_ranges 0x000000f0 0x20 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_ranges 0x00000110 0x4c0 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_ranges 0x000005d0 0x210 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_ranges 0x000007e0 0x50 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_ranges 0x00000830 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_line 0x00000000 0x12a0
+ .debug_line 0x00000000 0xec ARM Flash Debug/../../obj/boot.o
+ .debug_line 0x000000ec 0x11e ARM Flash Debug/../../obj/cstart.o
+ .debug_line 0x0000020a 0xe8 ARM Flash Debug/../../obj/irq.o
+ .debug_line 0x000002f2 0xb6 ARM Flash Debug/../../obj/led.o
+ .debug_line 0x000003a8 0xe9 ARM Flash Debug/../../obj/main.o
+ .debug_line 0x00000491 0xd5 ARM Flash Debug/../../obj/timer.o
+ .debug_line 0x00000566 0x9d ARM Flash Debug/../../obj/vectors.o
+ .debug_line 0x00000603 0x75 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .debug_line 0x00000678 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .debug_line 0x000006ec 0x54f C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .debug_line 0x00000c3b 0x56a C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .debug_line 0x000011a5 0x74 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .debug_line 0x00001219 0x87 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.debug_str 0x00000000 0xfc6
+ .debug_str 0x00000000 0x132 ARM Flash Debug/../../obj/boot.o
+ .debug_str 0x00000132 0xe8 ARM Flash Debug/../../obj/irq.o
+ 0x121 (size before relaxing)
+ .debug_str 0x0000021a 0xae ARM Flash Debug/../../obj/led.o
+ 0xda (size before relaxing)
+ .debug_str 0x000002c8 0x8f ARM Flash Debug/../../obj/main.o
+ 0xc0 (size before relaxing)
+ .debug_str 0x00000357 0xb0 ARM Flash Debug/../../obj/timer.o
+ 0xce (size before relaxing)
+ .debug_str 0x00000407 0x75 ARM Flash Debug/../../obj/vectors.o
+ 0x81 (size before relaxing)
+ .debug_str 0x0000047c 0x64 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ 0x70 (size before relaxing)
+ .debug_str 0x000004e0 0x7c C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ 0x88 (size before relaxing)
+ .debug_str 0x0000055c 0x54a C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ 0x5d3 (size before relaxing)
+ .debug_str 0x00000aa6 0x3cc C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ 0x3d8 (size before relaxing)
+ .debug_str 0x00000e72 0xd2 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ 0xde (size before relaxing)
+ .debug_str 0x00000f44 0x82 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+ 0x8e (size before relaxing)
+
+.comment 0x00000000 0x11
+ .comment 0x00000000 0x11 ARM Flash Debug/../../obj/boot.o
+ 0x12 (size before relaxing)
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/irq.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/led.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/main.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/timer.o
+ .comment 0x00000000 0x12 ARM Flash Debug/../../obj/vectors.o
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .comment 0x00000000 0x12 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+
+.ARM.attributes
+ 0x00000000 0x10
+ .ARM.attributes
+ 0x00000000 0x10 ARM Flash Debug/../../obj/boot.o
+ .ARM.attributes
+ 0x00000010 0x10 ARM Flash Debug/../../obj/cstart.o
+ .ARM.attributes
+ 0x00000020 0x10 ARM Flash Debug/../../obj/irq.o
+ .ARM.attributes
+ 0x00000030 0x10 ARM Flash Debug/../../obj/led.o
+ .ARM.attributes
+ 0x00000040 0x10 ARM Flash Debug/../../obj/main.o
+ .ARM.attributes
+ 0x00000050 0x10 ARM Flash Debug/../../obj/timer.o
+ .ARM.attributes
+ 0x00000060 0x10 ARM Flash Debug/../../obj/vectors.o
+ .ARM.attributes
+ 0x00000070 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2_asm.o)
+ .ARM.attributes
+ 0x00000080 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfprintf_int.o)
+ .ARM.attributes
+ 0x00000090 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(__vfscanf_int.o)
+ .ARM.attributes
+ 0x000000a0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc2.o)
+ .ARM.attributes
+ 0x000000b0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_v4t_a_le.a(libc_asm.o)
+ .ARM.attributes
+ 0x000000c0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libdebugio_v4t_a_le.a(libdebugio.o)
+ .ARM.attributes
+ 0x000000d0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libc_user_libc_v4t_a_le.a(user_libc.o)
+ .ARM.attributes
+ 0x000000e0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm.o)
+ .ARM.attributes
+ 0x000000f0 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libarm_v4t_a_le.a(libarm_run_dcc_port_server.o)
+ .ARM.attributes
+ 0x00000100 0x10 C:/Program Files (x86)/Rowley Associates Limited/CrossWorks for ARM 2.1/lib/libm_v4t_a_le.a(libm_asm.o)
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.srec b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.srec
new file mode 100644
index 00000000..0335692a
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/bin/demoprog_olimex_lpc_l2294_20mhz.srec
@@ -0,0 +1,502 @@
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diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c
new file mode 100644
index 00000000..b375cc13
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.c
@@ -0,0 +1,353 @@
+/****************************************************************************************
+| Description: demo program bootloader interface source file
+| File Name: boot.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+** NAME: BootActivate
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Bootloader activation function.
+**
+****************************************************************************************/
+static void BootActivate(void)
+{
+ void (*pEntryFromProgFnc)(void);
+
+ /* set pointer to the address of function EntryFromProg in the bootloader */
+ pEntryFromProgFnc = (void*)0x00000040;
+ /* call EntryFromProg to activate the bootloader. */
+ pEntryFromProgFnc();
+} /*** end of BootActivate ***/
+
+
+#if (BOOT_COM_UART_ENABLE > 0)
+/****************************************************************************************
+* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define UART_DLAB (0x80) /* divisor latch access bit */
+#define UART_MODE_8N1 (0x03) /* 8 data and 1 stop bit, no parity */
+#define UART_FIFO_RX1 (0x07) /* FIFO reset and RX FIFO 1 deep */
+#define UART_RDR (0x01) /* receiver data ready */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static unsigned char UartReceiveByte(unsigned char *data);
+
+
+/****************************************************************************************
+** NAME: BootComInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the UART communication interface
+**
+****************************************************************************************/
+void BootComInit(void)
+{
+ unsigned long baud_reg_value; /* baudrate register value */
+
+ /* configure P0.0 for UART0 Tx and P0.1 for UART0 Rx functionality */
+ PINSEL0 |= 0x05;
+ /* disable UART related interrupt generation. this driver works in polling mode */
+ U0IER = 0;
+ /* clear interrupt id register */
+ U0IIR = 0;
+ /* clear line status register */
+ U0LSR = 0;
+ /* set divisor latch DLAB = 1 so buadrate can be configured */
+ U0LCR = UART_DLAB;
+ /* Baudrate calculation:
+ * y = BOOT_CPU_SYSTEM_SPEED_KHZ * 1000 / 16 / BOOT_COM_UART_BAUDRATE and add
+ * smartness to automatically round the value up/down using the following trick:
+ * y = x/n can round with y = (x + (n + 1)/2 ) / n
+ */
+ baud_reg_value = (((BOOT_CPU_SYSTEM_SPEED_KHZ*1000/16)+ \
+ ((BOOT_COM_UART_BAUDRATE+1)/2))/BOOT_COM_UART_BAUDRATE);
+ /* write the calculated baudrate selector value to the registers */
+ U0DLL = (unsigned char)baud_reg_value;
+ U0DLM = (unsigned char)(baud_reg_value >> 8);
+ /* configure 8 data bits, no parity and 1 stop bit and set DLAB = 0 */
+ U0LCR = UART_MODE_8N1;
+ /* enable and reset transmit and receive FIFO. necessary for UART operation */
+ U0FCR = UART_FIFO_RX1;
+} /*** end of BootComInit ***/
+
+
+/****************************************************************************************
+** NAME: BootComCheckActivationRequest
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
+** bootloader should be activated and, if so, activates it.
+**
+****************************************************************************************/
+void BootComCheckActivationRequest(void)
+{
+ static unsigned char xcpCtoReqPacket[BOOT_COM_UART_RX_MAX_DATA+1];
+ static unsigned char xcpCtoRxLength;
+ static unsigned char xcpCtoRxInProgress = 0;
+
+ /* start of cto packet received? */
+ if (xcpCtoRxInProgress == 0)
+ {
+ /* store the message length when received */
+ if (UartReceiveByte(&xcpCtoReqPacket[0]) == 1)
+ {
+ /* indicate that a cto packet is being received */
+ xcpCtoRxInProgress = 1;
+
+ /* reset packet data count */
+ xcpCtoRxLength = 0;
+ }
+ }
+ else
+ {
+ /* store the next packet byte */
+ if (UartReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
+ {
+ /* increment the packet data count */
+ xcpCtoRxLength++;
+
+ /* check to see if the entire packet was received */
+ if (xcpCtoRxLength == xcpCtoReqPacket[0])
+ {
+ /* done with cto packet reception */
+ xcpCtoRxInProgress = 0;
+
+ /* check if this was an XCP CONNECT command */
+ if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
+ {
+ /* connection request received so start the bootloader */
+ BootActivate();
+ }
+ }
+ }
+ }
+} /*** end of BootComCheckActivationRequest ***/
+
+
+/****************************************************************************************
+** NAME: UartReceiveByte
+** PARAMETER: data pointer to byte where the data is to be stored.
+** RETURN VALUE: 1 if a byte was received, 0 otherwise.
+** DESCRIPTION: Receives a communication interface byte if one is present.
+**
+****************************************************************************************/
+static unsigned char UartReceiveByte(unsigned char *data)
+{
+ /* check if a new byte was received by means of the RDR-bit */
+ if((U0LSR & UART_RDR) != 0)
+ {
+ /* store the received byte */
+ data[0] = U0RBR;
+ /* inform caller of the newly received byte */
+ return 1;
+ }
+ /* inform caller that no new data was received */
+ return 0;
+} /*** end of UartReceiveByte ***/
+#endif /* BOOT_COM_UART_ENABLE > 0 */
+
+
+#if (BOOT_COM_CAN_ENABLE > 0)
+/****************************************************************************************
+* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
+****************************************************************************************/
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define CAN_TBS1 (0x00000004) /* transmit buffer 1 idle */
+#define CAN_TCS1 (0x00000008) /* transmit buffer 1 complete */
+#define CAN_RRB (0x04) /* receive buffer release */
+#define CAN_RBS (0x01) /* receive buffer status */
+#define CAN_TR (0x01) /* transmission request */
+#define CAN_STB1 (0x20) /* select tx buffer 1 for transmit */
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+typedef struct t_can_bus_timing
+{
+ unsigned char tseg1; /* CAN time segment 1 */
+ unsigned char tseg2; /* CAN time segment 2 */
+} tCanBusTiming; /* bus timing structure type */
+
+
+/****************************************************************************************
+* Local constant declarations
+****************************************************************************************/
+/* According to the CAN protocol 1 bit-time can be made up of between 8..25 time quanta
+ * (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC always being 1.
+ * The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) * 100%. This array contains
+ * possible and valid time quanta configurations with a sample point between 68..78%.
+ */
+static const tCanBusTiming canTiming[] =
+{ /* TQ | TSEG1 | TSEG2 | SP */
+ /* ------------------------- */
+ { 5, 2 }, /* 8 | 5 | 2 | 75% */
+ { 6, 2 }, /* 9 | 6 | 2 | 78% */
+ { 6, 3 }, /* 10 | 6 | 3 | 70% */
+ { 7, 3 }, /* 11 | 7 | 3 | 73% */
+ { 8, 3 }, /* 12 | 8 | 3 | 75% */
+ { 9, 3 }, /* 13 | 9 | 3 | 77% */
+ { 9, 4 }, /* 14 | 9 | 4 | 71% */
+ { 10, 4 }, /* 15 | 10 | 4 | 73% */
+ { 11, 4 }, /* 16 | 11 | 4 | 75% */
+ { 12, 4 }, /* 17 | 12 | 4 | 76% */
+ { 12, 5 }, /* 18 | 12 | 5 | 72% */
+ { 13, 5 }, /* 19 | 13 | 5 | 74% */
+ { 14, 5 }, /* 20 | 14 | 5 | 75% */
+ { 15, 5 }, /* 21 | 15 | 5 | 76% */
+ { 15, 6 }, /* 22 | 15 | 6 | 73% */
+ { 16, 6 }, /* 23 | 16 | 6 | 74% */
+ { 16, 7 }, /* 24 | 16 | 7 | 71% */
+ { 16, 8 } /* 25 | 16 | 8 | 68% */
+};
+
+
+/****************************************************************************************
+** NAME: CanGetSpeedConfig
+** PARAMETER: baud The desired baudrate in kbps. Valid values are 10..1000.
+** btr Pointer to where the value for register CANxBTR will be stored.
+** RETURN VALUE: 1 if the CAN bustiming register values were found, 0 otherwise.
+** DESCRIPTION: Search algorithm to match the desired baudrate to a possible bus
+** timing configuration.
+**
+****************************************************************************************/
+static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned long *btr)
+{
+ unsigned short prescaler;
+ unsigned char cnt;
+
+ /* loop through all possible time quanta configurations to find a match */
+ for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
+ {
+ if ((BOOT_CPU_SYSTEM_SPEED_KHZ % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
+ {
+ /* compute the prescaler that goes with this TQ configuration */
+ prescaler = BOOT_CPU_SYSTEM_SPEED_KHZ/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
+
+ /* make sure the prescaler is valid */
+ if ( (prescaler > 0) && (prescaler <= 1024) )
+ {
+ /* store the prescaler and bustiming register value */
+ *btr = prescaler - 1;
+ *btr |= ((canTiming[cnt].tseg2 - 1) << 20) | ((canTiming[cnt].tseg1 - 1) << 16);
+ /* found a good bus timing configuration */
+ return 1;
+ }
+ }
+ }
+ /* could not find a good bus timing configuration */
+ return 0;
+} /*** end of CanGetSpeedConfig ***/
+
+
+/****************************************************************************************
+** NAME: BootComInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the CAN communication interface
+**
+****************************************************************************************/
+void BootComInit(void)
+{
+ unsigned long btr_reg_value;
+
+ /* configure acceptance filter for bypass mode so it receives all messages */
+ CANAFMR = 0x00000002L;
+ /* take CAN controller offline and go into reset mode */
+ CAN1MOD = 1;
+ /* disable all interrupts. driver only needs to work in polling mode */
+ CAN1IER = 0;
+ /* reset CAN controller status */
+ CAN1GSR = 0;
+ /* configure the bittiming */
+ if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &btr_reg_value) == 1)
+ {
+ /* write the bittiming configuration to the register */
+ CAN1BTR = btr_reg_value;
+ }
+ /* enter normal operating mode and synchronize to the CAN bus */
+ CAN1MOD = 0;
+} /*** end of BootComInit ***/
+
+
+/****************************************************************************************
+** NAME: BootComCheckActivationRequest
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Receives the CONNECT request from the host, which indicates that the
+** bootloader should be activated and, if so, activates it.
+**
+****************************************************************************************/
+void BootComCheckActivationRequest(void)
+{
+ unsigned char data[2];
+
+ /* check if a new message was received */
+ if ((CAN1SR & CAN_RBS) == 0)
+ {
+ return;
+ }
+ /* see if this is the message identifier that we are interested in */
+ if (CAN1RID != BOOT_COM_CAN_RX_MSG_ID)
+ {
+ return;
+ }
+ /* store the message data */
+ data[0] = (unsigned char)CAN1RDA;
+ data[1] = (unsigned char)(CAN1RDA >> 8);
+ /* release the receive buffer */
+ CAN1CMR = CAN_RRB;
+ /* check if this was an XCP CONNECT command */
+ if ((data[0] == 0xff) && (data[1] == 0x00))
+ {
+ /* connection request received so start the bootloader */
+ BootActivate();
+ }
+} /*** end of BootComCheckActivationRequest ***/
+#endif /* BOOT_COM_CAN_ENABLE > 0 */
+
+
+/*********************************** end of boot.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h
new file mode 100644
index 00000000..92789052
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/boot.h
@@ -0,0 +1,42 @@
+/****************************************************************************************
+| Description: demo program bootloader interface header file
+| File Name: boot.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef BOOT_H
+#define BOOT_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void BootComInit(void);
+void BootComCheckActivationRequest(void);
+
+
+#endif /* BOOT_H */
+/*********************************** end of boot.h *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s
new file mode 100644
index 00000000..35f28e4b
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/cstart.s
@@ -0,0 +1,415 @@
+/*****************************************************************************
+ * Copyright (c) 2001, 2002 Rowley Associates Limited. *
+ * *
+ * This file may be distributed under the terms of the License Agreement *
+ * provided with this software. *
+ * *
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Preprocessor Definitions
+ * ------------------------
+ * APP_ENTRY_POINT
+ *
+ * Defines the application entry point function, if undefined this setting
+ * defaults to "main".
+ *
+ * INITIALIZE_STACKS
+ *
+ * If defined, the contents of the stacks will be initialized to a the
+ * value 0xCC.
+ *
+ * INITIALIZE_SECONDARY_SECTIONS
+ *
+ * If defined, the .text2, .data2 and .bss2 sections will be initialized.
+ *
+ * SUPERVISOR_START
+ *
+ * If defined, the application will start up in supervisor mode. If
+ * undefined the application will start up in system mode.
+ *
+ * FULL_LIBRARY
+ *
+ * If defined then
+ * - argc, argv are setup by the debug_getargs.
+ * - the exit symbol is defined and executes on return from main.
+ * - the exit symbol calls destructors, atexit functions and then debug_exit.
+ *
+ * If not defined then
+ * - argc and argv are zero.
+ * - the exit symbol is defined, executes on return from main and loops
+ *
+ *****************************************************************************/
+
+ .section .vectors, "ax"
+ .code 32
+ .align 0
+ .global _vectors
+ .global reset_handler
+
+/*****************************************************************************
+ * Exception Vectors *
+ *****************************************************************************/
+_vectors:
+ ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
+ ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
+ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
+ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
+ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
+ .word 0xB9205F88 /* boot loader checksum */
+ ldr pc, [pc, #-0xFF0] /* irq handler */
+ ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */
+
+reset_handler_address:
+ .word _start
+undef_handler_address:
+ .word undef_handler
+swi_handler_address:
+ .word swi_handler
+pabort_handler_address:
+ .word pabort_handler
+dabort_handler_address:
+ .word dabort_handler
+fiq_handler_address:
+ .word fiq_handler
+
+ .section .init, "ax"
+ .code 32
+ .align 0
+
+/******************************************************************************
+ * *
+ * Default exception handlers *
+ * *
+ ******************************************************************************/
+/******************************************************************************
+ * *
+ * Default exception handlers *
+ * These are declared weak symbols so they can be redefined in user code. *
+ * *
+ ******************************************************************************/
+undef_handler:
+ b undef_handler
+
+swi_handler:
+ b swi_handler
+
+pabort_handler:
+ b pabort_handler
+
+dabort_handler:
+ b dabort_handler
+
+fiq_handler:
+ b fiq_handler
+
+irq_handler:
+ b irq_handler
+
+ .weak undef_handler, swi_handler, pabort_handler, dabort_handler, fiq_handler, irq_handler
+
+ .section .init, "ax"
+ .code 32
+ .align 4
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+
+ .weak _start
+ .global __start
+ .global __gccmain
+ .extern APP_ENTRY_POINT
+ .global exit
+
+/*****************************************************************************
+ * Function : _start *
+ * Description : Main entry point and startup code for C system. *
+ *****************************************************************************/
+_start:
+__start:
+ mrs r0, cpsr
+ bic r0, r0, #0x1F
+
+ /* Setup stacks */
+ orr r1, r0, #0x1B /* Undefined mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_und_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x17 /* Abort mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_abt_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x12 /* IRQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_irq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x11 /* FIQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_fiq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x13 /* Supervisor mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_svc_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+#ifdef SUPERVISOR_START
+ /* Start application in supervisor mode */
+ ldr r1, =__stack_end__ /* Setup user/system mode stack */
+#ifdef __ARM_EABI__
+ bic r1, r1, #0x7
+#endif
+ mov r2, sp
+ stmfd r2!, {r1}
+ ldmfd r2, {sp}^
+#else
+ /* Start application in system mode */
+ orr r1, r0, #0x1F /* System mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+#endif
+
+#ifdef INITIALIZE_STACKS
+ mov r2, #0xCC
+ ldr r0, =__stack_und_start__
+ ldr r1, =__stack_und_end__
+ bl memory_set
+ ldr r0, =__stack_abt_start__
+ ldr r1, =__stack_abt_end__
+ bl memory_set
+ ldr r0, =__stack_irq_start__
+ ldr r1, =__stack_irq_end__
+ bl memory_set
+ ldr r0, =__stack_fiq_start__
+ ldr r1, =__stack_fiq_end__
+ bl memory_set
+ ldr r0, =__stack_svc_start__
+ ldr r1, =__stack_svc_end__
+ bl memory_set
+ ldr r0, =__stack_start__
+ ldr r1, =__stack_end__
+ bl memory_set
+#endif
+
+ /* Copy initialised memory sections into RAM (if necessary). */
+ ldr r0, =__data_load_start__
+ ldr r1, =__data_start__
+ ldr r2, =__data_end__
+ bl memory_copy
+ ldr r0, =__text_load_start__
+ ldr r1, =__text_start__
+ ldr r2, =__text_end__
+ bl memory_copy
+ ldr r0, =__fast_load_start__
+ ldr r1, =__fast_start__
+ ldr r2, =__fast_end__
+ bl memory_copy
+ ldr r0, =__ctors_load_start__
+ ldr r1, =__ctors_start__
+ ldr r2, =__ctors_end__
+ bl memory_copy
+ ldr r0, =__dtors_load_start__
+ ldr r1, =__dtors_start__
+ ldr r2, =__dtors_end__
+ bl memory_copy
+ ldr r0, =__rodata_load_start__
+ ldr r1, =__rodata_start__
+ ldr r2, =__rodata_end__
+ bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__data2_load_start__
+ ldr r1, =__data2_start__
+ ldr r2, =__data2_end__
+ bl memory_copy
+ ldr r0, =__text2_load_start__
+ ldr r1, =__text2_start__
+ ldr r2, =__text2_end__
+ bl memory_copy
+ ldr r0, =__rodata2_load_start__
+ ldr r1, =__rodata2_start__
+ ldr r2, =__rodata2_end__
+ bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Zero the bss. */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+ bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__bss2_start__
+ ldr r1, =__bss2_end__
+ mov r2, #0
+ bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Initialise the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ sub r1, r1, r0
+ cmp r1, #8
+ movge r2, #0
+ strge r2, [r0], #+4
+ strge r1, [r0]
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop:
+ cmp r0, r1
+ beq ctor_end
+ ldr r2, [r0], #+4
+ stmfd sp!, {r0-r1}
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldmfd sp!, {r0-r1}
+ b ctor_loop
+ctor_end:
+
+ .type start, function
+start:
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ mov r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldr r1, =args
+#else
+ mov r0, #0
+ mov r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+exit:
+#ifdef FULL_LIBRARY
+ mov r5, r0 // save the exit parameter/return result
+
+ /* Call destructors */
+ ldr r0, =__dtors_start__
+ ldr r1, =__dtors_end__
+dtor_loop:
+ cmp r0, r1
+ beq dtor_end
+ ldr r2, [r0], #+4
+ stmfd sp!, {r0-r1}
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldmfd sp!, {r0-r1}
+ b dtor_loop
+dtor_end:
+
+ /* Call atexit functions */
+ ldr r2, =_execute_at_exit_fns
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+ /* Call debug_exit with return result/exit parameter */
+ mov r0, r5
+ ldr r2, =debug_exit
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+#endif
+
+ /* Returned from application entry point/debug_exit, loop forever. */
+exit_loop:
+ b exit_loop
+
+memory_copy:
+ cmp r0, r1
+ moveq pc, lr
+ subs r2, r2, r1
+ moveq pc, lr
+
+ /* if either pointer or length is not word aligned then byte copy */
+ orr r3, r0, r1
+ orr r3, r3, r2
+ tst r3, #0x3
+ bne 2f
+ /* word copy */
+1:
+ ldr r3, [r0], #+4
+ str r3, [r1], #+4
+ subs r2, r2, #4
+ bne 1b
+ mov pc, lr
+ /* byte copy */
+2:
+ ldrb r3, [r0], #+1
+ strb r3, [r1], #+1
+ subs r2, r2, #1
+ bne 2b
+ mov pc, lr
+
+memory_set:
+ cmp r0, r1
+ moveq pc, lr
+ strb r2, [r0], #1
+ b memory_set
+
+#ifdef FULL_LIBRARY
+ .bss
+args:
+ .space ARGSSPACE
+#endif
+
+ /* Setup attibutes of stack and heap sections so they don't take up unnecessary room in the elf file */
+ .section .stack, "wa", %nobits
+ .section .stack_abt, "wa", %nobits
+ .section .stack_irq, "wa", %nobits
+ .section .stack_fiq, "wa", %nobits
+ .section .stack_svc, "wa", %nobits
+ .section .stack_und, "wa", %nobits
+ .section .heap, "wa", %nobits
+
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h
new file mode 100644
index 00000000..1a21e96e
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/header.h
@@ -0,0 +1,46 @@
+/****************************************************************************************
+| Description: generic header file
+| File Name: header.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef HEADER_H
+#define HEADER_H
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "../Boot/config.h" /* bootloader configuration */
+#include "lpc2294.h" /* CPU register definitions */
+#include "boot.h" /* bootloader interface driver */
+#include "irq.h" /* IRQ driver */
+#include "led.h" /* LED driver */
+#include "timer.h" /* Timer driver */
+
+
+#endif /* HEADER_H */
+/*********************************** end of header.h ***********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp
new file mode 100644
index 00000000..d502c976
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzp
@@ -0,0 +1,40 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs
new file mode 100644
index 00000000..aeea24ef
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/lpc2294_crossworks.hzs
@@ -0,0 +1,60 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt
new file mode 100644
index 00000000..87eb22da
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/ide/readme.txt
@@ -0,0 +1,4 @@
+Integrated Development Environment
+----------------------------------
+Rowleys CrossWorks was used as the editor during the development of this software program. This directory contains
+the CrossWorks project and solution files. More info is available at: http://www.rowley.co.uk/
\ No newline at end of file
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c
new file mode 100644
index 00000000..650763a1
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.c
@@ -0,0 +1,140 @@
+/****************************************************************************************
+| Description: IRQ driver source file
+| File Name: irq.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Local data definitions
+****************************************************************************************/
+static unsigned long oldInterruptStatus; /* used for global interrupt en/disable */
+static unsigned char interruptNesting = 0; /* used for global interrupt en/disable */
+
+
+/****************************************************************************************
+** NAME: IrqGetCPSR
+** PARAMETER: none
+** RETURN VALUE: CPSR value
+** DESCRIPTION: Obtains current value of CPSR CPU register.
+** NOTE: Derived from a sample by R O Software that is Copyright 2004,
+** R O SoftWare, and can be used for hobby or commercial purposes.
+**
+****************************************************************************************/
+static unsigned long IrqGetCPSR(void)
+{
+ unsigned long retval;
+ __asm__ volatile (" mrs %0, cpsr" : "=r" (retval) : /* no inputs */ );
+ return retval;
+} /*** end of IrqGetCPSR ***/
+
+
+/****************************************************************************************
+** NAME: IrqSetCPSR
+** PARAMETER: CPSR value
+** RETURN VALUE: none
+** DESCRIPTION: Update value of CPSR CPU register.
+** NOTE: Derived from a sample by R O Software that is Copyright 2004,
+** R O SoftWare, and can be used for hobby or commercial purposes.
+**
+****************************************************************************************/
+static void IrqSetCPSR(unsigned long val)
+{
+ __asm__ volatile (" msr cpsr, %0" : /* no outputs */ : "r" (val) );
+} /*** end of IrqSetCPSR ***/
+
+
+/****************************************************************************************
+** NAME: IrqInterruptEnable
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Enables the generation IRQ interrupts. Typically called once during
+** software startup after completion of the initialization.
+**
+****************************************************************************************/
+void IrqInterruptEnable(void)
+{
+ unsigned _cpsr;
+
+ _cpsr = IrqGetCPSR();
+ IrqSetCPSR(_cpsr & ~0x00000080);
+} /*** end of IrqInterruptEnable ***/
+
+
+/****************************************************************************************
+** NAME: HwInterruptDisable
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Disables the generation IRQ interrupts and stores information on
+** whether or not the interrupts were already disabled before explicitly
+** disabling them with this function. Normally used as a pair together
+** with IrqInterruptRestore during a critical section.
+**
+****************************************************************************************/
+void IrqInterruptDisable(void)
+{
+ unsigned long _cpsr;
+
+ if (interruptNesting == 0)
+ {
+ _cpsr = IrqGetCPSR();
+ IrqSetCPSR(_cpsr | 0x00000080);
+ oldInterruptStatus = _cpsr;
+ }
+ interruptNesting++;
+} /*** end of IrqInterruptDisable ***/
+
+
+/****************************************************************************************
+** NAME: IrqInterruptRestore
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Restore the generation IRQ interrupts to the setting it had prior to
+** calling IrqInterruptDisable. Normally used as a pair together with
+** IrqInterruptDisable during a critical section.
+**
+****************************************************************************************/
+void IrqInterruptRestore(void)
+{
+ unsigned _cpsr;
+
+ interruptNesting--;
+ if (interruptNesting == 0)
+ {
+ _cpsr = IrqGetCPSR();
+ IrqSetCPSR((_cpsr & ~0x00000080) | (oldInterruptStatus & 0x00000080));
+ }
+} /*** end of IrqInterruptRestore ***/
+
+
+/*********************************** end of irq.c **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h
new file mode 100644
index 00000000..9f12faf4
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/irq.h
@@ -0,0 +1,43 @@
+/****************************************************************************************
+| Description: IRQ driver header file
+| File Name: irq.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef IRQ_H
+#define IRQ_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void IrqInterruptEnable(void);
+void IrqInterruptDisable(void);
+void IrqInterruptRestore(void);
+
+
+#endif /* IRQ_H */
+/*********************************** end of irq.h **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c
new file mode 100644
index 00000000..7e579999
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.c
@@ -0,0 +1,100 @@
+/****************************************************************************************
+| Description: LED driver source file
+| File Name: led.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define LED_TOGGLE_MS (500) /* toggle interval time in millisecodns */
+
+
+/****************************************************************************************
+** NAME: LedInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the LED.
+**
+****************************************************************************************/
+void LedInit(void)
+{
+ /* set io pins for led P1.23 */
+ IO1DIR |= 0x00800000;
+ /* turn the led off */
+ IO1SET = 0x00800000;
+} /*** end of LedInit ***/
+
+
+/****************************************************************************************
+** NAME: LedToggle
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Toggles the LED at a fixed time interval.
+**
+****************************************************************************************/
+void LedToggle(void)
+{
+ static unsigned char led_toggle_state = 0;
+ static unsigned long timer_counter_last = 0;
+ unsigned long timer_counter_now;
+
+ /* check if toggle interval time passed */
+ timer_counter_now = TimerGet();
+ if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
+ {
+ /* not yet time to toggle */
+ return;
+ }
+
+ /* determine toggle action */
+ if (led_toggle_state == 0)
+ {
+ led_toggle_state = 1;
+ /* turn the LED on */
+ IO1CLR = 0x00800000;
+ }
+ else
+ {
+ led_toggle_state = 0;
+ /* turn the LED off */
+ IO1SET = 0x00800000;
+ }
+
+ /* store toggle time to determine next toggle interval */
+ timer_counter_last = timer_counter_now;
+} /*** end of LedToggle ***/
+
+
+/*********************************** end of led.c **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h
new file mode 100644
index 00000000..f69b6a44
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/led.h
@@ -0,0 +1,42 @@
+/****************************************************************************************
+| Description: LED driver header file
+| File Name: led.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef LED_H
+#define LED_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void LedInit(void);
+void LedToggle(void);
+
+
+#endif /* LED_H */
+/*********************************** end of led.h **************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h
new file mode 100644
index 00000000..209015fb
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/lpc2294.h
@@ -0,0 +1,409 @@
+/****************************************************************************************
+| Description: NXP LPC2294 register definitions
+| File Name: lpc2294.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef LPC2294_H
+#define LPC2294_H
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+/* EXTERNAL MEMORY CONTROLLER (EMC) */
+#define BCFG0 (*((volatile unsigned long *) 0xFFE00000)) /* lpc22xx only */
+#define BCFG1 (*((volatile unsigned long *) 0xFFE00004)) /* lpc22xx only */
+#define BCFG2 (*((volatile unsigned long *) 0xFFE00008)) /* lpc22xx only */
+#define BCFG3 (*((volatile unsigned long *) 0xFFE0000C)) /* lpc22xx only */
+
+/* External Interrupts */
+#define EXTINT (*((volatile unsigned char *) 0xE01FC140))
+#define EXTWAKE (*((volatile unsigned char *) 0xE01FC144))
+#define EXTMODE (*((volatile unsigned char *) 0xE01FC148)) /* no in lpc210x*/
+#define EXTPOLAR (*((volatile unsigned char *) 0xE01FC14C)) /* no in lpc210x*/
+
+/* SMemory mapping control. */
+#define MEMMAP (*((volatile unsigned long *) 0xE01FC040))
+
+/* Phase Locked Loop (PLL) */
+#define PLLCON (*((volatile unsigned char *) 0xE01FC080))
+#define PLLCFG (*((volatile unsigned char *) 0xE01FC084))
+#define PLLSTAT (*((volatile unsigned short*) 0xE01FC088))
+#define PLLFEED (*((volatile unsigned char *) 0xE01FC08C))
+
+/* Power Control */
+#define PCON (*((volatile unsigned char *) 0xE01FC0C0))
+#define PCONP (*((volatile unsigned long *) 0xE01FC0C4))
+
+/* VPB Divider */
+#define VPBDIV (*((volatile unsigned char *) 0xE01FC100))
+
+/* Memory Accelerator Module (MAM) */
+#define MAMCR (*((volatile unsigned char *) 0xE01FC000))
+#define MAMTIM (*((volatile unsigned char *) 0xE01FC004))
+
+/* Vectored Interrupt Controller (VIC) */
+#define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000))
+#define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004))
+#define VICRawIntr (*((volatile unsigned long *) 0xFFFFF008))
+#define VICIntSelect (*((volatile unsigned long *) 0xFFFFF00C))
+#define VICIntEnable (*((volatile unsigned long *) 0xFFFFF010))
+#define VICIntEnClr (*((volatile unsigned long *) 0xFFFFF014))
+#define VICSoftInt (*((volatile unsigned long *) 0xFFFFF018))
+#define VICSoftIntClear (*((volatile unsigned long *) 0xFFFFF01C))
+#define VICProtection (*((volatile unsigned long *) 0xFFFFF020))
+#define VICVectAddr (*((volatile unsigned long *) 0xFFFFF030))
+#define VICDefVectAddr (*((volatile unsigned long *) 0xFFFFF034))
+#define VICVectAddr0 (*((volatile unsigned long *) 0xFFFFF100))
+#define VICVectAddr1 (*((volatile unsigned long *) 0xFFFFF104))
+#define VICVectAddr2 (*((volatile unsigned long *) 0xFFFFF108))
+#define VICVectAddr3 (*((volatile unsigned long *) 0xFFFFF10C))
+#define VICVectAddr4 (*((volatile unsigned long *) 0xFFFFF110))
+#define VICVectAddr5 (*((volatile unsigned long *) 0xFFFFF114))
+#define VICVectAddr6 (*((volatile unsigned long *) 0xFFFFF118))
+#define VICVectAddr7 (*((volatile unsigned long *) 0xFFFFF11C))
+#define VICVectAddr8 (*((volatile unsigned long *) 0xFFFFF120))
+#define VICVectAddr9 (*((volatile unsigned long *) 0xFFFFF124))
+#define VICVectAddr10 (*((volatile unsigned long *) 0xFFFFF128))
+#define VICVectAddr11 (*((volatile unsigned long *) 0xFFFFF12C))
+#define VICVectAddr12 (*((volatile unsigned long *) 0xFFFFF130))
+#define VICVectAddr13 (*((volatile unsigned long *) 0xFFFFF134))
+#define VICVectAddr14 (*((volatile unsigned long *) 0xFFFFF138))
+#define VICVectAddr15 (*((volatile unsigned long *) 0xFFFFF13C))
+#define VICVectCntl0 (*((volatile unsigned long *) 0xFFFFF200))
+#define VICVectCntl1 (*((volatile unsigned long *) 0xFFFFF204))
+#define VICVectCntl2 (*((volatile unsigned long *) 0xFFFFF208))
+#define VICVectCntl3 (*((volatile unsigned long *) 0xFFFFF20C))
+#define VICVectCntl4 (*((volatile unsigned long *) 0xFFFFF210))
+#define VICVectCntl5 (*((volatile unsigned long *) 0xFFFFF214))
+#define VICVectCntl6 (*((volatile unsigned long *) 0xFFFFF218))
+#define VICVectCntl7 (*((volatile unsigned long *) 0xFFFFF21C))
+#define VICVectCntl8 (*((volatile unsigned long *) 0xFFFFF220))
+#define VICVectCntl9 (*((volatile unsigned long *) 0xFFFFF224))
+#define VICVectCntl10 (*((volatile unsigned long *) 0xFFFFF228))
+#define VICVectCntl11 (*((volatile unsigned long *) 0xFFFFF22C))
+#define VICVectCntl12 (*((volatile unsigned long *) 0xFFFFF230))
+#define VICVectCntl13 (*((volatile unsigned long *) 0xFFFFF234))
+#define VICVectCntl14 (*((volatile unsigned long *) 0xFFFFF238))
+#define VICVectCntl15 (*((volatile unsigned long *) 0xFFFFF23C))
+
+/* Pin Connect Block */
+#define PINSEL0 (*((volatile unsigned long *) 0xE002C000))
+#define PINSEL1 (*((volatile unsigned long *) 0xE002C004))
+#define PINSEL2 (*((volatile unsigned long *) 0xE002C014)) /* no in lpc210x*/
+
+/* General Purpose Input/Output (GPIO) */
+#define IOPIN (*((volatile unsigned long *) 0xE0028000)) /* lpc210x only */
+#define IOSET (*((volatile unsigned long *) 0xE0028004)) /* lpc210x only */
+#define IODIR (*((volatile unsigned long *) 0xE0028008)) /* lpc210x only */
+#define IOCLR (*((volatile unsigned long *) 0xE002800C)) /* lpc210x only */
+
+#define IO0PIN (*((volatile unsigned long *) 0xE0028000)) /* no in lpc210x*/
+#define IO0SET (*((volatile unsigned long *) 0xE0028004)) /* no in lpc210x*/
+#define IO0DIR (*((volatile unsigned long *) 0xE0028008)) /* no in lpc210x*/
+#define IO0CLR (*((volatile unsigned long *) 0xE002800C)) /* no in lpc210x*/
+
+#define IO1PIN (*((volatile unsigned long *) 0xE0028010)) /* no in lpc210x*/
+#define IO1SET (*((volatile unsigned long *) 0xE0028014)) /* no in lpc210x*/
+#define IO1DIR (*((volatile unsigned long *) 0xE0028018)) /* no in lpc210x*/
+#define IO1CLR (*((volatile unsigned long *) 0xE002801C)) /* no in lpc210x*/
+
+#define IO2PIN (*((volatile unsigned long *) 0xE0028020)) /* lpc22xx only */
+#define IO2SET (*((volatile unsigned long *) 0xE0028024)) /* lpc22xx only */
+#define IO2DIR (*((volatile unsigned long *) 0xE0028028)) /* lpc22xx only */
+#define IO2CLR (*((volatile unsigned long *) 0xE002802C)) /* lpc22xx only */
+
+#define IO3PIN (*((volatile unsigned long *) 0xE0028030)) /* lpc22xx only */
+#define IO3SET (*((volatile unsigned long *) 0xE0028034)) /* lpc22xx only */
+#define IO3DIR (*((volatile unsigned long *) 0xE0028038)) /* lpc22xx only */
+#define IO3CLR (*((volatile unsigned long *) 0xE002803C)) /* lpc22xx only */
+
+/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
+#define U0RBR (*((volatile unsigned char *) 0xE000C000))
+#define U0THR (*((volatile unsigned char *) 0xE000C000))
+#define U0IER (*((volatile unsigned char *) 0xE000C004))
+#define U0IIR (*((volatile unsigned char *) 0xE000C008))
+#define U0FCR (*((volatile unsigned char *) 0xE000C008))
+#define U0LCR (*((volatile unsigned char *) 0xE000C00C))
+#define U0LSR (*((volatile unsigned char *) 0xE000C014))
+#define U0SCR (*((volatile unsigned char *) 0xE000C01C))
+#define U0DLL (*((volatile unsigned char *) 0xE000C000))
+#define U0DLM (*((volatile unsigned char *) 0xE000C004))
+
+/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
+#define U1RBR (*((volatile unsigned char *) 0xE0010000))
+#define U1THR (*((volatile unsigned char *) 0xE0010000))
+#define U1IER (*((volatile unsigned char *) 0xE0010004))
+#define U1IIR (*((volatile unsigned char *) 0xE0010008))
+#define U1FCR (*((volatile unsigned char *) 0xE0010008))
+#define U1LCR (*((volatile unsigned char *) 0xE001000C))
+#define U1MCR (*((volatile unsigned char *) 0xE0010010))
+#define U1LSR (*((volatile unsigned char *) 0xE0010014))
+#define U1MSR (*((volatile unsigned char *) 0xE0010018))
+#define U1SCR (*((volatile unsigned char *) 0xE001001C))
+#define U1DLL (*((volatile unsigned char *) 0xE0010000))
+#define U1DLM (*((volatile unsigned char *) 0xE0010004))
+
+/* I2C (8/16 bit data bus) */
+#define I2CONSET (*((volatile unsigned long *) 0xE001C000))
+#define I2STAT (*((volatile unsigned long *) 0xE001C004))
+#define I2DAT (*((volatile unsigned long *) 0xE001C008))
+#define I2ADR (*((volatile unsigned long *) 0xE001C00C))
+#define I2SCLH (*((volatile unsigned long *) 0xE001C010))
+#define I2SCLL (*((volatile unsigned long *) 0xE001C014))
+#define I2CONCLR (*((volatile unsigned long *) 0xE001C018))
+
+/* SPI (Serial Peripheral Interface) */
+ /* only for lpc210x*/
+#define SPI_SPCR (*((volatile unsigned char *) 0xE0020000))
+#define SPI_SPSR (*((volatile unsigned char *) 0xE0020004))
+#define SPI_SPDR (*((volatile unsigned char *) 0xE0020008))
+#define SPI_SPCCR (*((volatile unsigned char *) 0xE002000C))
+#define SPI_SPINT (*((volatile unsigned char *) 0xE002001C))
+
+#define S0PCR (*((volatile unsigned char *) 0xE0020000)) /* no in lpc210x*/
+#define S0PSR (*((volatile unsigned char *) 0xE0020004)) /* no in lpc210x*/
+#define S0PDR (*((volatile unsigned char *) 0xE0020008)) /* no in lpc210x*/
+#define S0PCCR (*((volatile unsigned char *) 0xE002000C)) /* no in lpc210x*/
+#define S0PINT (*((volatile unsigned char *) 0xE002001C)) /* no in lpc210x*/
+
+#define S1PCR (*((volatile unsigned char *) 0xE0030000)) /* no in lpc210x*/
+#define S1PSR (*((volatile unsigned char *) 0xE0030004)) /* no in lpc210x*/
+#define S1PDR (*((volatile unsigned char *) 0xE0030008)) /* no in lpc210x*/
+#define S1PCCR (*((volatile unsigned char *) 0xE003000C)) /* no in lpc210x*/
+#define S1PINT (*((volatile unsigned char *) 0xE003001C)) /* no in lpc210x*/
+
+/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
+#define CAN1MOD (*((volatile unsigned long *) 0xE0044000)) /* All CAN Parts */
+#define CAN1CMR (*((volatile unsigned long *) 0xE0044004)) /* All CAN Parts */
+#define CAN1GSR (*((volatile unsigned long *) 0xE0044008)) /* All CAN Parts */
+#define CAN1ICR (*((volatile unsigned long *) 0xE004400C)) /* All CAN Parts */
+#define CAN1IER (*((volatile unsigned long *) 0xE0044010)) /* All CAN Parts */
+#define CAN1BTR (*((volatile unsigned long *) 0xE0044014)) /* All CAN Parts */
+#define CAN1EWL (*((volatile unsigned long *) 0xE0044018)) /* All CAN Parts */
+#define CAN1SR (*((volatile unsigned long *) 0xE004401C)) /* All CAN Parts */
+#define CAN1RFS (*((volatile unsigned long *) 0xE0044020)) /* All CAN Parts */
+#define CAN1RID (*((volatile unsigned long *) 0xE0044024)) /* All CAN Parts */
+#define CAN1RDA (*((volatile unsigned long *) 0xE0044028)) /* All CAN Parts */
+#define CAN1RDB (*((volatile unsigned long *) 0xE004402C)) /* All CAN Parts */
+#define CAN1TFI1 (*((volatile unsigned long *) 0xE0044030)) /* All CAN Parts */
+#define CAN1TID1 (*((volatile unsigned long *) 0xE0044034)) /* All CAN Parts */
+#define CAN1TDA1 (*((volatile unsigned long *) 0xE0044038)) /* All CAN Parts */
+#define CAN1TDB1 (*((volatile unsigned long *) 0xE004403C)) /* All CAN Parts */
+#define CAN1TFI2 (*((volatile unsigned long *) 0xE0044040)) /* All CAN Parts */
+#define CAN1TID2 (*((volatile unsigned long *) 0xE0044044)) /* All CAN Parts */
+#define CAN1TDA2 (*((volatile unsigned long *) 0xE0044048)) /* All CAN Parts */
+#define CAN1TDB2 (*((volatile unsigned long *) 0xE004404C)) /* All CAN Parts */
+#define CAN1TFI3 (*((volatile unsigned long *) 0xE0044050)) /* All CAN Parts */
+#define CAN1TID3 (*((volatile unsigned long *) 0xE0044054)) /* All CAN Parts */
+#define CAN1TDA3 (*((volatile unsigned long *) 0xE0044058)) /* All CAN Parts */
+#define CAN1TDB3 (*((volatile unsigned long *) 0xE004405C)) /* All CAN Parts */
+
+#define CAN2MOD (*((volatile unsigned long *) 0xE0048000)) /* All CAN Parts */
+#define CAN2CMR (*((volatile unsigned long *) 0xE0048004)) /* All CAN Parts */
+#define CAN2GSR (*((volatile unsigned long *) 0xE0048008)) /* All CAN Parts */
+#define CAN2ICR (*((volatile unsigned long *) 0xE004800C)) /* All CAN Parts */
+#define CAN2IER (*((volatile unsigned long *) 0xE0048010)) /* All CAN Parts */
+#define CAN2BTR (*((volatile unsigned long *) 0xE0048014)) /* All CAN Parts */
+#define CAN2EWL (*((volatile unsigned long *) 0xE0048018)) /* All CAN Parts */
+#define CAN2SR (*((volatile unsigned long *) 0xE004801C)) /* All CAN Parts */
+#define CAN2RFS (*((volatile unsigned long *) 0xE0048020)) /* All CAN Parts */
+#define CAN2RID (*((volatile unsigned long *) 0xE0048024)) /* All CAN Parts */
+#define CAN2RDA (*((volatile unsigned long *) 0xE0048028)) /* All CAN Parts */
+#define CAN2RDB (*((volatile unsigned long *) 0xE004802C)) /* All CAN Parts */
+#define CAN2TFI1 (*((volatile unsigned long *) 0xE0048030)) /* All CAN Parts */
+#define CAN2TID1 (*((volatile unsigned long *) 0xE0048034)) /* All CAN Parts */
+#define CAN2TDA1 (*((volatile unsigned long *) 0xE0048038)) /* All CAN Parts */
+#define CAN2TDB1 (*((volatile unsigned long *) 0xE004803C)) /* All CAN Parts */
+#define CAN2TFI2 (*((volatile unsigned long *) 0xE0048040)) /* All CAN Parts */
+#define CAN2TID2 (*((volatile unsigned long *) 0xE0048044)) /* All CAN Parts */
+#define CAN2TDA2 (*((volatile unsigned long *) 0xE0048048)) /* All CAN Parts */
+#define CAN2TDB2 (*((volatile unsigned long *) 0xE004804C)) /* All CAN Parts */
+#define CAN2TFI3 (*((volatile unsigned long *) 0xE0048050)) /* All CAN Parts */
+#define CAN2TID3 (*((volatile unsigned long *) 0xE0048054)) /* All CAN Parts */
+#define CAN2TDA3 (*((volatile unsigned long *) 0xE0048058)) /* All CAN Parts */
+#define CAN2TDB3 (*((volatile unsigned long *) 0xE004805C)) /* All CAN Parts */
+
+#define CAN3MOD (*((volatile unsigned long *) 0xE004C000)) /* lpc2194\lpc2294 only */
+#define CAN3CMR (*((volatile unsigned long *) 0xE004C004)) /* lpc2194\lpc2294 only */
+#define CAN3GSR (*((volatile unsigned long *) 0xE004C008)) /* lpc2194\lpc2294 only */
+#define CAN3ICR (*((volatile unsigned long *) 0xE004C00C)) /* lpc2194\lpc2294 only */
+#define CAN3IER (*((volatile unsigned long *) 0xE004C010)) /* lpc2194\lpc2294 only */
+#define CAN3BTR (*((volatile unsigned long *) 0xE004C014)) /* lpc2194\lpc2294 only */
+#define CAN3EWL (*((volatile unsigned long *) 0xE004C018)) /* lpc2194\lpc2294 only */
+#define CAN3SR (*((volatile unsigned long *) 0xE004C01C)) /* lpc2194\lpc2294 only */
+#define CAN3RFS (*((volatile unsigned long *) 0xE004C020)) /* lpc2194\lpc2294 only */
+#define CAN3RID (*((volatile unsigned long *) 0xE004C024)) /* lpc2194\lpc2294 only */
+#define CAN3RDA (*((volatile unsigned long *) 0xE004C028)) /* lpc2194\lpc2294 only */
+#define CAN3RDB (*((volatile unsigned long *) 0xE004C02C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI1 (*((volatile unsigned long *) 0xE004C030)) /* lpc2194\lpc2294 only */
+#define CAN3TID1 (*((volatile unsigned long *) 0xE004C034)) /* lpc2194\lpc2294 only */
+#define CAN3TDA1 (*((volatile unsigned long *) 0xE004C038)) /* lpc2194\lpc2294 only */
+#define CAN3TDB1 (*((volatile unsigned long *) 0xE004C03C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI2 (*((volatile unsigned long *) 0xE004C040)) /* lpc2194\lpc2294 only */
+#define CAN3TID2 (*((volatile unsigned long *) 0xE004C044)) /* lpc2194\lpc2294 only */
+#define CAN3TDA2 (*((volatile unsigned long *) 0xE004C048)) /* lpc2194\lpc2294 only */
+#define CAN3TDB2 (*((volatile unsigned long *) 0xE004C04C)) /* lpc2194\lpc2294 only */
+#define CAN3TFI3 (*((volatile unsigned long *) 0xE004C050)) /* lpc2194\lpc2294 only */
+#define CAN3TID3 (*((volatile unsigned long *) 0xE004C054)) /* lpc2194\lpc2294 only */
+#define CAN3TDA3 (*((volatile unsigned long *) 0xE004C058)) /* lpc2194\lpc2294 only */
+#define CAN3TDB3 (*((volatile unsigned long *) 0xE004C05C)) /* lpc2194\lpc2294 only */
+
+#define CAN4MOD (*((volatile unsigned long *) 0xE0050000)) /* lpc2194\lpc2294 only */
+#define CAN4CMR (*((volatile unsigned long *) 0xE0050004)) /* lpc2194\lpc2294 only */
+#define CAN4GSR (*((volatile unsigned long *) 0xE0050008)) /* lpc2194\lpc2294 only */
+#define CAN4ICR (*((volatile unsigned long *) 0xE005000C)) /* lpc2194\lpc2294 only */
+#define CAN4IER (*((volatile unsigned long *) 0xE0050010)) /* lpc2194\lpc2294 only */
+#define CAN4BTR (*((volatile unsigned long *) 0xE0050014)) /* lpc2194\lpc2294 only */
+#define CAN4EWL (*((volatile unsigned long *) 0xE0050018)) /* lpc2194\lpc2294 only */
+#define CAN4SR (*((volatile unsigned long *) 0xE005001C)) /* lpc2194\lpc2294 only */
+#define CAN4RFS (*((volatile unsigned long *) 0xE0050020)) /* lpc2194\lpc2294 only */
+#define CAN4RID (*((volatile unsigned long *) 0xE0050024)) /* lpc2194\lpc2294 only */
+#define CAN4RDA (*((volatile unsigned long *) 0xE0050028)) /* lpc2194\lpc2294 only */
+#define CAN4RDB (*((volatile unsigned long *) 0xE005002C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI1 (*((volatile unsigned long *) 0xE0050030)) /* lpc2194\lpc2294 only */
+#define CAN4TID1 (*((volatile unsigned long *) 0xE0050034)) /* lpc2194\lpc2294 only */
+#define CAN4TDA1 (*((volatile unsigned long *) 0xE0050038)) /* lpc2194\lpc2294 only */
+#define CAN4TDB1 (*((volatile unsigned long *) 0xE005003C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI2 (*((volatile unsigned long *) 0xE0050040)) /* lpc2194\lpc2294 only */
+#define CAN4TID2 (*((volatile unsigned long *) 0xE0050044)) /* lpc2194\lpc2294 only */
+#define CAN4TDA2 (*((volatile unsigned long *) 0xE0050048)) /* lpc2194\lpc2294 only */
+#define CAN4TDB2 (*((volatile unsigned long *) 0xE005004C)) /* lpc2194\lpc2294 only */
+#define CAN4TFI3 (*((volatile unsigned long *) 0xE0050050)) /* lpc2194\lpc2294 only */
+#define CAN4TID3 (*((volatile unsigned long *) 0xE0050054)) /* lpc2194\lpc2294 only */
+#define CAN4TDA3 (*((volatile unsigned long *) 0xE0050058)) /* lpc2194\lpc2294 only */
+#define CAN4TDB3 (*((volatile unsigned long *) 0xE005005C)) /* lpc2194\lpc2294 only */
+
+
+#define CANTxSR (*((volatile unsigned long *) 0xE0040000)) /* ALL CAN Parts */
+#define CANRxSR (*((volatile unsigned long *) 0xE0040004)) /* ALL CAN Parts */
+#define CANMSR (*((volatile unsigned long *) 0xE0040008)) /* ALL CAN Parts */
+
+#define CANAFMR (*((volatile unsigned char *) 0xE003C000)) /* ALL CAN Parts */
+#define CANSFF_sa (*((volatile unsigned short*) 0xE003C004)) /* ALL CAN Parts */
+#define CANSFF_GRP_sa (*((volatile unsigned short*) 0xE003C008)) /* ALL CAN Parts */
+#define CANEFF_sa (*((volatile unsigned short*) 0xE003C00C)) /* ALL CAN Parts */
+#define CANEFF_GRP_sa (*((volatile unsigned short*) 0xE003C010)) /* ALL CAN Parts */
+#define CANENDofTable (*((volatile unsigned short*) 0xE003C014)) /* ALL CAN Parts */
+#define CANLUTerrAd (*((volatile unsigned short*) 0xE003C018)) /* ALL CAN Parts */
+#define CANLUTerr (*((volatile unsigned char *) 0xE003C01C)) /* ALL CAN Parts */
+
+
+/* Timer 0 */
+#define T0IR (*((volatile unsigned long *) 0xE0004000))
+#define T0TCR (*((volatile unsigned long *) 0xE0004004))
+#define T0TC (*((volatile unsigned long *) 0xE0004008))
+#define T0PR (*((volatile unsigned long *) 0xE000400C))
+#define T0PC (*((volatile unsigned long *) 0xE0004010))
+#define T0MCR (*((volatile unsigned long *) 0xE0004014))
+#define T0MR0 (*((volatile unsigned long *) 0xE0004018))
+#define T0MR1 (*((volatile unsigned long *) 0xE000401C))
+#define T0MR2 (*((volatile unsigned long *) 0xE0004020))
+#define T0MR3 (*((volatile unsigned long *) 0xE0004024))
+#define T0CCR (*((volatile unsigned long *) 0xE0004028))
+#define T0CR0 (*((volatile unsigned long *) 0xE000402C))
+#define T0CR1 (*((volatile unsigned long *) 0xE0004030))
+#define T0CR2 (*((volatile unsigned long *) 0xE0004034))
+#define T0CR3 (*((volatile unsigned long *) 0xE0004038))
+#define T0EMR (*((volatile unsigned long *) 0xE000403C))
+
+/* Timer 1 */
+#define T1IR (*((volatile unsigned long *) 0xE0008000))
+#define T1TCR (*((volatile unsigned long *) 0xE0008004))
+#define T1TC (*((volatile unsigned long *) 0xE0008008))
+#define T1PR (*((volatile unsigned long *) 0xE000800C))
+#define T1PC (*((volatile unsigned long *) 0xE0008010))
+#define T1MCR (*((volatile unsigned long *) 0xE0008014))
+#define T1MR0 (*((volatile unsigned long *) 0xE0008018))
+#define T1MR1 (*((volatile unsigned long *) 0xE000801C))
+#define T1MR2 (*((volatile unsigned long *) 0xE0008020))
+#define T1MR3 (*((volatile unsigned long *) 0xE0008024))
+#define T1CCR (*((volatile unsigned long *) 0xE0008028))
+#define T1CR0 (*((volatile unsigned long *) 0xE000802C))
+#define T1CR1 (*((volatile unsigned long *) 0xE0008030))
+#define T1CR2 (*((volatile unsigned long *) 0xE0008034))
+#define T1CR3 (*((volatile unsigned long *) 0xE0008038))
+#define T1EMR (*((volatile unsigned long *) 0xE000803C))
+
+/* Pulse Width Modulator (PWM) */
+#define PWMIR (*((volatile unsigned long *) 0xE0014000))
+#define PWMTCR (*((volatile unsigned long *) 0xE0014004))
+#define PWMTC (*((volatile unsigned long *) 0xE0014008))
+#define PWMPR (*((volatile unsigned long *) 0xE001400C))
+#define PWMPC (*((volatile unsigned long *) 0xE0014010))
+#define PWMMCR (*((volatile unsigned long *) 0xE0014014))
+#define PWMMR0 (*((volatile unsigned long *) 0xE0014018))
+#define PWMMR1 (*((volatile unsigned long *) 0xE001401C))
+#define PWMMR2 (*((volatile unsigned long *) 0xE0014020))
+#define PWMMR3 (*((volatile unsigned long *) 0xE0014024))
+#define PWMMR4 (*((volatile unsigned long *) 0xE0014040))
+#define PWMMR5 (*((volatile unsigned long *) 0xE0014044))
+#define PWMMR6 (*((volatile unsigned long *) 0xE0014048))
+#define PWMPCR (*((volatile unsigned long *) 0xE001404C))
+#define PWMLER (*((volatile unsigned long *) 0xE0014050))
+
+/* A/D CONVERTER */
+#define ADCR (*((volatile unsigned long *) 0xE0034000)) /* no in lpc210x*/
+#define ADDR (*((volatile unsigned long *) 0xE0034004)) /* no in lpc210x*/
+
+/* Real Time Clock */
+#define ILR (*((volatile unsigned char *) 0xE0024000))
+#define CTC (*((volatile unsigned short*) 0xE0024004))
+#define CCR (*((volatile unsigned char *) 0xE0024008))
+#define CIIR (*((volatile unsigned char *) 0xE002400C))
+#define AMR (*((volatile unsigned char *) 0xE0024010))
+#define CTIME0 (*((volatile unsigned long *) 0xE0024014))
+#define CTIME1 (*((volatile unsigned long *) 0xE0024018))
+#define CTIME2 (*((volatile unsigned long *) 0xE002401C))
+#define SEC (*((volatile unsigned char *) 0xE0024020))
+#define MIN (*((volatile unsigned char *) 0xE0024024))
+#define HOUR (*((volatile unsigned char *) 0xE0024028))
+#define DOM (*((volatile unsigned char *) 0xE002402C))
+#define DOW (*((volatile unsigned char *) 0xE0024030))
+#define DOY (*((volatile unsigned short*) 0xE0024034))
+#define MONTH (*((volatile unsigned char *) 0xE0024038))
+#define YEAR (*((volatile unsigned short*) 0xE002403C))
+#define ALSEC (*((volatile unsigned char *) 0xE0024060))
+#define ALMIN (*((volatile unsigned char *) 0xE0024064))
+#define ALHOUR (*((volatile unsigned char *) 0xE0024068))
+#define ALDOM (*((volatile unsigned char *) 0xE002406C))
+#define ALDOW (*((volatile unsigned char *) 0xE0024070))
+#define ALDOY (*((volatile unsigned short*) 0xE0024074))
+#define ALMON (*((volatile unsigned char *) 0xE0024078))
+#define ALYEAR (*((volatile unsigned short*) 0xE002407C))
+#define PREINT (*((volatile unsigned short*) 0xE0024080))
+#define PREFRAC (*((volatile unsigned short*) 0xE0024084))
+
+/* Watchdog */
+#define WDMOD (*((volatile unsigned char *) 0xE0000000))
+#define WDTC (*((volatile unsigned long *) 0xE0000004))
+#define WDFEED (*((volatile unsigned char *) 0xE0000008))
+#define WDTV (*((volatile unsigned long *) 0xE000000C))
+
+#endif /* LPC2294_H */
+/*********************************** end of lpc2294.h **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c
new file mode 100644
index 00000000..1c4b590a
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/main.c
@@ -0,0 +1,151 @@
+/****************************************************************************************
+| Description: demo program application source file
+| File Name: main.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static void Init(void);
+
+
+/****************************************************************************************
+** NAME: main
+** PARAMETER: none
+** RETURN VALUE: program return code
+** DESCRIPTION: This is the entry point for the bootloader application and is called
+** by the reset interrupt vector after the C-startup routines executed.
+**
+****************************************************************************************/
+int main(void)
+{
+ /* initialize the microcontroller */
+ Init();
+
+ /* initialize the bootloader interface */
+ BootComInit();
+
+ /* start the infinite program loop */
+ while (1)
+ {
+ /* toggle LED with a fixed frequency */
+ LedToggle();
+
+ /* check for bootloader activation request */
+ BootComCheckActivationRequest();
+ }
+
+ /* program should never get here */
+ return 0;
+} /*** end of main ***/
+
+
+/****************************************************************************************
+** NAME: Init
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the microcontroller. The Fpll is set to 60MHz and Fvpb is
+** configured equal to Fpll. The GPIO pin of the status LED is configured
+** as digital output.
+**
+****************************************************************************************/
+static void Init(void)
+{
+ unsigned char m_sel; /* pll multiplier register value */
+ unsigned char pll_dividers[] = { 1, 2, 4, 8 }; /* possible pll dividers */
+ unsigned char p_sel_cnt; /* loop counter to find p_sel */
+ unsigned long f_cco; /* current controller oscillator */
+
+ /* calculate MSEL: M = round(Fcclk / Fosc) */
+ m_sel = (BOOT_CPU_SYSTEM_SPEED_KHZ + ((BOOT_CPU_XTAL_SPEED_KHZ+1)/2)) / \
+ BOOT_CPU_XTAL_SPEED_KHZ;
+ /* value for the PLLCFG register is -1 */
+ m_sel--;
+
+ /* find PSEL value so that Fcco(= Fcclk * 2 * P) is in the 156000..320000 kHz range. */
+ for (p_sel_cnt=0; p_sel_cnt= 156000) && (f_cco <= 320000) )
+ {
+ /* found a valid pll divider value */
+ break;
+ }
+ }
+
+ /* set multiplier and divider values */
+ PLLCFG = (p_sel_cnt << 5) | m_sel;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* enable the PLL */
+ PLLCON = 0x1;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* wait for the PLL to lock to set frequency */
+ while(!(PLLSTAT & 0x400)) { ; }
+ /* connect the PLL as the clock source */
+ PLLCON = 0x3;
+ PLLFEED = 0xAA;
+ PLLFEED = 0x55;
+ /* enable MAM and set number of clocks used for Flash memory fetch. Recommended:
+ * Fcclk >= 60 MHz: 4 clock cycles
+ * Fcclk >= 40 MHz: 3 clock cycles
+ * Fcclk >= 20 MHz: 2 clock cycles
+ * Fcclk < 20 MHz: 1 clock cycle
+ */
+ MAMCR = 0x0;
+#if (BOOT_CPU_SYSTEM_SPEED_KHZ >= 60)
+ MAMTIM = 4;
+#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 40)
+ MAMTIM = 3;
+#elif (BOOT_CPU_SYSTEM_SPEED_KHZ >= 20)
+ MAMTIM = 2;
+#else
+ MAMTIM = 1;
+#endif
+ MAMCR = 0x2;
+ /* setting peripheral Clock (pclk) to System Clock (cclk) */
+ VPBDIV = 0x1;
+ /* init the led driver */
+ LedInit();
+ /* init the timer driver */
+ TimerInit();
+ /* enable IRQ's */
+ IrqInterruptEnable();
+} /*** end of Init ***/
+
+
+/*********************************** end of main.c *************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x
new file mode 100644
index 00000000..cb5d5a1c
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/memory.x
@@ -0,0 +1,356 @@
+MEMORY
+{
+ UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+ AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000
+ VPB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000
+ BANK3 (wx) : ORIGIN = 0x83000000, LENGTH = 0x01000000
+ BANK2 (wx) : ORIGIN = 0x82000000, LENGTH = 0x01000000
+ External_SRAM (wx) : ORIGIN = 0x81000000, LENGTH = 0x00100000
+ External_FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00400000
+ SRAM (wx) : ORIGIN = 0x40000200, LENGTH = 0x00003CE0
+ FLASH (rx) : ORIGIN = 0x00002000, LENGTH = 0x0003E000
+}
+
+
+SECTIONS
+{
+ __AHB_Peripherals_segment_start__ = 0xffe00000;
+ __AHB_Peripherals_segment_end__ = 0x00000000;
+ __VPB_Peripherals_segment_start__ = 0xe0000000;
+ __VPB_Peripherals_segment_end__ = 0xe0200000;
+ __BANK3_segment_start__ = 0x83000000;
+ __BANK3_segment_end__ = 0x84000000;
+ __BANK2_segment_start__ = 0x82000000;
+ __BANK2_segment_end__ = 0x83000000;
+ __External_SRAM_segment_start__ = 0x81000000;
+ __External_SRAM_segment_end__ = 0x81100000;
+ __External_FLASH_segment_start__ = 0x80000000;
+ __External_FLASH_segment_end__ = 0x80400000;
+ __SRAM_segment_start__ = 0x40002000;
+ __SRAM_segment_end__ = 0x40003EE0;
+ __FLASH_segment_start__ = 0x00002000;
+ __FLASH_segment_end__ = 0x00040000;
+
+ __STACKSIZE__ = 1024;
+ __STACKSIZE_IRQ__ = 256;
+ __STACKSIZE_FIQ__ = 256;
+ __STACKSIZE_SVC__ = 256;
+ __STACKSIZE_ABT__ = 256;
+ __STACKSIZE_UND__ = 256;
+ __HEAPSIZE__ = 1024;
+
+ __text2_load_start__ = ALIGN(__External_FLASH_segment_start__ , 4);
+ .text2 ALIGN(__External_FLASH_segment_start__ , 4) : AT(ALIGN(__External_FLASH_segment_start__ , 4))
+ {
+ __text2_start__ = .;
+ *(.text2 .text2.*)
+ }
+ __text2_end__ = __text2_start__ + SIZEOF(.text2);
+
+ __text2_load_end__ = __text2_end__;
+
+ . = ASSERT(__text2_end__ >= __External_FLASH_segment_start__ && __text2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .text2 is too large to fit in External_FLASH memory segment");
+
+ __rodata2_load_start__ = ALIGN(__text2_end__ , 4);
+ .rodata2 ALIGN(__text2_end__ , 4) : AT(ALIGN(__text2_end__ , 4))
+ {
+ __rodata2_start__ = .;
+ *(.rodata2 .rodata2.*)
+ }
+ __rodata2_end__ = __rodata2_start__ + SIZEOF(.rodata2);
+
+ __rodata2_load_end__ = __rodata2_end__;
+
+ . = ASSERT(__rodata2_end__ >= __External_FLASH_segment_start__ && __rodata2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .rodata2 is too large to fit in External_FLASH memory segment");
+
+ __data2_load_start__ = ALIGN(__rodata2_end__ , 4);
+ .data2 ALIGN(__External_SRAM_segment_start__ , 4) : AT(ALIGN(__rodata2_end__ , 4))
+ {
+ __data2_start__ = .;
+ *(.data2 .data2.*)
+ }
+ __data2_end__ = __data2_start__ + SIZEOF(.data2);
+
+ __data2_load_end__ = __data2_load_start__ + SIZEOF(.data2);
+
+ __External_FLASH_segment_used_end__ = ALIGN(__rodata2_end__ , 4) + SIZEOF(.data2);
+
+ . = ASSERT((__data2_load_start__ + SIZEOF(.data2)) >= __External_FLASH_segment_start__ && (__data2_load_start__ + SIZEOF(.data2)) <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .data2 is too large to fit in External_FLASH memory segment");
+
+ .data2_run ALIGN(__External_SRAM_segment_start__ , 4) (NOLOAD) :
+ {
+ __data2_run_start__ = .;
+ . = MAX(__data2_run_start__ + SIZEOF(.data2), .);
+ }
+ __data2_run_end__ = __data2_run_start__ + SIZEOF(.data2_run);
+
+ __data2_run_load_end__ = __data2_run_end__;
+
+ . = ASSERT(__data2_run_end__ >= __External_SRAM_segment_start__ && __data2_run_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .data2_run is too large to fit in External_SRAM memory segment");
+
+ __bss2_load_start__ = ALIGN(__data2_run_end__ , 4);
+ .bss2 ALIGN(__data2_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data2_run_end__ , 4))
+ {
+ __bss2_start__ = .;
+ *(.bss2 .bss2.*)
+ }
+ __bss2_end__ = __bss2_start__ + SIZEOF(.bss2);
+
+ __bss2_load_end__ = __bss2_end__;
+
+ __External_SRAM_segment_used_end__ = ALIGN(__data2_run_end__ , 4) + SIZEOF(.bss2);
+
+ . = ASSERT(__bss2_end__ >= __External_SRAM_segment_start__ && __bss2_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .bss2 is too large to fit in External_SRAM memory segment");
+
+ __vectors_ram_load_start__ = __SRAM_segment_start__;
+ .vectors_ram __SRAM_segment_start__ (NOLOAD) : AT(__SRAM_segment_start__)
+ {
+ __vectors_ram_start__ = .;
+ *(.vectors_ram .vectors_ram.*)
+ . = MAX(__vectors_ram_start__ + 0x0000003C , .);
+ }
+ __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
+
+ __vectors_ram_load_end__ = __vectors_ram_end__;
+
+ . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
+
+ __vectors_load_start__ = __FLASH_segment_start__;
+ .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
+ {
+ __vectors_start__ = .;
+ *(.vectors .vectors.*)
+ }
+ __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+ __vectors_load_end__ = __vectors_end__;
+
+ . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+ __init_load_start__ = ALIGN(__vectors_end__ , 4);
+ .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+ {
+ __init_start__ = .;
+ *(.init .init.*)
+ }
+ __init_end__ = __init_start__ + SIZEOF(.init);
+
+ __init_load_end__ = __init_end__;
+
+ . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
+
+ __text_load_start__ = ALIGN(__init_end__ , 4);
+ .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+ {
+ __text_start__ = .;
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+ }
+ __text_end__ = __text_start__ + SIZEOF(.text);
+
+ __text_load_end__ = __text_end__;
+
+ . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
+
+ __dtors_load_start__ = ALIGN(__text_end__ , 4);
+ .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+ {
+ __dtors_start__ = .;
+ KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+ }
+ __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+ __dtors_load_end__ = __dtors_end__;
+
+ . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+ __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+ .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+ {
+ __ctors_start__ = .;
+ KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+ }
+ __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+ __ctors_load_end__ = __ctors_end__;
+
+ . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+ __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+ .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+ {
+ __rodata_start__ = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ }
+ __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+ __rodata_load_end__ = __rodata_end__;
+
+ . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+ __data_load_start__ = ALIGN(__rodata_end__ , 4);
+ .data ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+ {
+ __data_start__ = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ }
+ __data_end__ = __data_start__ + SIZEOF(.data);
+
+ __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+ . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
+
+ .data_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
+ {
+ __data_run_start__ = .;
+ . = MAX(__data_run_start__ + SIZEOF(.data), .);
+ }
+ __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+ __data_run_load_end__ = __data_run_end__;
+
+ . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .data_run is too large to fit in SRAM memory segment");
+
+ __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+ .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+ {
+ __bss_start__ = .;
+ *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+ }
+ __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+ __bss_load_end__ = __bss_end__;
+
+ . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .bss is too large to fit in SRAM memory segment");
+
+ __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+ .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+ {
+ __non_init_start__ = .;
+ *(.non_init .non_init.*)
+ }
+ __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+ __non_init_load_end__ = __non_init_end__;
+
+ . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .non_init is too large to fit in SRAM memory segment");
+
+ __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+ .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+ {
+ __heap_start__ = .;
+ *(.heap .heap.*)
+ . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+ }
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ __heap_load_end__ = __heap_end__;
+
+ . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .heap is too large to fit in SRAM memory segment");
+
+ __stack_load_start__ = ALIGN(__heap_end__ , 4);
+ .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+ {
+ __stack_start__ = .;
+ *(.stack .stack.*)
+ . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+ }
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ __stack_load_end__ = __stack_end__;
+
+ . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack is too large to fit in SRAM memory segment");
+
+ __stack_irq_load_start__ = ALIGN(__stack_end__ , 4);
+ .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq .stack_irq.*)
+ . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4);
+ }
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ __stack_irq_load_end__ = __stack_irq_end__;
+
+ . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_irq is too large to fit in SRAM memory segment");
+
+ __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4);
+ .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_irq_end__ , 4))
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq .stack_fiq.*)
+ . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4);
+ }
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ __stack_fiq_load_end__ = __stack_fiq_end__;
+
+ . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_fiq is too large to fit in SRAM memory segment");
+
+ __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4);
+ .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_fiq_end__ , 4))
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc .stack_svc.*)
+ . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4);
+ }
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ __stack_svc_load_end__ = __stack_svc_end__;
+
+ . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_svc is too large to fit in SRAM memory segment");
+
+ __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4);
+ .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_svc_end__ , 4))
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt .stack_abt.*)
+ . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4);
+ }
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ __stack_abt_load_end__ = __stack_abt_end__;
+
+ . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_abt is too large to fit in SRAM memory segment");
+
+ __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4);
+ .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_abt_end__ , 4))
+ {
+ __stack_und_start__ = .;
+ *(.stack_und .stack_und.*)
+ . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4);
+ }
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ __stack_und_load_end__ = __stack_und_end__;
+
+ . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_und is too large to fit in SRAM memory segment");
+
+ __fast_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
+ .fast ALIGN(__stack_und_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
+ {
+ __fast_start__ = .;
+ *(.fast .fast.*)
+ }
+ __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+ __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+ __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.fast);
+
+ . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
+
+ .fast_run ALIGN(__stack_und_end__ , 4) (NOLOAD) :
+ {
+ __fast_run_start__ = .;
+ . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+ }
+ __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+ __fast_run_load_end__ = __fast_run_end__;
+
+ __SRAM_segment_used_end__ = ALIGN(__stack_und_end__ , 4) + SIZEOF(.fast_run);
+
+ . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .fast_run is too large to fit in SRAM memory segment");
+
+}
+
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c
new file mode 100644
index 00000000..6aa579af
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.c
@@ -0,0 +1,119 @@
+/****************************************************************************************
+| Description: Timer driver source file
+| File Name: timer.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+static unsigned long millisecond_counter;
+
+
+/****************************************************************************************
+* External functions
+****************************************************************************************/
+extern void TIMER0_ISR(void);
+
+
+/****************************************************************************************
+** NAME: TimerInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the timer.
+**
+****************************************************************************************/
+void TimerInit(void)
+{
+ /* configure timer0 as 1 ms software output compare */
+ T0MR0 = BOOT_CPU_SYSTEM_SPEED_KHZ-1;
+ /* enable interrupt and automatic reset upon compare */
+ T0MCR = 0x01 | 0x02;
+ /* enable the output compare */
+ T0TCR = 0x01;
+ /* set the interrupt service routine for the output compare event */
+ VICVectAddr0 = (unsigned long)TIMER0_ISR;
+ /* connect vectored IRQ slot 0 to Timer0's channel 4 */
+ VICVectCntl0 = 0x20 | 4;
+ /* enable the timer0 interrupt */
+ VICIntEnable = 0x10;
+ /* reset the millisecond counter */
+ TimerSet(0);
+} /*** end of TimerInit ***/
+
+
+/****************************************************************************************
+** NAME: TimerUpdate
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Updates the millisecond timer. Should be called every millisecond by
+** the timer interrupt service routine.
+**
+****************************************************************************************/
+void TimerUpdate(void)
+{
+ /* increment the millisecond counter */
+ millisecond_counter++;
+} /*** end of TimerUpdate ***/
+
+
+/****************************************************************************************
+** NAME: TimerSet
+** PARAMETER: timer_value initialize value of the millisecond timer.
+** RETURN VALUE: none
+** DESCRIPTION: Sets the initial counter value of the millisecond timer.
+**
+****************************************************************************************/
+void TimerSet(unsigned long timer_value)
+{
+ /* set the millisecond counter */
+ millisecond_counter = timer_value;
+} /*** end of TimerSet ***/
+
+
+/****************************************************************************************
+** NAME: TimerGet
+** PARAMETER: none
+** RETURN VALUE: current value of the millisecond timer
+** DESCRIPTION: Obtains the counter value of the millisecond timer.
+**
+****************************************************************************************/
+unsigned long TimerGet(void)
+{
+ /* read and return the millisecond counter value */
+ return millisecond_counter;
+} /*** end of TimerGet ***/
+
+
+/*********************************** end of timer.c ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h
new file mode 100644
index 00000000..e1bb1754
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/timer.h
@@ -0,0 +1,44 @@
+/****************************************************************************************
+| Description: Timer driver header file
+| File Name: timer.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef TIMER_H
+#define TIMER_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void TimerInit(void);
+void TimerUpdate(void);
+void TimerSet(unsigned long timer_value);
+unsigned long TimerGet(void);
+
+
+#endif /* TIMER_H */
+/*********************************** end of timer.h ************************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c
new file mode 100644
index 00000000..5fe2ae98
--- /dev/null
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_Crossworks/Prog/vectors.c
@@ -0,0 +1,62 @@
+/****************************************************************************************
+| Description: demo program interrupt vectors source file
+| File Name: vectors.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "header.h" /* generic header */
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void __attribute__ ((interrupt("IRQ"))) TIMER0_ISR(void);
+
+
+/****************************************************************************************
+** NAME: TIMER0_ISR
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Timer0 exception routine.
+**
+****************************************************************************************/
+void TIMER0_ISR(void)
+{
+ /* clear the interrupt flag */
+ T0IR = 0x01;
+ /* acknowledge interrupt */
+ VICVectAddr = 0;
+ /* process time tick */
+ TimerUpdate();
+} /*** end of TIMER0_ISR ***/
+
+
+/*********************************** end of vectors.c **********************************/
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf
index 3981fbeb..d34a1d09 100644
Binary files a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf and b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.elf differ
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.hex b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.hex
index b2a52ca8..5adf7246 100644
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.hex
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.hex
@@ -1,7 +1,7 @@
:1000000018F09FE518F09FE518F09FE518F09FE5C0
:1000100018F09FE50000A0E118F09FE510F09FE5C3
-:100020005000000034150000A0000000341500004E
-:1000300034150000E41400000C150000000000005E
+:100020005000000040150000A00000004015000036
+:1000300040150000F014000018150000000000003A
:10004000E4009FE50110A0E3001080E5000000EF50
:10005000D8009FE5DBF021E300D0A0E1040040E2FE
:10006000D7F021E300D0A0E1040040E2D1F021E389
@@ -17,7 +17,7 @@
:10010000030052E10400913404008234FBFFFF3A03
:100110000000A0E324109FE524209FE5020051E1A8
:1001200004008134FCFFFF3A1EFF2FE140C01FE0B6
-:10013000DC1E00407C16000000020040000200406F
+:10013000DC1E004088160000000200400002004063
:1001400000020040F406004010402DE908D04DE2C6
:10015000FC309FE5003093E504308DE503308DE2FF
:100160000040A0E3EC109FE5EC209FE50100F3E5E3
@@ -35,8 +35,8 @@
:10022000013C83E20020C3E53C309FE5002093E5DC
:10023000052082E3002083E530309FE50FE0A0E158
:1002400013FF2FE128409FE50FE0A0E114FF2FE10D
-:10025000FCFFFFEA58150000C0D40100A080020096
-:10026000241600007C0A000000C01FE000C002E06D
+:10025000FCFFFFEA64150000C0D40100A08002008A
+:10026000301600007C0A000000C01FE000C002E061
:1002700078020000C402000008402DE930309FE5FC
:100280000FE0A0E113FF2FE128309FE50FE0A0E190
:1002900013FF2FE120309FE50FE0A0E113FF2FE1D6
@@ -153,7 +153,7 @@
:1009800020309FE50120A0E34320C3E5030083E27C
:10099000B414D3E128309FE50FE0A0E113FF2FE16D
:1009A0003840BDE81EFF2FE144020040A40A0000C9
-:1009B0005C1500009C0D0000F00D0000B80D00005B
+:1009B000681500009C0D0000F00D0000B80D00004F
:1009C000380B0000A403000008402DE95C309FE5CF
:1009D0000FE0A0E113FF2FE1010050E31100000A36
:1009E0004C309FE50030D3E5010053E30D00001AC1
@@ -201,7 +201,7 @@
:100C800017FF2FE10400D5E7BBFFFFEB010050E3A6
:100C90000800A0118E10A0130FE0A0111AFF2F1151
:100CA000014084E20438A0E1230856E1F2FFFF8A04
-:100CB000F845BDE81EFF2FE12C1600007C0A00005D
+:100CB000F845BDE81EFF2FE1381600007C0A000051
:100CC000780A000070402DE90050A0E1A0309FE5B7
:100CD0000030D3E5000053E30A00001A94009FE5BA
:100CE0009BFFFFEB010050E30000A0131E00001A61
@@ -220,11 +220,11 @@
:100DB0001EFF2FE13412000008402DE90C309FE5A2
:100DC0000FE0A0E113FF2FE10840BDE81EFF2FE177
:100DD000A012000008402DE90C309FE50FE0A0E1D3
-:100DE00013FF2FE10840BDE81EFF2FE14014000073
+:100DE00013FF2FE10840BDE81EFF2FE1D4130000E0
:100DF00008402DE920309FE50FE0A0E113FF2FE12F
:100E0000000050E30000A00310309F150FE0A01178
-:100E100013FF2F110840BDE81EFF2FE1D41300007F
-:100E20008814000014309FE50020A0E3042083E52F
+:100E100013FF2F110840BDE81EFF2FE11C14000036
+:100E20009414000014309FE50020A0E3042083E523
:100E30000C2083E5082083E5102083E51EFF2FE1C9
:100E4000004000E01C309FE5082093E518309FE546
:100E5000001093E5011082E0040093E5011060E0CA
@@ -243,7 +243,7 @@
:100F20000400002A852085E028309FE5023183E017
:100F30000800D3E5040000EA015085E20C4084E299
:100F4000C00054E3ECFFFF1AFF00A0E3F041BDE84E
-:100F50001EFF2FE1780A00006415000030402DE9E3
+:100F50001EFF2FE1780A00007015000030402DE9D7
:100F600024D04DE20040A0E1000090E5DCFFFFEB63
:100F7000FF0050E30000A0033D00000A3230A0E370
:100F80000C308DE510008DE514008DE50130A0E3F7
@@ -315,47 +315,48 @@
:1013A0000D00A0E114108DE23A31E0E30FE0A0E17E
:1013B00013FF2FE114009DE5010070E20000A0334F
:1013C00020D08DE27040BDE81EFF2FE1780A0000BA
-:1013D00060EA000004E02DE50CD04DE254209FE5CA
-:1013E000823F82E2030093E9011080E0082292E547
-:1013F000021081E00C2093E5021081E0102093E5BB
-:10140000021081E0182093E5021081E01C2093E592
-:10141000023081E0003063E208208DE2043022E5F2
-:1014200014009FE50410A0E381FFFFEB0CD08DE2D8
-:1014300004E09DE41EFF2FE1EC02004014200000B8
-:10144000023AA0E3050093E8000082E0082093E55B
-:10145000020080E00C2093E5020080E0102093E57C
-:10146000020080E0142093E5020080E0182093E55C
-:10147000020080E01C3093E5030080E0010070E290
-:101480000000A0331EFF2FE108402DE948309FE502
-:10149000043293E5010073E30400000A3C009FE579
-:1014A000ADFEFFEB000050E30000A0030800000ABF
-:1014B00024309FE5003093E5010073E30100A003B1
-:1014C0000300000A10009FE5A3FEFFEB000050E2BE
-:1014D0000100A0130840BDE81EFF2FE1EC02004010
-:1014E000F004004004E04EE21F402DE910009FE5AB
-:1014F0003810A0E30C309FE50FE0A0E113FF2FE1CF
-:101500001F80FDE8501600007C0A000004E04EE257
-:101510000F502DE910009FE54610A0E30C309FE529
-:101520000FE0A0E113FF2FE10F90FDE8501600003F
-:101530007C0A00000F502DE910009FE55410A0E335
-:101540000C309FE50FE0A0E113FF2FE10F90FDE8C5
-:10155000501600007C0A0000010204084F70656EFE
-:10156000424C540000200000002000000100000058
-:1015700000400000002000000200000000600000A9
-:101580000020000003000000008000000020000098
-:101590000400000000A00000002000000500000082
-:1015A00000C00000002000000600000000E0000075
-:1015B0000020000007000000000001000000010002
-:1015C0000800000000000200000001000900000007
-:1015D00000000300002000000A00000000200300BB
-:1015E000002000000B00000000400300002000006D
-:1015F0000C00000000600300002000000D0000004F
-:1016000000800300002000000E00000000A0030086
-:10161000002000000F00000000C0030000200000B8
-:10162000100000006D61696E2E6300002E2E2F2EBB
-:101630002E2F2E2E2F536F757263652F41524D370B
-:101640005F4C5043323030302F756172742E63001E
-:101650002E2E2F2E2E2F2E2E2F536F757263652F49
-:1016600041524D375F4C5043323030302F47434367
-:0C1670002F766563746F72732E630000A8
+:1013D00060EA0000023AA0E3050093E8000082E022
+:1013E000082093E5020080E00C2093E5020080E0F5
+:1013F000102093E5020080E0142093E5020080E0D5
+:10140000182093E5020080E01C3093E5030080E0A3
+:10141000010070E20000A0331EFF2FE110402DE913
+:1014200008D04DE260209FE5823F82E2120093E9FE
+:10143000044081E0082292E5024084E00C2093E51C
+:10144000024084E0102093E5024084E0182093E5F8
+:10145000024084E01C3093E5034084E0004064E2F5
+:1014600004408DE5DAFFFFEB000054E10100A0032A
+:1014700018009F150410A01301208D106CFFFF1B96
+:1014800008D08DE21040BDE81EFF2FE1EC020040C5
+:101490001420000008402DE948309FE5043293E510
+:1014A000010073E30400000A3C009FE5AAFEFFEB85
+:1014B000000050E30000A0030800000A24309FE56C
+:1014C000003093E5010073E30100A0030300000A6C
+:1014D00010009FE5A0FEFFEB000050E20100A0130A
+:1014E0000840BDE81EFF2FE1EC020040F004004080
+:1014F00004E04EE21F402DE910009FE53810A0E304
+:101500000C309FE50FE0A0E113FF2FE11F80FDE805
+:101510005C1600007C0A000004E04EE20F502DE94A
+:1015200010009FE54610A0E30C309FE50FE0A0E11E
+:1015300013FF2FE10F90FDE85C1600007C0A00000D
+:101540000F502DE910009FE55410A0E30C309FE5EB
+:101550000FE0A0E113FF2FE10F90FDE85C16000003
+:101560007C0A0000010204084F70656E424C540072
+:1015700000200000002000000100000000400000EA
+:1015800000200000020000000060000000200000B9
+:1015900003000000008000000020000004000000A4
+:1015A00000A00000002000000500000000C00000B6
+:1015B000002000000600000000E000000020000005
+:1015C000070000000000010000000100080000000A
+:1015D00000000200000001000900000000000300FC
+:1015E000002000000A00000000200300002000008E
+:1015F0000B00000000400300002000000C00000071
+:1016000000600300002000000D00000000800300C7
+:10161000002000000E00000000A0030000200000D9
+:101620000F00000000C003000020000010000000B8
+:101630006D61696E2E6300002E2E2F2E2E2F2E2E02
+:101640002F536F757263652F41524D375F4C504376
+:10165000323030302F756172742E63002E2E2F2E93
+:101660002E2F2E2E2F536F757263652F41524D37DB
+:101670005F4C5043323030302F4743432F76656301
+:08168000746F72732E63000009
:00000001FF
diff --git a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map
index 49cf82a0..d2e23625 100644
--- a/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map
+++ b/Target/Demo/ARM7_LPC2000_Olimex_LPC_L2294_GCC/Boot/bin/openbtl_olimex_lpc_l2294_20mhz.map
@@ -7,38 +7,38 @@ start address 0x00000000
Program Header:
LOAD off 0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15
- filesz 0x0000167c memsz 0x0000167c flags r-x
- LOAD off 0x00010200 vaddr 0x40000200 paddr 0x0000167c align 2**15
+ filesz 0x00001688 memsz 0x00001688 flags r-x
+ LOAD off 0x00010200 vaddr 0x40000200 paddr 0x00001688 align 2**15
filesz 0x00000000 memsz 0x000004f4 flags rw-
private flags = 5000000: [Version5 EABI]
Sections:
Idx Name Size VMA LMA File off Algn
- 0 .text 0000167c 00000000 00000000 00008000 2**2
+ 0 .text 00001688 00000000 00000000 00008000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 1 .bss 000004f4 40000200 0000167c 00010200 2**2
+ 1 .bss 000004f4 40000200 00001688 00010200 2**2
ALLOC
- 2 .ARM.attributes 00000030 00000000 00000000 0000967c 2**0
+ 2 .ARM.attributes 00000030 00000000 00000000 00009688 2**0
CONTENTS, READONLY
- 3 .comment 0000002a 00000000 00000000 000096ac 2**0
+ 3 .comment 0000002a 00000000 00000000 000096b8 2**0
CONTENTS, READONLY
- 4 .debug_abbrev 00000a61 00000000 00000000 000096d6 2**0
+ 4 .debug_abbrev 00000a61 00000000 00000000 000096e2 2**0
CONTENTS, READONLY, DEBUGGING
- 5 .debug_info 0000173b 00000000 00000000 0000a137 2**0
+ 5 .debug_info 0000173c 00000000 00000000 0000a143 2**0
CONTENTS, READONLY, DEBUGGING
- 6 .debug_line 00000873 00000000 00000000 0000b872 2**0
+ 6 .debug_line 00000878 00000000 00000000 0000b87f 2**0
CONTENTS, READONLY, DEBUGGING
- 7 .debug_pubtypes 00000312 00000000 00000000 0000c0e5 2**0
+ 7 .debug_pubtypes 00000312 00000000 00000000 0000c0f7 2**0
CONTENTS, READONLY, DEBUGGING
- 8 .debug_str 000008fa 00000000 00000000 0000c3f7 2**0
+ 8 .debug_str 000008fa 00000000 00000000 0000c409 2**0
CONTENTS, READONLY, DEBUGGING
- 9 .debug_loc 00000be6 00000000 00000000 0000ccf1 2**0
+ 9 .debug_loc 00000bf9 00000000 00000000 0000cd03 2**0
CONTENTS, READONLY, DEBUGGING
- 10 .debug_pubnames 000003af 00000000 00000000 0000d8d7 2**0
+ 10 .debug_pubnames 000003af 00000000 00000000 0000d8fc 2**0
CONTENTS, READONLY, DEBUGGING
- 11 .debug_aranges 000001a0 00000000 00000000 0000dc86 2**0
+ 11 .debug_aranges 000001a0 00000000 00000000 0000dcab 2**0
CONTENTS, READONLY, DEBUGGING
- 12 .debug_frame 0000063c 00000000 00000000 0000de28 2**2
+ 12 .debug_frame 0000063c 00000000 00000000 0000de4c 2**2
CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
00000000 l d .text 00000000 .text
@@ -80,7 +80,7 @@ e01fc040 l *ABS* 00000000 MEMMAP
000000a0 l .text 00000000 Reset_Handler_SWI
00000000 l df *ABS* 00000000 hooks.c
00000000 l df *ABS* 00000000 main.c
-00001558 l O .text 00000004 C.0.2157
+00001564 l O .text 00000004 C.0.2157
00000000 l df *ABS* 00000000 boot.c
00000000 l df *ABS* 00000000 com.c
40000200 l O .bss 00000001 comEntryStateConnect
@@ -88,7 +88,7 @@ e01fc040 l *ABS* 00000000 MEMMAP
00000000 l df *ABS* 00000000 xcp.c
00000414 l F .text 00000014 XcpProtectResources
00000428 l F .text 00000020 XcpSetCtoError
-0000155c l O .text 00000008 xcpStationId
+00001568 l O .text 00000008 xcpStationId
40000244 l O .bss 0000004c xcpInfo
00000000 l df *ABS* 00000000 backdoor.c
40000290 l O .bss 00000001 backdoorOpen
@@ -114,14 +114,14 @@ e01fc040 l *ABS* 00000000 MEMMAP
00001088 l F .text 00000044 FlashInitBlock
000010cc l F .text 00000068 FlashSwitchBlock
00001134 l F .text 000000e8 FlashAddToBlock
-00001564 l O .text 000000c0 flashLayout
+00001570 l O .text 000000c0 flashLayout
400002ec l O .bss 00000204 blockInfo
400004f0 l O .bss 00000204 bootBlockInfo
00000000 l df *ABS* 00000000 vectors.c
00000300 g F .text 00000068 ComInit
00001234 g F .text 0000006c FlashWrite
00000a7c g F .text 00000028 AssertFailure
-0000150c g F .text 00000028 IRQ_ISR
+00001518 g F .text 00000028 IRQ_ISR
00000e44 g F .text 0000002c TimerUpdate
00000488 g F .text 00000014 XcpPacketTransmitted
00000368 g F .text 0000003c ComTask
@@ -129,10 +129,10 @@ e01fc040 l *ABS* 00000000 MEMMAP
00000278 g F .text 0000004c BootInit
00000a44 g F .text 00000030 BackDoorInit
00000a78 g F .text 00000004 CopService
-0000167c g .text 00000000 _etext
+00001688 g .text 00000000 _etext
00000e24 g F .text 00000020 TimerReset
000002c4 g F .text 0000003c BootTask
-000013d4 g F .text 0000006c FlashWriteChecksum
+0000141c g F .text 00000078 FlashWriteChecksum
40000200 g .bss 00000000 _bss_start
000003a4 g F .text 00000030 ComTransmitPacket
00000000 g .text 00000000 _startup
@@ -144,7 +144,7 @@ e01fc040 l *ABS* 00000000 MEMMAP
00000bdc g F .text 00000040 UartInit
00000db8 g F .text 0000001c NvmErase
0000049c g F .text 0000052c XcpPacketReceived
-00001488 g F .text 0000005c FlashDone
+00001494 g F .text 0000005c FlashDone
00000040 g .text 00000000 EntryFromProg
000003e8 g F .text 00000010 ComIsConnectEntryState
00000448 g F .text 00000028 XcpInit
@@ -156,7 +156,7 @@ e01fc040 l *ABS* 00000000 MEMMAP
00000aa4 g F .text 00000044 CpuMemCopy
40001edc g *ABS* 00000000 _stack_end
00000e70 g F .text 00000010 TimerSet
-000014e4 g F .text 00000028 FIQ_ISR
+000014f0 g F .text 00000028 FIQ_ISR
00000cc4 g F .text 000000bc UartReceivePacket
40000200 g .text 00000000 _data
00000a74 g F .text 00000004 CopInit
@@ -164,10 +164,10 @@ e01fc040 l *ABS* 00000000 MEMMAP
000000f4 g .text 00000000 SetupRAM
00000d9c g F .text 0000001c NvmWrite
00000ae8 g F .text 00000050 CpuStartUserProgram
-00001440 g F .text 00000048 FlashVerifyChecksum
+000013d4 g F .text 00000048 FlashVerifyChecksum
40000200 g .text 00000000 _edata
400006f4 g *ABS* 00000000 _end
-00001534 g F .text 00000024 UNDEF_ISR
+00001540 g F .text 00000024 UNDEF_ISR
000003f8 g F .text 0000001c ComIsConnected
000009c8 g F .text 0000007c BackDoorCheck
00000ec8 g F .text 0000001c TimerGet
diff --git a/Target/Source/ARM7_LPC2000/Crossworks/cstart.s b/Target/Source/ARM7_LPC2000/Crossworks/cstart.s
new file mode 100644
index 00000000..2b4dd7b6
--- /dev/null
+++ b/Target/Source/ARM7_LPC2000/Crossworks/cstart.s
@@ -0,0 +1,669 @@
+/*****************************************************************************
+ * Copyright (c) 2001, 2002 Rowley Associates Limited. *
+ * *
+ * This file may be distributed under the terms of the License Agreement *
+ * provided with this software. *
+ * *
+ * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE *
+ * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
+ *****************************************************************************/
+
+/*****************************************************************************
+ * Preprocessor Definitions
+ * ------------------------
+ * APP_ENTRY_POINT
+ *
+ * Defines the application entry point function, if undefined this setting
+ * defaults to "main".
+ *
+ * INITIALIZE_STACKS
+ *
+ * If defined, the contents of the stacks will be initialized to a the
+ * value 0xCC.
+ *
+ * INITIALIZE_SECONDARY_SECTIONS
+ *
+ * If defined, the .text2, .data2 and .bss2 sections will be initialized.
+ *
+ * SUPERVISOR_START
+ *
+ * If defined, the application will start up in supervisor mode. If
+ * undefined the application will start up in system mode.
+ *
+ * FULL_LIBRARY
+ *
+ * If defined then
+ * - argc, argv are setup by the debug_getargs.
+ * - the exit symbol is defined and executes on return from main.
+ * - the exit symbol calls destructors, atexit functions and then debug_exit.
+ *
+ * If not defined then
+ * - argc and argv are zero.
+ * - the exit symbol is defined, executes on return from main and loops
+ *
+ *****************************************************************************/
+
+ .section .vectors, "ax"
+ .code 32
+ .align 0
+ .global _vectors
+ .global reset_handler
+
+/*****************************************************************************
+ * Exception Vectors *
+ *****************************************************************************/
+_vectors:
+ ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
+ ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
+ ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
+ ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
+ ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
+ .word 0xB9205F88 /* boot loader checksum */
+ ldr pc, [pc, #-0xFF0] /* irq handler */
+ ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq handler */
+
+reset_handler_address:
+ .word Reset_Handler
+undef_handler_address:
+ .word undef_handler
+swi_handler_address:
+ .word Reset_Handler_SWI
+pabort_handler_address:
+ .word pabort_handler
+dabort_handler_address:
+ .word dabort_handler
+fiq_handler_address:
+ .word fiq_handler
+
+
+ .section .init, "ax"
+ .code 32
+ .align 4
+/* microcontroller registers */
+.set MEMMAP, 0xE01FC040 /* MEMMAP register */
+
+.global EntryFromProg
+/****************************************************************************************
+** NAME: EntryFromProg
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Called by the user program to activate the bootloader. Do not place
+** any assembly code between this function and the end of the vector
+** table. This guarantees that this function is located at address
+** 0x00000040. The user program can call this function from C in the
+** following way:
+** void ActivateBootloader(void)
+** {
+** void (*pEntryFromProgFnc)(void);
+**
+** pEntryFromProgFnc = (void*)0x00000040;
+** pEntryFromProgFnc();
+** }
+**
+****************************************************************************************/
+EntryFromProg:
+ /* remap interrupt vector table back to ROM to make sure the bootloader
+ * vectors are used:
+ * MEMMAP = 0x01;
+ */
+ ldr r0, =MEMMAP
+ mov r1, #1
+ str r1, [r0, #0]
+ /* trigger SWI to entry supervisor mode and run Reset_Handler_SWI */
+ swi 0
+ /*** end of EntryFromProg ***/
+
+
+ .section .init, "ax"
+ .code 32
+ .align 4
+
+#ifndef APP_ENTRY_POINT
+#define APP_ENTRY_POINT main
+#endif
+
+#ifndef ARGSSPACE
+#define ARGSSPACE 128
+#endif
+
+ .weak Reset_Handler
+ .global __start
+ .global __gccmain
+ .extern APP_ENTRY_POINT
+ .global exit
+
+/****************************************************************************************
+** NAME: Reset_Handler
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Reset interrupt service routine. Configures the stack for each mode,
+** disables the IRQ and FIQ interrupts, initializes RAM and jumps to
+** function main.
+**
+****************************************************************************************/
+Reset_Handler:
+__start:
+ mrs r0, cpsr
+ bic r0, r0, #0x1F
+
+ /* Setup stacks */
+ orr r1, r0, #0x1B /* Undefined mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_und_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x17 /* Abort mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_abt_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x12 /* IRQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_irq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x11 /* FIQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_fiq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x13 /* Supervisor mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_svc_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+#ifdef SUPERVISOR_START
+ /* Start application in supervisor mode */
+ ldr r1, =__stack_end__ /* Setup user/system mode stack */
+#ifdef __ARM_EABI__
+ bic r1, r1, #0x7
+#endif
+ mov r2, sp
+ stmfd r2!, {r1}
+ ldmfd r2, {sp}^
+#else
+ /* Start application in system mode */
+ orr r1, r0, #0x1F /* System mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+#endif
+
+#ifdef INITIALIZE_STACKS
+ mov r2, #0xCC
+ ldr r0, =__stack_und_start__
+ ldr r1, =__stack_und_end__
+ bl memory_set
+ ldr r0, =__stack_abt_start__
+ ldr r1, =__stack_abt_end__
+ bl memory_set
+ ldr r0, =__stack_irq_start__
+ ldr r1, =__stack_irq_end__
+ bl memory_set
+ ldr r0, =__stack_fiq_start__
+ ldr r1, =__stack_fiq_end__
+ bl memory_set
+ ldr r0, =__stack_svc_start__
+ ldr r1, =__stack_svc_end__
+ bl memory_set
+ ldr r0, =__stack_start__
+ ldr r1, =__stack_end__
+ bl memory_set
+#endif
+
+ /* Copy initialised memory sections into RAM (if necessary). */
+ ldr r0, =__data_load_start__
+ ldr r1, =__data_start__
+ ldr r2, =__data_end__
+ bl memory_copy
+ ldr r0, =__text_load_start__
+ ldr r1, =__text_start__
+ ldr r2, =__text_end__
+ bl memory_copy
+ ldr r0, =__fast_load_start__
+ ldr r1, =__fast_start__
+ ldr r2, =__fast_end__
+ bl memory_copy
+ ldr r0, =__ctors_load_start__
+ ldr r1, =__ctors_start__
+ ldr r2, =__ctors_end__
+ bl memory_copy
+ ldr r0, =__dtors_load_start__
+ ldr r1, =__dtors_start__
+ ldr r2, =__dtors_end__
+ bl memory_copy
+ ldr r0, =__rodata_load_start__
+ ldr r1, =__rodata_start__
+ ldr r2, =__rodata_end__
+ bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__data2_load_start__
+ ldr r1, =__data2_start__
+ ldr r2, =__data2_end__
+ bl memory_copy
+ ldr r0, =__text2_load_start__
+ ldr r1, =__text2_start__
+ ldr r2, =__text2_end__
+ bl memory_copy
+ ldr r0, =__rodata2_load_start__
+ ldr r1, =__rodata2_start__
+ ldr r2, =__rodata2_end__
+ bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Zero the bss. */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+ bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__bss2_start__
+ ldr r1, =__bss2_end__
+ mov r2, #0
+ bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Initialise the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ sub r1, r1, r0
+ cmp r1, #8
+ movge r2, #0
+ strge r2, [r0], #+4
+ strge r1, [r0]
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop:
+ cmp r0, r1
+ beq ctor_end
+ ldr r2, [r0], #+4
+ stmfd sp!, {r0-r1}
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldmfd sp!, {r0-r1}
+ b ctor_loop
+ctor_end:
+
+ .type start, function
+start:
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ mov r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldr r1, =args
+#else
+ mov r0, #0
+ mov r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+exit:
+#ifdef FULL_LIBRARY
+ mov r5, r0 // save the exit parameter/return result
+
+ /* Call destructors */
+ ldr r0, =__dtors_start__
+ ldr r1, =__dtors_end__
+dtor_loop:
+ cmp r0, r1
+ beq dtor_end
+ ldr r2, [r0], #+4
+ stmfd sp!, {r0-r1}
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldmfd sp!, {r0-r1}
+ b dtor_loop
+dtor_end:
+
+ /* Call atexit functions */
+ ldr r2, =_execute_at_exit_fns
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+ /* Call debug_exit with return result/exit parameter */
+ mov r0, r5
+ ldr r2, =debug_exit
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+#endif
+
+ /* Returned from application entry point/debug_exit, loop forever. */
+exit_loop:
+ b exit_loop
+
+
+.extern ComSetConnectEntryState
+/****************************************************************************************
+** NAME: Reset_Handler_SWI
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Reset handler for a software reset after the user program activated
+** the bootloader. Configures the stack for each mode, disables the IRQ
+** and FIQ interrupts, initializes RAM. Most importantly, before jumping
+** to function main to start the bootloader program, the COM interface
+** is configured to start in a connected state. Here is why:
+** At the start of a new programming session, the host sends the XCP
+** CONNECT command. Upon reception, the user program activates the
+** bootloader by jumping to function EntryFromProg(), which triggers the
+** SWI instruction that gets the program to this point. When the
+** bootloader is started, it now needs to send the response to the XCP
+** CONNECT command, because the host is waiting for this before it can
+** continue.
+**
+****************************************************************************************/
+Reset_Handler_SWI:
+__start2:
+ mrs r0, cpsr
+ bic r0, r0, #0x1F
+
+ /* Setup stacks */
+ orr r1, r0, #0x1B /* Undefined mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_und_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x17 /* Abort mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_abt_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x12 /* IRQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_irq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x11 /* FIQ mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_fiq_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+ orr r1, r0, #0x13 /* Supervisor mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_svc_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+
+#ifdef SUPERVISOR_START
+ /* Start application in supervisor mode */
+ ldr r1, =__stack_end__ /* Setup user/system mode stack */
+#ifdef __ARM_EABI__
+ bic r1, r1, #0x7
+#endif
+ mov r2, sp
+ stmfd r2!, {r1}
+ ldmfd r2, {sp}^
+#else
+ /* Start application in system mode */
+ orr r1, r0, #0x1F /* System mode */
+ msr cpsr_cxsf, r1
+ ldr sp, =__stack_end__
+#ifdef __ARM_EABI__
+ bic sp, sp, #0x7
+#endif
+#endif
+
+#ifdef INITIALIZE_STACKS
+ mov r2, #0xCC
+ ldr r0, =__stack_und_start__
+ ldr r1, =__stack_und_end__
+ bl memory_set
+ ldr r0, =__stack_abt_start__
+ ldr r1, =__stack_abt_end__
+ bl memory_set
+ ldr r0, =__stack_irq_start__
+ ldr r1, =__stack_irq_end__
+ bl memory_set
+ ldr r0, =__stack_fiq_start__
+ ldr r1, =__stack_fiq_end__
+ bl memory_set
+ ldr r0, =__stack_svc_start__
+ ldr r1, =__stack_svc_end__
+ bl memory_set
+ ldr r0, =__stack_start__
+ ldr r1, =__stack_end__
+ bl memory_set
+#endif
+
+ /* Copy initialised memory sections into RAM (if necessary). */
+ ldr r0, =__data_load_start__
+ ldr r1, =__data_start__
+ ldr r2, =__data_end__
+ bl memory_copy
+ ldr r0, =__text_load_start__
+ ldr r1, =__text_start__
+ ldr r2, =__text_end__
+ bl memory_copy
+ ldr r0, =__fast_load_start__
+ ldr r1, =__fast_start__
+ ldr r2, =__fast_end__
+ bl memory_copy
+ ldr r0, =__ctors_load_start__
+ ldr r1, =__ctors_start__
+ ldr r2, =__ctors_end__
+ bl memory_copy
+ ldr r0, =__dtors_load_start__
+ ldr r1, =__dtors_start__
+ ldr r2, =__dtors_end__
+ bl memory_copy
+ ldr r0, =__rodata_load_start__
+ ldr r1, =__rodata_start__
+ ldr r2, =__rodata_end__
+ bl memory_copy
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__data2_load_start__
+ ldr r1, =__data2_start__
+ ldr r2, =__data2_end__
+ bl memory_copy
+ ldr r0, =__text2_load_start__
+ ldr r1, =__text2_start__
+ ldr r2, =__text2_end__
+ bl memory_copy
+ ldr r0, =__rodata2_load_start__
+ ldr r1, =__rodata2_start__
+ ldr r2, =__rodata2_end__
+ bl memory_copy
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Zero the bss. */
+ ldr r0, =__bss_start__
+ ldr r1, =__bss_end__
+ mov r2, #0
+ bl memory_set
+#ifdef INITIALIZE_SECONDARY_SECTIONS
+ ldr r0, =__bss2_start__
+ ldr r1, =__bss2_end__
+ mov r2, #0
+ bl memory_set
+#endif /* #ifdef INITIALIZE_SECONDARY_SECTIONS */
+
+ /* Initialise the heap */
+ ldr r0, = __heap_start__
+ ldr r1, = __heap_end__
+ sub r1, r1, r0
+ cmp r1, #8
+ movge r2, #0
+ strge r2, [r0], #+4
+ strge r1, [r0]
+
+ /* Call constructors */
+ ldr r0, =__ctors_start__
+ ldr r1, =__ctors_end__
+ctor_loop2:
+ cmp r0, r1
+ beq ctor_end
+ ldr r2, [r0], #+4
+ stmfd sp!, {r0-r1}
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldmfd sp!, {r0-r1}
+ b ctor_loop
+ctor_end2:
+
+ .type start, function
+start2:
+ /* this part makes the difference with the normal Reset_Handler */
+ bl ComSetConnectEntryState
+ /* Jump to application entry point */
+#ifdef FULL_LIBRARY
+ mov r0, #ARGSSPACE
+ ldr r1, =args
+ ldr r2, =debug_getargs
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+ ldr r1, =args
+#else
+ mov r0, #0
+ mov r1, #0
+#endif
+ ldr r2, =APP_ENTRY_POINT
+ mov lr, pc
+#ifdef __ARM_ARCH_3__
+ mov pc, r2
+#else
+ bx r2
+#endif
+
+
+
+memory_copy:
+ cmp r0, r1
+ moveq pc, lr
+ subs r2, r2, r1
+ moveq pc, lr
+
+ /* if either pointer or length is not word aligned then byte copy */
+ orr r3, r0, r1
+ orr r3, r3, r2
+ tst r3, #0x3
+ bne 2f
+ /* word copy */
+1:
+ ldr r3, [r0], #+4
+ str r3, [r1], #+4
+ subs r2, r2, #4
+ bne 1b
+ mov pc, lr
+ /* byte copy */
+2:
+ ldrb r3, [r0], #+1
+ strb r3, [r1], #+1
+ subs r2, r2, #1
+ bne 2b
+ mov pc, lr
+
+memory_set:
+ cmp r0, r1
+ moveq pc, lr
+ strb r2, [r0], #1
+ b memory_set
+
+
+ .section .init, "ax"
+ .code 32
+ .align 0
+
+/******************************************************************************
+ * *
+ * Default exception handlers *
+ * *
+ ******************************************************************************/
+/******************************************************************************
+ * *
+ * Default exception handlers *
+ * These are declared weak symbols so they can be redefined in user code. *
+ * *
+ ******************************************************************************/
+undef_handler:
+ b undef_handler
+
+pabort_handler:
+ b pabort_handler
+
+dabort_handler:
+ b dabort_handler
+
+fiq_handler:
+ b fiq_handler
+
+irq_handler:
+ b irq_handler
+
+ .weak undef_handler, pabort_handler, dabort_handler, fiq_handler, irq_handler
+
+
+#ifdef FULL_LIBRARY
+ .bss
+args:
+ .space ARGSSPACE
+#endif
+
+ /* Setup attibutes of stack and heap sections so they don't take up unnecessary room in the elf file */
+ .section .stack, "wa", %nobits
+ .section .stack_abt, "wa", %nobits
+ .section .stack_irq, "wa", %nobits
+ .section .stack_fiq, "wa", %nobits
+ .section .stack_svc, "wa", %nobits
+ .section .stack_und, "wa", %nobits
+ .section .heap, "wa", %nobits
+
diff --git a/Target/Source/ARM7_LPC2000/Crossworks/flash.c b/Target/Source/ARM7_LPC2000/Crossworks/flash.c
new file mode 100644
index 00000000..f8fe1ab7
--- /dev/null
+++ b/Target/Source/ARM7_LPC2000/Crossworks/flash.c
@@ -0,0 +1,713 @@
+/****************************************************************************************
+| Description: bootloader flash driver source file
+| File Name: flash.c
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+
+/****************************************************************************************
+* Include files
+****************************************************************************************/
+#include "boot.h" /* bootloader generic header */
+
+
+/****************************************************************************************
+* Macro definitions
+****************************************************************************************/
+#define FLASH_INVALID_SECTOR (0xff)
+#define FLASH_INVALID_ADDRESS (0xffffffff)
+#define FLASH_WRITE_BLOCK_SIZE (512)
+#define FLASH_TOTAL_SECTORS (sizeof(flashLayout)/sizeof(flashLayout[0]))
+/* entry address for the IAP algorithms, enabling a switch to thumb mode */
+#define IAP_ENTRY_ADDRESS (0x7ffffff1)
+/* command codes */
+#define IAP_CMD_PREPARE_SECTORS (50)
+#define IAP_CMD_COPY_RAM_TO_FLASH (51)
+#define IAP_CMD_ERASE_SECTORS (52)
+#define IAP_CMD_BLANK_CHECK_SECTORS (53)
+#define IAP_CMD_COMPARE (56)
+/* result codes */
+#define IAP_CMD_SUCCESS (0)
+
+
+/****************************************************************************************
+* Type definitions
+****************************************************************************************/
+/* function pointer type that is needed to call IAP functions of the NXP LPC2xxx */
+typedef void (*pIapHandler)(blt_int32u command[], blt_int32u result[]);
+
+/* flash sector descriptor type */
+typedef struct
+{
+ blt_addr sector_start; /* sector start address */
+ blt_int32u sector_size; /* sector size in bytes */
+ blt_int8u sector_num; /* sector number */
+} tFlashSector; /* flash sector description */
+
+/* programming is done per block of max FLASH_WRITE_BLOCK_SIZE. for this a flash block
+ * manager is implemented in this driver. this flash block manager depends on this
+ * flash block info structure. It holds the base address of the flash block and the
+ * data that should be programmed into the flash block. Note that the .data member must
+ * be 32-bit aligned by the linker. the .base_addr must be a multiple of
+ * FLASH_WRITE_BLOCK_SIZE.
+ */
+typedef struct
+{
+ blt_addr base_addr;
+ blt_int8u data[FLASH_WRITE_BLOCK_SIZE] __attribute__ ((aligned (4)));
+} tFlashBlockInfo;
+
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address);
+static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr);
+static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
+ blt_int8u *data, blt_int16u len);
+static blt_bool FlashWriteBlock(tFlashBlockInfo *block);
+static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector);
+static blt_int8u FlashGetSector(blt_addr address);
+
+
+/****************************************************************************************
+* Local constant declarations
+****************************************************************************************/
+/* The current flash layout supports the NXP LPC21xx and LPC22xx targets. LPC23xx have
+ * a slightly different layout. To support the LPC23xx, simply update this flash layout.
+ */
+static const tFlashSector flashLayout[] =
+{
+#if (BOOT_NVM_SIZE_KB == 64)
+ /* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
+ { 0x00002000, 0x02000, 1}, /* flash sector 1 */
+ { 0x00004000, 0x02000, 2}, /* flash sector 2 */
+ { 0x00006000, 0x02000, 3}, /* flash sector 3 */
+ { 0x00008000, 0x02000, 4}, /* flash sector 4 */
+ { 0x0000A000, 0x02000, 5}, /* flash sector 5 */
+ { 0x0000C000, 0x02000, 6}, /* flash sector 6 */
+ /* { 0x0000E000, 0x02000, 7}, flash sector 7 - used by NXP bootcode */
+#endif
+#if (BOOT_NVM_SIZE_KB == 128)
+ /* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
+ { 0x00002000, 0x02000, 1}, /* flash sector 1 */
+ { 0x00004000, 0x02000, 2}, /* flash sector 2 */
+ { 0x00006000, 0x02000, 3}, /* flash sector 3 */
+ { 0x00008000, 0x02000, 4}, /* flash sector 4 */
+ { 0x0000A000, 0x02000, 5}, /* flash sector 5 */
+ { 0x0000C000, 0x02000, 6}, /* flash sector 6 */
+ { 0x0000E000, 0x02000, 7}, /* flash sector 7 */
+ { 0x00010000, 0x02000, 8}, /* flash sector 8 */
+ { 0x00012000, 0x02000, 9}, /* flash sector 9 */
+ { 0x00014000, 0x02000, 10}, /* flash sector 10 */
+ { 0x00016000, 0x02000, 11}, /* flash sector 11 */
+ { 0x00018000, 0x02000, 12}, /* flash sector 12 */
+ { 0x0001A000, 0x02000, 13}, /* flash sector 13 */
+ { 0x0001C000, 0x02000, 14}, /* flash sector 14 */
+ /* { 0x0001E000, 0x02000, 15}, flash sector 15 - used by NXP bootcode */
+#endif
+#if (BOOT_NVM_SIZE_KB == 256)
+ /* { 0x00000000, 0x02000, 0}, flash sector 0 - reserved for bootloader */
+ { 0x00002000, 0x02000, 1}, /* flash sector 1 */
+ { 0x00004000, 0x02000, 2}, /* flash sector 2 */
+ { 0x00006000, 0x02000, 3}, /* flash sector 3 */
+ { 0x00008000, 0x02000, 4}, /* flash sector 4 */
+ { 0x0000A000, 0x02000, 5}, /* flash sector 5 */
+ { 0x0000C000, 0x02000, 6}, /* flash sector 6 */
+ { 0x0000E000, 0x02000, 7}, /* flash sector 7 */
+ { 0x00010000, 0x10000, 8}, /* flash sector 8 */
+ { 0x00020000, 0x10000, 9}, /* flash sector 9 */
+ { 0x00030000, 0x02000, 10}, /* flash sector 10 */
+ { 0x00032000, 0x02000, 11}, /* flash sector 11 */
+ { 0x00034000, 0x02000, 12}, /* flash sector 12 */
+ { 0x00036000, 0x02000, 13}, /* flash sector 13 */
+ { 0x00038000, 0x02000, 14}, /* flash sector 14 */
+ { 0x0003A000, 0x02000, 15}, /* flash sector 15 */
+ { 0x0003C000, 0x02000, 16}, /* flash sector 16 */
+ /* { 0x0003E000, 0x02000, 17}, flash sector 17 - used by NXP bootcode */
+#endif
+};
+
+
+/****************************************************************************************
+* Local data declarations
+****************************************************************************************/
+/* The smallest amount of flash that can be programmed is FLASH_WRITE_BLOCK_SIZE. A flash
+ * block manager is implemented in this driver and stores info in this variable. Whenever
+ * new data should be flashed, it is first added to a RAM buffer, which is part of this
+ * variable. Whenever the RAM buffer, which has the size of a flash block, is full or
+ * data needs to be written to a different block, the contents of the RAM buffer are
+ * programmed to flash. The flash block manager requires some software overhead, yet
+ * results is faster flash programming because data is first harvested, ideally until
+ * there is enough to program an entire flash block, before the flash device is actually
+ * operated on.
+ */
+static tFlashBlockInfo blockInfo;
+
+/* The first block of the user program holds the vector table, which on the LPC2000 is
+ * also the where the checksum is written to. Is it likely that the vector table is
+ * first flashed and then, at the end of the programming sequence, the checksum. This
+ * means that this flash block need to be written to twice. Normally this is not a
+ * problem with flash memory, as long as you write the same values to those bytes that
+ * are not supposed to be changed and the locations where you do write to are still in
+ * the erased 0xFF state. Unfortunately, writing twice to flash this way, does not work
+ * reliably on the LPC2000. This is why we need to have an extra block, the bootblock,
+ * placed under the management of the block manager. This way is it possible to implement
+ * functionality so that the bootblock is only written to once at the end of the
+ * programming sequency.
+ */
+static tFlashBlockInfo bootBlockInfo;
+
+
+/****************************************************************************************
+** NAME: FlashInit
+** PARAMETER: none
+** RETURN VALUE: none
+** DESCRIPTION: Initializes the flash driver.
+**
+****************************************************************************************/
+void FlashInit(void)
+{
+ /* check the flash block data buffer alignments */
+ if ((((blt_addr)blockInfo.data % 4) != 0) || (((blt_addr)bootBlockInfo.data % 4) != 0))
+ {
+ /* incorrect alignment */
+ ASSERT_RT(BLT_FALSE);
+ }
+ /* init the flash block info structs by setting the address to an invalid address */
+ blockInfo.base_addr = FLASH_INVALID_ADDRESS;
+ bootBlockInfo.base_addr = FLASH_INVALID_ADDRESS;
+} /*** end of FlashInit ***/
+
+
+/****************************************************************************************
+** NAME: FlashWrite
+** PARAMETER: addr start address
+** len length in bytes
+** data pointer to the data buffer.
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Writes the data to flash through a flash block manager. Note that this
+** function also checks that no data is programmed outside the flash
+** memory region, so the bootloader can never be overwritten.
+**
+****************************************************************************************/
+blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
+{
+ blt_addr base_addr;
+
+ /* make sure the addresses are within the flash device */
+ if ( (FlashGetSector(addr) == FLASH_INVALID_SECTOR) || \
+ (FlashGetSector(addr+len-1) == FLASH_INVALID_SECTOR) )
+ {
+ return BLT_FALSE;
+ }
+
+ /* if this is the bootblock, then let the boot block manager handle it */
+ base_addr = (addr/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
+ if (base_addr == flashLayout[0].sector_start)
+ {
+ /* let the boot block manager handle it */
+ return FlashAddToBlock(&bootBlockInfo, addr, data, len);
+ }
+ /* let the block manager handle it */
+ return FlashAddToBlock(&blockInfo, addr, data, len);
+} /*** end of FlashWrite ***/
+
+
+/****************************************************************************************
+** NAME: FlashErase
+** PARAMETER: addr start address
+** len length in bytes
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Erases the flash memory. Note that this function also checks that no
+** data is erased outside the flash memory region, so the bootloader can
+** never be erased.
+**
+****************************************************************************************/
+blt_bool FlashErase(blt_addr addr, blt_int32u len)
+{
+ blt_int8u first_sector;
+ blt_int8u last_sector;
+
+ /* obtain the first and last sector number */
+ first_sector = FlashGetSector(addr);
+ last_sector = FlashGetSector(addr+len-1);
+ /* check them */
+ if ( (first_sector == FLASH_INVALID_SECTOR) || (last_sector == FLASH_INVALID_SECTOR) )
+ {
+ return BLT_FALSE;
+ }
+ /* erase the sectors */
+ return FlashEraseSectors(first_sector, last_sector);
+} /*** end of FlashErase ***/
+
+
+/****************************************************************************************
+** NAME: FlashWriteChecksum
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
+** DESCRIPTION: Writes a checksum of the user program to non-volatile memory. This is
+** performed once the entire user program has been programmed. Through
+** the checksum, the bootloader can check if the programming session
+** was completed, which indicates that a valid user programming is
+** present and can be started.
+**
+****************************************************************************************/
+blt_bool FlashWriteChecksum(void)
+{
+ blt_int32u signature_checksum = 0;
+
+ /* The ARM7 core already has a spot reserved for a checksum that the bootloader can
+ * store at the end of a programming session.
+ *
+ * Layout of the vector table (* = don't care)
+ * 0x******00 Reset Exception
+ * 0x******04 Undefined Instruction Exception
+ * 0x******08 Software Interrupt Exception
+ * 0x******0C Prefetch Exception
+ * 0x******10 Abort Exception
+ * 0x******14 [reserved for signature checksum]
+ * 0x******18 IRQ Exception
+ * 0x******1C FIQ Exception
+ *
+ * signature_checksum = Two's complement of (SUM(exception address values))
+ */
+
+ /* compute the checksum. note that the user program's vectors are not yet written
+ * to flash but are present in the bootblock data structure at this point.
+ */
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x00]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x04]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x08]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x0C]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x10]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x18]));
+ signature_checksum += *((blt_int32u*)(&bootBlockInfo.data[0+0x1C]));
+ signature_checksum = ~signature_checksum; /* one's complement */
+ signature_checksum += 1; /* two's complement */
+
+ /* check that this value of the checksum is not already present, which means
+ * the program area with the vector table was not programmed, so the checksum
+ * also doesn't need to be written. this check is important because it allows
+ * for additional data to be programmed, such as calibration parameters, in
+ * which case the checksum doesn't not need to be rewritten
+ */
+ if (signature_checksum == FlashVerifyChecksum())
+ {
+ return BLT_TRUE;
+ }
+ /* write the checksum */
+ return FlashWrite(flashLayout[0].sector_start+0x14, sizeof(blt_addr),
+ (blt_int8u*)&signature_checksum);
+} /*** end of FlashWriteChecksum ***/
+
+
+/****************************************************************************************
+** NAME: FlashVerifyChecksum
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is successful, BTL_FALSE otherwise.
+** DESCRIPTION: Verifies the checksum, which indicates that a valid user program is
+** present and can be started.
+**
+****************************************************************************************/
+blt_bool FlashVerifyChecksum(void)
+{
+ blt_int32u signature_checksum = 0;
+
+ /* verify the checksum based on how it was written by CpuWriteChecksum() */
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x04));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x08));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x0C));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x10));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x14));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x18));
+ signature_checksum += *((blt_int32u*)(flashLayout[0].sector_start+0x1C));
+
+ /* sum should add up to an unsigned 32-bit value of 0 */
+ if (signature_checksum == 0)
+ {
+ /* checksum okay */
+ return BLT_TRUE;
+ }
+ /* checksum incorrect */
+ return BLT_FALSE;
+} /*** end of FlashVerifyChecksum ***/
+
+
+/****************************************************************************************
+** NAME: FlashDone
+** PARAMETER: none
+** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
+** DESCRIPTION: Finilizes the flash driver operations. There could still be data in
+** the currently active block that needs to be flashed.
+**
+****************************************************************************************/
+blt_bool FlashDone(void)
+{
+ /* check if there is still data waiting to be programmed in the boot block */
+ if (bootBlockInfo.base_addr != FLASH_INVALID_ADDRESS)
+ {
+ if (FlashWriteBlock(&bootBlockInfo) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* check if there is still data waiting to be programmed */
+ if (blockInfo.base_addr != FLASH_INVALID_ADDRESS)
+ {
+ if (FlashWriteBlock(&blockInfo) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+ /* still here so all is okay */
+ return BLT_TRUE;
+} /*** end of FlashDone ***/
+
+
+/****************************************************************************************
+** NAME: FlashInitBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** address base address of the block data.
+** RETURN VALUE: BLT_TRUE is succesful, BLT_FALSE otherwise.
+** DESCRIPTION: Copies data currently in flash to the block->data and sets the
+** base address.
+**
+****************************************************************************************/
+static blt_bool FlashInitBlock(tFlashBlockInfo *block, blt_addr address)
+{
+ /* check address alignment */
+ if ((address % FLASH_WRITE_BLOCK_SIZE) != 0)
+ {
+ return BLT_FALSE;
+ }
+ /* make sure that we are initializing a new block and not the same one */
+ if (block->base_addr == address)
+ {
+ /* block already initialized, so nothing to do */
+ return BLT_TRUE;
+ }
+ /* set the base address and copies the current data from flash */
+ block->base_addr = address;
+ CpuMemCopy((blt_addr)block->data, address, FLASH_WRITE_BLOCK_SIZE);
+ return BLT_TRUE;
+} /*** end of FlashInitBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashSwitchBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** base_addr base address for the next block
+** RETURN VALUE: the pointer of the block info struct that is no being used, or a NULL
+** pointer in case of error.
+** DESCRIPTION: Switches blocks by programming the current one and initializing the
+** next.
+**
+****************************************************************************************/
+static tFlashBlockInfo *FlashSwitchBlock(tFlashBlockInfo *block, blt_addr base_addr)
+{
+ /* check if a switch needs to be made away from the boot block. in this case the boot
+ * block shouldn't be written yet, because this is done at the end of the programming
+ * session by FlashDone(), this is right after the checksum was written.
+ */
+ if (block == &bootBlockInfo)
+ {
+ /* switch from the boot block to the generic block info structure */
+ block = &blockInfo;
+ }
+ /* check if a switch back into the bootblock is needed. in this case the generic block
+ * doesn't need to be written here yet.
+ */
+ else if (base_addr == flashLayout[0].sector_start)
+ {
+ /* switch from the generic block to the boot block info structure */
+ block = &bootBlockInfo;
+ base_addr = flashLayout[0].sector_start;
+ }
+ else
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ if (FlashWriteBlock(block) == BLT_FALSE)
+ {
+ return BLT_NULL;
+ }
+ }
+
+ /* initialize tne new block when necessary */
+ if (FlashInitBlock(block, base_addr) == BLT_FALSE)
+ {
+ return BLT_NULL;
+ }
+
+ /* still here to all is okay */
+ return block;
+} /*** end of FlashSwitchBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashAddToBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** address flash destination address
+** data pointer to the byte array with data
+** len number of bytes to add to the block
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Programming is done per block. This function adds data to the block
+** that is currently collecting data to be written to flash. If the
+** address is outside of the current block, the current block is written
+** to flash an a new block is initialized.
+**
+****************************************************************************************/
+static blt_bool FlashAddToBlock(tFlashBlockInfo *block, blt_addr address,
+ blt_int8u *data, blt_int16u len)
+{
+ blt_addr current_base_addr;
+ blt_int8u *dst;
+ blt_int8u *src;
+
+ /* determine the current base address */
+ current_base_addr = (address/FLASH_WRITE_BLOCK_SIZE)*FLASH_WRITE_BLOCK_SIZE;
+
+ /* make sure the blockInfo is not uninitialized */
+ if (block->base_addr == FLASH_INVALID_ADDRESS)
+ {
+ /* initialize the blockInfo struct for the current block */
+ if (FlashInitBlock(block, current_base_addr) == BLT_FALSE)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* check if the new data fits in the current block */
+ if (block->base_addr != current_base_addr)
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ block = FlashSwitchBlock(block, current_base_addr);
+ if (block == BLT_NULL)
+ {
+ return BLT_FALSE;
+ }
+ }
+
+ /* add the data to the current block, but check for block overflow */
+ dst = &(block->data[address - block->base_addr]);
+ src = data;
+ do
+ {
+ /* keep the watchdog happy */
+ CopService();
+ /* buffer overflow? */
+ if ((blt_addr)(dst-&(block->data[0])) >= FLASH_WRITE_BLOCK_SIZE)
+ {
+ /* need to switch to a new block, so program the current one and init the next */
+ block = FlashSwitchBlock(block, current_base_addr+FLASH_WRITE_BLOCK_SIZE);
+ if (block == BLT_NULL)
+ {
+ return BLT_FALSE;
+ }
+ /* reset destination pointer */
+ dst = &(block->data[0]);
+ }
+ /* write the data to the buffer */
+ *dst = *src;
+ /* update pointers */
+ dst++;
+ src++;
+ /* decrement byte counter */
+ len--;
+ }
+ while (len > 0);
+ /* still here so all is good */
+ return BLT_TRUE;
+} /*** end of FlashAddToBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashWriteBlock
+** PARAMETER: block pointer to flash block info structure to operate on.
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Programs FLASH_WRITE_BLOCK_SIZE bytes to flash from the block->data
+** array.
+**
+****************************************************************************************/
+static blt_bool FlashWriteBlock(tFlashBlockInfo *block)
+{
+ blt_int32u iap_command[5];
+ blt_int32u iap_result[3];
+ blt_int8u sector_num;
+ pIapHandler iapHandler = (void *)IAP_ENTRY_ADDRESS;
+
+ /* check that address is actually within flash */
+ sector_num = FlashGetSector(block->base_addr);
+ if (sector_num == FLASH_INVALID_SECTOR)
+ {
+ return BLT_FALSE;
+ }
+ /* send the prepare sector command for just this one sector */
+ iap_command[0] = IAP_CMD_PREPARE_SECTORS;
+ iap_command[1] = sector_num;
+ iap_command[2] = sector_num;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* send the erase sector command */
+ iap_command[0] = IAP_CMD_COPY_RAM_TO_FLASH;
+ iap_command[1] = (blt_int32u)block->base_addr;
+ iap_command[2] = (blt_int32u)block->data;
+ iap_command[3] = FLASH_WRITE_BLOCK_SIZE;
+ iap_command[4] = BOOT_CPU_SYSTEM_SPEED_KHZ;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* perform a comparison for verification purposes */
+ iap_command[0] = IAP_CMD_COMPARE;
+ iap_command[1] = (blt_int32u)block->base_addr;
+ iap_command[2] = (blt_int32u)block->data;
+ iap_command[3] = FLASH_WRITE_BLOCK_SIZE;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* still here so all is okay */
+ return BLT_TRUE;
+
+} /*** end of FlashWriteBlock ***/
+
+
+/****************************************************************************************
+** NAME: FlashEraseSectors
+** PARAMETER: first_sector first flash sector number
+** last_sector last flash sector number
+** RETURN VALUE: BLT_TRUE if successful, BLT_FALSE otherwise.
+** DESCRIPTION: Erases the flash sectors from first_sector up until last_sector
+**
+****************************************************************************************/
+static blt_bool FlashEraseSectors(blt_int8u first_sector, blt_int8u last_sector)
+{
+ blt_int32u iap_command[5];
+ blt_int32u iap_result[3];
+ pIapHandler iapHandler = (void *)IAP_ENTRY_ADDRESS;
+
+ /* validate the sector numbers */
+ if (first_sector > last_sector)
+ {
+ return BLT_FALSE;
+ }
+ if ( (first_sector < flashLayout[0].sector_num) || \
+ (last_sector > flashLayout[FLASH_TOTAL_SECTORS-1].sector_num) )
+ {
+ return BLT_FALSE;
+ }
+
+ /* send the prepare sector command for just this one sector */
+ iap_command[0] = IAP_CMD_PREPARE_SECTORS;
+ iap_command[1] = first_sector;
+ iap_command[2] = last_sector;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* send the erase sector command */
+ iap_command[0] = IAP_CMD_ERASE_SECTORS;
+ iap_command[1] = first_sector;
+ iap_command[2] = last_sector;
+ iap_command[3] = BOOT_CPU_SYSTEM_SPEED_KHZ;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* perform a blank check for verification purposes */
+ iap_command[0] = IAP_CMD_BLANK_CHECK_SECTORS ;
+ iap_command[1] = first_sector;
+ iap_command[2] = last_sector;
+ iap_result[0] = !IAP_CMD_SUCCESS;
+ /* service the watchdog before calling the IAP handler */
+ CopService();
+ iapHandler(iap_command, iap_result);
+ if (iap_result[0] != IAP_CMD_SUCCESS)
+ {
+ return BLT_FALSE;
+ }
+ /* still here so all went okay */
+ return BLT_TRUE;
+} /*** end of FlashEraseSectors ***/
+
+
+/****************************************************************************************
+** NAME: FlashGetSector
+** PARAMETER: address address in the flash sector
+** RETURN VALUE: flash sector number or FLASH_INVALID_SECTOR
+** DESCRIPTION: Determines the flash sector the address is in.
+**
+****************************************************************************************/
+static blt_int8u FlashGetSector(blt_addr address)
+{
+ blt_int8u sectorIdx;
+
+ /* search through the sectors to find the right one */
+ for (sectorIdx = 0; sectorIdx < FLASH_TOTAL_SECTORS; sectorIdx++)
+ {
+ /* keep the watchdog happy */
+ CopService();
+ /* is the address in this sector? */
+ if ( (address >= flashLayout[sectorIdx].sector_start) && \
+ (address < (flashLayout[sectorIdx].sector_start + \
+ flashLayout[sectorIdx].sector_size)) )
+ {
+ /* return the sector number */
+ return flashLayout[sectorIdx].sector_num;
+ }
+ }
+ /* still here so no valid sector found */
+ return FLASH_INVALID_SECTOR;
+} /*** end of FlashGetSector ***/
+
+
+/*********************************** end of flash.c ************************************/
diff --git a/Target/Source/ARM7_LPC2000/Crossworks/flash.h b/Target/Source/ARM7_LPC2000/Crossworks/flash.h
new file mode 100644
index 00000000..9cae116f
--- /dev/null
+++ b/Target/Source/ARM7_LPC2000/Crossworks/flash.h
@@ -0,0 +1,46 @@
+/****************************************************************************************
+| Description: bootloader flash driver header file
+| File Name: flash.h
+|
+|----------------------------------------------------------------------------------------
+| C O P Y R I G H T
+|----------------------------------------------------------------------------------------
+| Copyright (c) 2011 by Feaser http://www.feaser.com All rights reserved
+|
+|----------------------------------------------------------------------------------------
+| L I C E N S E
+|----------------------------------------------------------------------------------------
+| This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
+| modify it under the terms of the GNU General Public License as published by the Free
+| Software Foundation, either version 3 of the License, or (at your option) any later
+| version.
+|
+| OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+| without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+| PURPOSE. See the GNU General Public License for more details.
+|
+| You should have received a copy of the GNU General Public License along with OpenBLT.
+| If not, see .
+|
+| A special exception to the GPL is included to allow you to distribute a combined work
+| that includes OpenBLT without being obliged to provide the source code for any
+| proprietary components. The exception text is included at the bottom of the license
+| file .
+|
+****************************************************************************************/
+#ifndef FLASH_H
+#define FLASH_H
+
+/****************************************************************************************
+* Function prototypes
+****************************************************************************************/
+void FlashInit(void);
+blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
+blt_bool FlashErase(blt_addr addr, blt_int32u len);
+blt_bool FlashWriteChecksum(void);
+blt_bool FlashVerifyChecksum(void);
+blt_bool FlashDone(void);
+
+
+#endif /* FLASH_H */
+/*********************************** end of flash.h ************************************/
diff --git a/Target/Source/ARM7_LPC2000/Crossworks/memory.x b/Target/Source/ARM7_LPC2000/Crossworks/memory.x
new file mode 100644
index 00000000..e6148c8a
--- /dev/null
+++ b/Target/Source/ARM7_LPC2000/Crossworks/memory.x
@@ -0,0 +1,356 @@
+MEMORY
+{
+ UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+ AHB_Peripherals (wx) : ORIGIN = 0xffe00000, LENGTH = 0x00200000
+ VPB_Peripherals (wx) : ORIGIN = 0xe0000000, LENGTH = 0x00200000
+ BANK3 (wx) : ORIGIN = 0x83000000, LENGTH = 0x01000000
+ BANK2 (wx) : ORIGIN = 0x82000000, LENGTH = 0x01000000
+ External_SRAM (wx) : ORIGIN = 0x81000000, LENGTH = 0x00100000
+ External_FLASH (rx) : ORIGIN = 0x80000000, LENGTH = 0x00400000
+ SRAM (wx) : ORIGIN = 0x40000200, LENGTH = 0x00001CE0
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00002000
+}
+
+
+SECTIONS
+{
+ __AHB_Peripherals_segment_start__ = 0xffe00000;
+ __AHB_Peripherals_segment_end__ = 0x00000000;
+ __VPB_Peripherals_segment_start__ = 0xe0000000;
+ __VPB_Peripherals_segment_end__ = 0xe0200000;
+ __BANK3_segment_start__ = 0x83000000;
+ __BANK3_segment_end__ = 0x84000000;
+ __BANK2_segment_start__ = 0x82000000;
+ __BANK2_segment_end__ = 0x83000000;
+ __External_SRAM_segment_start__ = 0x81000000;
+ __External_SRAM_segment_end__ = 0x81100000;
+ __External_FLASH_segment_start__ = 0x80000000;
+ __External_FLASH_segment_end__ = 0x80400000;
+ __SRAM_segment_start__ = 0x40000200;
+ __SRAM_segment_end__ = 0x40001EE0;
+ __FLASH_segment_start__ = 0x00000000;
+ __FLASH_segment_end__ = 0x00002000;
+
+ __STACKSIZE__ = 1024;
+ __STACKSIZE_IRQ__ = 256;
+ __STACKSIZE_FIQ__ = 256;
+ __STACKSIZE_SVC__ = 0;
+ __STACKSIZE_ABT__ = 0;
+ __STACKSIZE_UND__ = 0;
+ __HEAPSIZE__ = 1024;
+
+ __text2_load_start__ = ALIGN(__External_FLASH_segment_start__ , 4);
+ .text2 ALIGN(__External_FLASH_segment_start__ , 4) : AT(ALIGN(__External_FLASH_segment_start__ , 4))
+ {
+ __text2_start__ = .;
+ *(.text2 .text2.*)
+ }
+ __text2_end__ = __text2_start__ + SIZEOF(.text2);
+
+ __text2_load_end__ = __text2_end__;
+
+ . = ASSERT(__text2_end__ >= __External_FLASH_segment_start__ && __text2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .text2 is too large to fit in External_FLASH memory segment");
+
+ __rodata2_load_start__ = ALIGN(__text2_end__ , 4);
+ .rodata2 ALIGN(__text2_end__ , 4) : AT(ALIGN(__text2_end__ , 4))
+ {
+ __rodata2_start__ = .;
+ *(.rodata2 .rodata2.*)
+ }
+ __rodata2_end__ = __rodata2_start__ + SIZEOF(.rodata2);
+
+ __rodata2_load_end__ = __rodata2_end__;
+
+ . = ASSERT(__rodata2_end__ >= __External_FLASH_segment_start__ && __rodata2_end__ <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .rodata2 is too large to fit in External_FLASH memory segment");
+
+ __data2_load_start__ = ALIGN(__rodata2_end__ , 4);
+ .data2 ALIGN(__External_SRAM_segment_start__ , 4) : AT(ALIGN(__rodata2_end__ , 4))
+ {
+ __data2_start__ = .;
+ *(.data2 .data2.*)
+ }
+ __data2_end__ = __data2_start__ + SIZEOF(.data2);
+
+ __data2_load_end__ = __data2_load_start__ + SIZEOF(.data2);
+
+ __External_FLASH_segment_used_end__ = ALIGN(__rodata2_end__ , 4) + SIZEOF(.data2);
+
+ . = ASSERT((__data2_load_start__ + SIZEOF(.data2)) >= __External_FLASH_segment_start__ && (__data2_load_start__ + SIZEOF(.data2)) <= (__External_FLASH_segment_start__ + 0x00400000) , "error: .data2 is too large to fit in External_FLASH memory segment");
+
+ .data2_run ALIGN(__External_SRAM_segment_start__ , 4) (NOLOAD) :
+ {
+ __data2_run_start__ = .;
+ . = MAX(__data2_run_start__ + SIZEOF(.data2), .);
+ }
+ __data2_run_end__ = __data2_run_start__ + SIZEOF(.data2_run);
+
+ __data2_run_load_end__ = __data2_run_end__;
+
+ . = ASSERT(__data2_run_end__ >= __External_SRAM_segment_start__ && __data2_run_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .data2_run is too large to fit in External_SRAM memory segment");
+
+ __bss2_load_start__ = ALIGN(__data2_run_end__ , 4);
+ .bss2 ALIGN(__data2_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data2_run_end__ , 4))
+ {
+ __bss2_start__ = .;
+ *(.bss2 .bss2.*)
+ }
+ __bss2_end__ = __bss2_start__ + SIZEOF(.bss2);
+
+ __bss2_load_end__ = __bss2_end__;
+
+ __External_SRAM_segment_used_end__ = ALIGN(__data2_run_end__ , 4) + SIZEOF(.bss2);
+
+ . = ASSERT(__bss2_end__ >= __External_SRAM_segment_start__ && __bss2_end__ <= (__External_SRAM_segment_start__ + 0x00100000) , "error: .bss2 is too large to fit in External_SRAM memory segment");
+
+ __vectors_ram_load_start__ = __SRAM_segment_start__;
+ .vectors_ram __SRAM_segment_start__ (NOLOAD) : AT(__SRAM_segment_start__)
+ {
+ __vectors_ram_start__ = .;
+ *(.vectors_ram .vectors_ram.*)
+ . = MAX(__vectors_ram_start__ + 0x0000003C , .);
+ }
+ __vectors_ram_end__ = __vectors_ram_start__ + SIZEOF(.vectors_ram);
+
+ __vectors_ram_load_end__ = __vectors_ram_end__;
+
+ . = ASSERT(__vectors_ram_end__ >= __SRAM_segment_start__ && __vectors_ram_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .vectors_ram is too large to fit in SRAM memory segment");
+
+ __vectors_load_start__ = __FLASH_segment_start__;
+ .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
+ {
+ __vectors_start__ = .;
+ *(.vectors .vectors.*)
+ }
+ __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+ __vectors_load_end__ = __vectors_end__;
+
+ . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+ __init_load_start__ = ALIGN(__vectors_end__ , 4);
+ .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+ {
+ __init_start__ = .;
+ *(.init .init.*)
+ }
+ __init_end__ = __init_start__ + SIZEOF(.init);
+
+ __init_load_end__ = __init_end__;
+
+ . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .init is too large to fit in FLASH memory segment");
+
+ __text_load_start__ = ALIGN(__init_end__ , 4);
+ .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+ {
+ __text_start__ = .;
+ *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+ }
+ __text_end__ = __text_start__ + SIZEOF(.text);
+
+ __text_load_end__ = __text_end__;
+
+ . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .text is too large to fit in FLASH memory segment");
+
+ __dtors_load_start__ = ALIGN(__text_end__ , 4);
+ .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+ {
+ __dtors_start__ = .;
+ KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+ }
+ __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+ __dtors_load_end__ = __dtors_end__;
+
+ . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+ __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+ .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+ {
+ __ctors_start__ = .;
+ KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+ }
+ __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+ __ctors_load_end__ = __ctors_end__;
+
+ . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+ __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+ .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+ {
+ __rodata_start__ = .;
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ }
+ __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+ __rodata_load_end__ = __rodata_end__;
+
+ . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00040000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+ __data_load_start__ = ALIGN(__rodata_end__ , 4);
+ .data ALIGN(__vectors_ram_end__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+ {
+ __data_start__ = .;
+ *(.data .data.* .gnu.linkonce.d.*)
+ }
+ __data_end__ = __data_start__ + SIZEOF(.data);
+
+ __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+ . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .data is too large to fit in FLASH memory segment");
+
+ .data_run ALIGN(__vectors_ram_end__ , 4) (NOLOAD) :
+ {
+ __data_run_start__ = .;
+ . = MAX(__data_run_start__ + SIZEOF(.data), .);
+ }
+ __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+ __data_run_load_end__ = __data_run_end__;
+
+ . = ASSERT(__data_run_end__ >= __SRAM_segment_start__ && __data_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .data_run is too large to fit in SRAM memory segment");
+
+ __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+ .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+ {
+ __bss_start__ = .;
+ *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+ }
+ __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+ __bss_load_end__ = __bss_end__;
+
+ . = ASSERT(__bss_end__ >= __SRAM_segment_start__ && __bss_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .bss is too large to fit in SRAM memory segment");
+
+ __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+ .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+ {
+ __non_init_start__ = .;
+ *(.non_init .non_init.*)
+ }
+ __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+ __non_init_load_end__ = __non_init_end__;
+
+ . = ASSERT(__non_init_end__ >= __SRAM_segment_start__ && __non_init_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .non_init is too large to fit in SRAM memory segment");
+
+ __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+ .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+ {
+ __heap_start__ = .;
+ *(.heap .heap.*)
+ . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+ }
+ __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+ __heap_load_end__ = __heap_end__;
+
+ . = ASSERT(__heap_end__ >= __SRAM_segment_start__ && __heap_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .heap is too large to fit in SRAM memory segment");
+
+ __stack_load_start__ = ALIGN(__heap_end__ , 4);
+ .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+ {
+ __stack_start__ = .;
+ *(.stack .stack.*)
+ . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+ }
+ __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+ __stack_load_end__ = __stack_end__;
+
+ . = ASSERT(__stack_end__ >= __SRAM_segment_start__ && __stack_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack is too large to fit in SRAM memory segment");
+
+ __stack_irq_load_start__ = ALIGN(__stack_end__ , 4);
+ .stack_irq ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+ {
+ __stack_irq_start__ = .;
+ *(.stack_irq .stack_irq.*)
+ . = ALIGN(MAX(__stack_irq_start__ + __STACKSIZE_IRQ__ , .), 4);
+ }
+ __stack_irq_end__ = __stack_irq_start__ + SIZEOF(.stack_irq);
+
+ __stack_irq_load_end__ = __stack_irq_end__;
+
+ . = ASSERT(__stack_irq_end__ >= __SRAM_segment_start__ && __stack_irq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_irq is too large to fit in SRAM memory segment");
+
+ __stack_fiq_load_start__ = ALIGN(__stack_irq_end__ , 4);
+ .stack_fiq ALIGN(__stack_irq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_irq_end__ , 4))
+ {
+ __stack_fiq_start__ = .;
+ *(.stack_fiq .stack_fiq.*)
+ . = ALIGN(MAX(__stack_fiq_start__ + __STACKSIZE_FIQ__ , .), 4);
+ }
+ __stack_fiq_end__ = __stack_fiq_start__ + SIZEOF(.stack_fiq);
+
+ __stack_fiq_load_end__ = __stack_fiq_end__;
+
+ . = ASSERT(__stack_fiq_end__ >= __SRAM_segment_start__ && __stack_fiq_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_fiq is too large to fit in SRAM memory segment");
+
+ __stack_svc_load_start__ = ALIGN(__stack_fiq_end__ , 4);
+ .stack_svc ALIGN(__stack_fiq_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_fiq_end__ , 4))
+ {
+ __stack_svc_start__ = .;
+ *(.stack_svc .stack_svc.*)
+ . = ALIGN(MAX(__stack_svc_start__ + __STACKSIZE_SVC__ , .), 4);
+ }
+ __stack_svc_end__ = __stack_svc_start__ + SIZEOF(.stack_svc);
+
+ __stack_svc_load_end__ = __stack_svc_end__;
+
+ . = ASSERT(__stack_svc_end__ >= __SRAM_segment_start__ && __stack_svc_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_svc is too large to fit in SRAM memory segment");
+
+ __stack_abt_load_start__ = ALIGN(__stack_svc_end__ , 4);
+ .stack_abt ALIGN(__stack_svc_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_svc_end__ , 4))
+ {
+ __stack_abt_start__ = .;
+ *(.stack_abt .stack_abt.*)
+ . = ALIGN(MAX(__stack_abt_start__ + __STACKSIZE_ABT__ , .), 4);
+ }
+ __stack_abt_end__ = __stack_abt_start__ + SIZEOF(.stack_abt);
+
+ __stack_abt_load_end__ = __stack_abt_end__;
+
+ . = ASSERT(__stack_abt_end__ >= __SRAM_segment_start__ && __stack_abt_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_abt is too large to fit in SRAM memory segment");
+
+ __stack_und_load_start__ = ALIGN(__stack_abt_end__ , 4);
+ .stack_und ALIGN(__stack_abt_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_abt_end__ , 4))
+ {
+ __stack_und_start__ = .;
+ *(.stack_und .stack_und.*)
+ . = ALIGN(MAX(__stack_und_start__ + __STACKSIZE_UND__ , .), 4);
+ }
+ __stack_und_end__ = __stack_und_start__ + SIZEOF(.stack_und);
+
+ __stack_und_load_end__ = __stack_und_end__;
+
+ . = ASSERT(__stack_und_end__ >= __SRAM_segment_start__ && __stack_und_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .stack_und is too large to fit in SRAM memory segment");
+
+ __fast_load_start__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4);
+ .fast ALIGN(__stack_und_end__ , 4) : AT(ALIGN(__data_load_start__ + SIZEOF(.data) , 4))
+ {
+ __fast_start__ = .;
+ *(.fast .fast.*)
+ }
+ __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+ __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+ __FLASH_segment_used_end__ = ALIGN(__data_load_start__ + SIZEOF(.data) , 4) + SIZEOF(.fast);
+
+ . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00040000) , "error: .fast is too large to fit in FLASH memory segment");
+
+ .fast_run ALIGN(__stack_und_end__ , 4) (NOLOAD) :
+ {
+ __fast_run_start__ = .;
+ . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+ }
+ __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+ __fast_run_load_end__ = __fast_run_end__;
+
+ __SRAM_segment_used_end__ = ALIGN(__stack_und_end__ , 4) + SIZEOF(.fast_run);
+
+ . = ASSERT(__fast_run_end__ >= __SRAM_segment_start__ && __fast_run_end__ <= (__SRAM_segment_start__ + 0x00004000) , "error: .fast_run is too large to fit in SRAM memory segment");
+
+}
+
diff --git a/Target/Source/ARM7_LPC2000/GCC/flash.c b/Target/Source/ARM7_LPC2000/GCC/flash.c
index 5e10bc44..f8fe1ab7 100644
--- a/Target/Source/ARM7_LPC2000/GCC/flash.c
+++ b/Target/Source/ARM7_LPC2000/GCC/flash.c
@@ -282,9 +282,7 @@ blt_bool FlashWriteChecksum(void)
blt_int32u signature_checksum = 0;
/* The ARM7 core already has a spot reserved for a checksum that the bootloader can
- * store at the end of a programming session. In order for the bootloader to be able
- * to program the checksum, it is important that address 0x******14, which is reserved
- * for the checksum, is set to 0xffffffff in the user program.
+ * store at the end of a programming session.
*
* Layout of the vector table (* = don't care)
* 0x******00 Reset Exception
@@ -312,6 +310,16 @@ blt_bool FlashWriteChecksum(void)
signature_checksum = ~signature_checksum; /* one's complement */
signature_checksum += 1; /* two's complement */
+ /* check that this value of the checksum is not already present, which means
+ * the program area with the vector table was not programmed, so the checksum
+ * also doesn't need to be written. this check is important because it allows
+ * for additional data to be programmed, such as calibration parameters, in
+ * which case the checksum doesn't not need to be rewritten
+ */
+ if (signature_checksum == FlashVerifyChecksum())
+ {
+ return BLT_TRUE;
+ }
/* write the checksum */
return FlashWrite(flashLayout[0].sector_start+0x14, sizeof(blt_addr),
(blt_int8u*)&signature_checksum);
diff --git a/Target/Source/ARM7_LPC2000/GCC/memory.x b/Target/Source/ARM7_LPC2000/GCC/memory.x
index a31919b0..8e94216b 100644
--- a/Target/Source/ARM7_LPC2000/GCC/memory.x
+++ b/Target/Source/ARM7_LPC2000/GCC/memory.x
@@ -7,7 +7,7 @@ ENTRY(_startup)
*/
MEMORY
{
- flash : ORIGIN = 0x00000000, LENGTH = 16K /* FLASH ROM reserved for the bootloader */
+ flash : ORIGIN = 0x00000000, LENGTH = 8K /* FLASH ROM reserved for the bootloader */
ram_vectors(A) : ORIGIN = 0x40000000, LENGTH = 64 /* RAM vectors of the user program */
ram_monitor(A) : ORIGIN = 0x40000040, LENGTH = 224 /* variables used by Philips RealMonitor */
ram_isp_low(A) : ORIGIN = 0x40000120, LENGTH = 224 /* variables used by Philips ISP bootloader */