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431 lines
13 KiB
431 lines
13 KiB
#ifndef _ASM_POWERPC_PTRACE_H |
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#define _ASM_POWERPC_PTRACE_H |
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/* |
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* Copyright (C) 2001 PPC64 Team, IBM Corp |
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* |
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* This struct defines the way the registers are stored on the |
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* kernel stack during a system call or other kernel entry. |
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* |
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* this should only contain volatile regs |
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* since we can keep non-volatile in the thread_struct |
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* should set this up when only volatiles are saved |
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* by intr code. |
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* |
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* Since this is going on the stack, *CARE MUST BE TAKEN* to insure |
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* that the overall structure is a multiple of 16 bytes in length. |
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* |
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* Note that the offsets of the fields in this struct correspond with |
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* the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation; either version |
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* 2 of the License, or (at your option) any later version. |
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*/ |
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#ifdef __KERNEL__ |
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#include <linux/types.h> |
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#else |
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#include <stdint.h> |
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#endif |
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#ifndef __ASSEMBLY__ |
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struct pt_regs { |
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unsigned long gpr[32]; |
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unsigned long nip; |
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unsigned long msr; |
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unsigned long orig_gpr3; /* Used for restarting system calls */ |
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unsigned long ctr; |
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unsigned long link; |
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unsigned long xer; |
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unsigned long ccr; |
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#ifdef __powerpc64__ |
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unsigned long softe; /* Soft enabled/disabled */ |
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#else |
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unsigned long mq; /* 601 only (not used at present) */ |
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/* Used on APUS to hold IPL value. */ |
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#endif |
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unsigned long trap; /* Reason for being here */ |
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/* N.B. for critical exceptions on 4xx, the dar and dsisr |
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fields are overloaded to hold srr0 and srr1. */ |
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unsigned long dar; /* Fault registers */ |
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unsigned long dsisr; /* on 4xx/Book-E used for ESR */ |
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unsigned long result; /* Result of a system call */ |
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}; |
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#endif /* __ASSEMBLY__ */ |
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#ifdef __KERNEL__ |
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#ifdef __powerpc64__ |
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#define STACK_FRAME_OVERHEAD 112 /* size of minimum stack frame */ |
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#define STACK_FRAME_LR_SAVE 2 /* Location of LR in stack frame */ |
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#define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265) |
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#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + \ |
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STACK_FRAME_OVERHEAD + 288) |
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#define STACK_FRAME_MARKER 12 |
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/* Size of dummy stack frame allocated when calling signal handler. */ |
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#define __SIGNAL_FRAMESIZE 128 |
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#define __SIGNAL_FRAMESIZE32 64 |
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#else /* __powerpc64__ */ |
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#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ |
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#define STACK_FRAME_LR_SAVE 1 /* Location of LR in stack frame */ |
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#define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773) |
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#define STACK_INT_FRAME_SIZE (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD) |
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#define STACK_FRAME_MARKER 2 |
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/* Size of stack frame allocated when calling signal handler. */ |
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#define __SIGNAL_FRAMESIZE 64 |
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#endif /* __powerpc64__ */ |
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#ifndef __ASSEMBLY__ |
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#define instruction_pointer(regs) ((regs)->nip) |
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#define user_stack_pointer(regs) ((regs)->gpr[1]) |
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#define kernel_stack_pointer(regs) ((regs)->gpr[1]) |
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#define regs_return_value(regs) ((regs)->gpr[3]) |
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#ifdef CONFIG_SMP |
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extern unsigned long profile_pc(struct pt_regs *regs); |
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#else |
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#define profile_pc(regs) instruction_pointer(regs) |
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#endif |
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#ifdef __powerpc64__ |
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#define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1) |
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#else |
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#define user_mode(regs) (((regs)->msr & MSR_PR) != 0) |
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#endif |
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#define force_successful_syscall_return() \ |
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do { \ |
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set_thread_flag(TIF_NOERROR); \ |
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} while(0) |
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struct task_struct; |
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extern unsigned long ptrace_get_reg(struct task_struct *task, int regno); |
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extern int ptrace_put_reg(struct task_struct *task, int regno, |
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unsigned long data); |
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/* |
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* We use the least-significant bit of the trap field to indicate |
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* whether we have saved the full set of registers, or only a |
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* partial set. A 1 there means the partial set. |
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* On 4xx we use the next bit to indicate whether the exception |
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* is a critical exception (1 means it is). |
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*/ |
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#define FULL_REGS(regs) (((regs)->trap & 1) == 0) |
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#ifndef __powerpc64__ |
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#define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) != 0) |
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#define IS_MCHECK_EXC(regs) (((regs)->trap & 4) != 0) |
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#define IS_DEBUG_EXC(regs) (((regs)->trap & 8) != 0) |
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#endif /* ! __powerpc64__ */ |
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#define TRAP(regs) ((regs)->trap & ~0xF) |
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#ifdef __powerpc64__ |
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#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1) |
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#else |
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#define CHECK_FULL_REGS(regs) \ |
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do { \ |
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if ((regs)->trap & 1) \ |
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printk(KERN_CRIT "%s: partial register set\n", __func__); \ |
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} while (0) |
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#endif /* __powerpc64__ */ |
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#define arch_has_single_step() (1) |
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#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) |
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#define ARCH_HAS_USER_SINGLE_STEP_INFO |
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/* |
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* kprobe-based event tracer support |
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*/ |
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#include <linux/stddef.h> |
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#include <linux/thread_info.h> |
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extern int regs_query_register_offset(const char *name); |
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extern const char *regs_query_register_name(unsigned int offset); |
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#define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr)) |
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/** |
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* regs_get_register() - get register value from its offset |
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* @regs: pt_regs from which register value is gotten |
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* @offset: offset number of the register. |
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* |
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* regs_get_register returns the value of a register whose offset from @regs. |
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* The @offset is the offset of the register in struct pt_regs. |
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0. |
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*/ |
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static inline unsigned long regs_get_register(struct pt_regs *regs, |
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unsigned int offset) |
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{ |
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if (unlikely(offset > MAX_REG_OFFSET)) |
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return 0; |
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return *(unsigned long *)((unsigned long)regs + offset); |
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} |
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/** |
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* regs_within_kernel_stack() - check the address in the stack |
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* @regs: pt_regs which contains kernel stack pointer. |
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* @addr: address which is checked. |
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* |
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* regs_within_kernel_stack() checks @addr is within the kernel stack page(s). |
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* If @addr is within the kernel stack, it returns true. If not, returns false. |
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*/ |
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static inline bool regs_within_kernel_stack(struct pt_regs *regs, |
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unsigned long addr) |
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{ |
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return ((addr & ~(THREAD_SIZE - 1)) == |
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(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1))); |
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} |
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/** |
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* regs_get_kernel_stack_nth() - get Nth entry of the stack |
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* @regs: pt_regs which contains kernel stack pointer. |
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* @n: stack entry number. |
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* |
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* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which |
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* is specified by @regs. If the @n th entry is NOT in the kernel stack, |
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* this returns 0. |
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*/ |
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static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, |
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unsigned int n) |
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{ |
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unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs); |
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addr += n; |
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if (regs_within_kernel_stack(regs, (unsigned long)addr)) |
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return *addr; |
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else |
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return 0; |
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} |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __KERNEL__ */ |
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/* |
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* Offsets used by 'ptrace' system call interface. |
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* These can't be changed without breaking binary compatibility |
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* with MkLinux, etc. |
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*/ |
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#define PT_R0 0 |
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#define PT_R1 1 |
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#define PT_R2 2 |
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#define PT_R3 3 |
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#define PT_R4 4 |
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#define PT_R5 5 |
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#define PT_R6 6 |
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#define PT_R7 7 |
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#define PT_R8 8 |
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#define PT_R9 9 |
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#define PT_R10 10 |
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#define PT_R11 11 |
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#define PT_R12 12 |
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#define PT_R13 13 |
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#define PT_R14 14 |
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#define PT_R15 15 |
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#define PT_R16 16 |
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#define PT_R17 17 |
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#define PT_R18 18 |
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#define PT_R19 19 |
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#define PT_R20 20 |
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#define PT_R21 21 |
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#define PT_R22 22 |
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#define PT_R23 23 |
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#define PT_R24 24 |
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#define PT_R25 25 |
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#define PT_R26 26 |
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#define PT_R27 27 |
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#define PT_R28 28 |
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#define PT_R29 29 |
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#define PT_R30 30 |
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#define PT_R31 31 |
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#define PT_NIP 32 |
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#define PT_MSR 33 |
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#define PT_ORIG_R3 34 |
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#define PT_CTR 35 |
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#define PT_LNK 36 |
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#define PT_XER 37 |
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#define PT_CCR 38 |
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#ifndef __powerpc64__ |
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#define PT_MQ 39 |
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#else |
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#define PT_SOFTE 39 |
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#endif |
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#define PT_TRAP 40 |
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#define PT_DAR 41 |
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#define PT_DSISR 42 |
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#define PT_RESULT 43 |
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#define PT_REGS_COUNT 44 |
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#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ |
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#ifndef __powerpc64__ |
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#define PT_FPR31 (PT_FPR0 + 2*31) |
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#define PT_FPSCR (PT_FPR0 + 2*32 + 1) |
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#else /* __powerpc64__ */ |
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#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */ |
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#ifdef __KERNEL__ |
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#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */ |
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#endif |
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#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */ |
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#define PT_VSCR (PT_VR0 + 32*2 + 1) |
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#define PT_VRSAVE (PT_VR0 + 33*2) |
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#ifdef __KERNEL__ |
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#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */ |
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#define PT_VSCR_32 (PT_VR0 + 32*4 + 3) |
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#define PT_VRSAVE_32 (PT_VR0 + 33*4) |
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#endif |
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/* |
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* Only store first 32 VSRs here. The second 32 VSRs in VR0-31 |
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*/ |
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#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */ |
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#define PT_VSR31 (PT_VSR0 + 2*31) |
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#ifdef __KERNEL__ |
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#define PT_VSR0_32 300 /* each VSR reg occupies 4 slots in 32-bit */ |
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#endif |
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#endif /* __powerpc64__ */ |
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/* |
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* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. |
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* The transfer totals 34 quadword. Quadwords 0-31 contain the |
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* corresponding vector registers. Quadword 32 contains the vscr as the |
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* last word (offset 12) within that quadword. Quadword 33 contains the |
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* vrsave as the first word (offset 0) within the quadword. |
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* |
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* This definition of the VMX state is compatible with the current PPC32 |
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* ptrace interface. This allows signal handling and ptrace to use the same |
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* structures. This also simplifies the implementation of a bi-arch |
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* (combined (32- and 64-bit) gdb. |
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*/ |
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#define PTRACE_GETVRREGS 18 |
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#define PTRACE_SETVRREGS 19 |
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/* Get/set all the upper 32-bits of the SPE registers, accumulator, and |
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* spefscr, in one go */ |
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#define PTRACE_GETEVRREGS 20 |
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#define PTRACE_SETEVRREGS 21 |
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/* Get the first 32 128bit VSX registers */ |
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#define PTRACE_GETVSRREGS 27 |
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#define PTRACE_SETVSRREGS 28 |
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/* |
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* Get or set a debug register. The first 16 are DABR registers and the |
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* second 16 are IABR registers. |
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*/ |
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#define PTRACE_GET_DEBUGREG 25 |
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#define PTRACE_SET_DEBUGREG 26 |
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/* (new) PTRACE requests using the same numbers as x86 and the same |
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* argument ordering. Additionally, they support more registers too |
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*/ |
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#define PTRACE_GETREGS 12 |
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#define PTRACE_SETREGS 13 |
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#define PTRACE_GETFPREGS 14 |
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#define PTRACE_SETFPREGS 15 |
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#define PTRACE_GETREGS64 22 |
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#define PTRACE_SETREGS64 23 |
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/* (old) PTRACE requests with inverted arguments */ |
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#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */ |
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#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */ |
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#define PPC_PTRACE_GETFPREGS 0x97 /* Get FPRs 0 - 31 */ |
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#define PPC_PTRACE_SETFPREGS 0x96 /* Set FPRs 0 - 31 */ |
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/* Calls to trace a 64bit program from a 32bit program */ |
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#define PPC_PTRACE_PEEKTEXT_3264 0x95 |
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#define PPC_PTRACE_PEEKDATA_3264 0x94 |
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#define PPC_PTRACE_POKETEXT_3264 0x93 |
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#define PPC_PTRACE_POKEDATA_3264 0x92 |
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#define PPC_PTRACE_PEEKUSR_3264 0x91 |
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#define PPC_PTRACE_POKEUSR_3264 0x90 |
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#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ |
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#define PPC_PTRACE_GETHWDBGINFO 0x89 |
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#define PPC_PTRACE_SETHWDEBUG 0x88 |
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#define PPC_PTRACE_DELHWDEBUG 0x87 |
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#ifndef __ASSEMBLY__ |
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struct ppc_debug_info { |
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uint32_t version; /* Only version 1 exists to date */ |
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uint32_t num_instruction_bps; |
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uint32_t num_data_bps; |
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uint32_t num_condition_regs; |
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uint32_t data_bp_alignment; |
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uint32_t sizeof_condition; /* size of the DVC register */ |
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uint64_t features; |
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}; |
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#endif /* __ASSEMBLY__ */ |
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/* |
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* features will have bits indication whether there is support for: |
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*/ |
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#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001 |
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#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002 |
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#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004 |
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#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008 |
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#ifndef __ASSEMBLY__ |
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struct ppc_hw_breakpoint { |
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uint32_t version; /* currently, version must be 1 */ |
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uint32_t trigger_type; /* only some combinations allowed */ |
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uint32_t addr_mode; /* address match mode */ |
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uint32_t condition_mode; /* break/watchpoint condition flags */ |
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uint64_t addr; /* break/watchpoint address */ |
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uint64_t addr2; /* range end or mask */ |
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uint64_t condition_value; /* contents of the DVC register */ |
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}; |
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#endif /* __ASSEMBLY__ */ |
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/* |
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* Trigger Type |
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*/ |
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#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001 |
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#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002 |
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#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004 |
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#define PPC_BREAKPOINT_TRIGGER_RW \ |
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(PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE) |
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/* |
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* Address Mode |
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*/ |
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#define PPC_BREAKPOINT_MODE_EXACT 0x00000000 |
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#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001 |
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#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002 |
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#define PPC_BREAKPOINT_MODE_MASK 0x00000003 |
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/* |
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* Condition Mode |
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*/ |
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#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003 |
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#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000 |
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#define PPC_BREAKPOINT_CONDITION_AND 0x00000001 |
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#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND |
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#define PPC_BREAKPOINT_CONDITION_OR 0x00000002 |
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#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003 |
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#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 |
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#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 |
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#define PPC_BREAKPOINT_CONDITION_BE(n) \ |
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(1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) |
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#endif /* _ASM_POWERPC_PTRACE_H */
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