arm-soc: First batch of cleanups

These cleanups are basically all over the place. The idea is to collect
 changes with minimal impact but large number of changes so we can avoid
 them from distracting in the diffstat in the other series.
 
 A significant number of lines get removed here, in particular because
 the ixp2000 and ixp23xx platforms get removed. These have never been
 extremely popular and have fallen into disuse over time with no active
 maintainer taking care of them. The u5500 soc never made it into a
 product, so we are removing it from the ux500 platform.
 
 Many good cleanups also went into the at91 and omap platforms, as has
 been the case for a number of releases.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJPuemiAAoJEIwa5zzehBx3L9oQAKiu0bsCiT6BM3VC5VGpluk7
 YVLH/fkYGdSUTeGrpjeaoxxZnN5M1CLwErg3DxWcyYidy0zfmqitC8t2KQxZMxuf
 bt+hn4flpFnXMNm31B9xBCXOOVAvteZHYS35FdSKGyWo5Kz2WKM8ZrrihkAA7jVi
 U75x4+shFPtIhLNg2sJg4e/9D1T14ypElB7W989NzxMtco5fbukVd6vDBHPlFDG3
 RVI2z2MbWUj3HVmdoyB+09ekruys0MQsbPOGo8D4aeJicrli/JBtL1r1w6ZZ6I8v
 Pe0+CbgemMWS69I37Zuxt35Bejpdofa8nKhT1jBrH4uHYxroKkhhx+VMTtuCcFVw
 Q2DhbbHImiW3598c0jkGi7Gk+TalTxkStMQiO3bqYAHApftdqFUgkpFSnOC/Jxgj
 Y6nUmd+GVPS+r0dDwZg4z5/AnUQd6t8Azp784muPDDxgTV1ZfdaC0LlLjdWesvMO
 x+PQib/U7NdxN5lifV6xCXpPoCQsgshrOkVUQiKVHmzaghm9MXgB8qrzXdTz3dLL
 XtR3+1KmSDTfHPSlTq/9vIN4RJtsKUnDWzNViTElEql36KzT7l5mJnBe6CJWirJh
 7JNyH0p6XDZfc2q7LgdiSU0dv/j9LzBaYUukQCyUI3Tk+5zKgAdKbYNJpRcfPuoO
 BK6OKbjCAoAHL+/nDU2s
 =Hcjs
 -----END PGP SIGNATURE-----

Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull first batch of arm-soc cleanups from Olof Johansson:
 "These cleanups are basically all over the place.  The idea is to
  collect changes with minimal impact but large number of changes so we
  can avoid them from distracting in the diffstat in the other series.

  A significant number of lines get removed here, in particular because
  the ixp2000 and ixp23xx platforms get removed.  These have never been
  extremely popular and have fallen into disuse over time with no active
  maintainer taking care of them.  The u5500 soc never made it into a
  product, so we are removing it from the ux500 platform.

  Many good cleanups also went into the at91 and omap platforms, as has
  been the case for a number of releases."

Trivial modify-delete conflicts in arch/arm/mach-{ixp2000,ixp23xx}

* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (152 commits)
  ARM: clps711x: Cleanup IRQ handling
  ARM clps711x: Removed unused header mach/time.h
  ARM: clps711x: Added note about support EP731x CPU to Kconfig
  ARM: clps711x: Added missing register definitions
  ARM: clps711x: Used own subarch directory for store header file
  Dove: Fix Section mismatch warnings
  ARM: orion5x: ts78xx debugging changes
  ARM: orion5x: remove PM dependency from ts78xx
  ARM: orion5x: ts78xx fix NAND resource off by one
  ARM: orion5x: ts78xx whitespace cleanups
  Orion5x: Fix Section mismatch warnings
  Orion5x: Fix warning: struct pci_dev declared inside paramter list
  ARM: clps711x: Combine header files into one for clps711x-targets
  ARM: S3C24XX: Use common macro to define resources on mach-qt2410.c
  ARM: S3C24XX: Use common macro to define resources on mach-osiris.c
  ARM: EXYNOS: Adapt to cpuidle core time keeping and irq enable
  ARM: S5PV210: Use common macro to define resources on mach-smdkv210.c
  ARM: S5PV210: Use common macro to define resources on dev-audio.c
  ARM: S5PC100: Use common macro to define resources on dev-audio.c
  ARM: S5P64X0: Use common macro to define resources on dev-audio.c
  ...
master
Linus Torvalds 11 years ago
commit 9bc747bea5
  1. 2
      Documentation/arm/00-INDEX
  2. 69
      Documentation/arm/IXP2000
  3. 17
      MAINTAINERS
  4. 34
      arch/arm/Kconfig
  5. 2
      arch/arm/Makefile
  6. 7
      arch/arm/boot/compressed/head-xscale.S
  7. 2
      arch/arm/common/Makefile
  8. 507
      arch/arm/common/uengine.c
  9. 196
      arch/arm/configs/at91_dt_defconfig
  10. 1
      arch/arm/configs/at91rm9200_defconfig
  11. 99
      arch/arm/configs/ixp2000_defconfig
  12. 105
      arch/arm/configs/ixp23xx_defconfig
  13. 49
      arch/arm/include/asm/hardware/cs89712.h
  14. 40
      arch/arm/include/asm/hardware/ep7211.h
  15. 83
      arch/arm/include/asm/hardware/ep7212.h
  16. 62
      arch/arm/include/asm/hardware/uengine.h
  17. 186
      arch/arm/mach-at91/Kconfig
  18. 26
      arch/arm/mach-at91/Makefile
  19. 12
      arch/arm/mach-at91/at91rm9200.c
  20. 12
      arch/arm/mach-at91/at91rm9200_devices.c
  21. 12
      arch/arm/mach-at91/at91sam9260.c
  22. 12
      arch/arm/mach-at91/at91sam9260_devices.c
  23. 12
      arch/arm/mach-at91/at91sam9261.c
  24. 12
      arch/arm/mach-at91/at91sam9261_devices.c
  25. 12
      arch/arm/mach-at91/at91sam9263.c
  26. 12
      arch/arm/mach-at91/at91sam9263_devices.c
  27. 12
      arch/arm/mach-at91/at91sam9g45.c
  28. 12
      arch/arm/mach-at91/at91sam9g45_devices.c
  29. 12
      arch/arm/mach-at91/at91sam9rl.c
  30. 12
      arch/arm/mach-at91/at91sam9rl_devices.c
  31. 24
      arch/arm/mach-at91/board-1arm.c
  32. 28
      arch/arm/mach-at91/board-afeb-9260v1.c
  33. 8
      arch/arm/mach-at91/board-cam60.c
  34. 18
      arch/arm/mach-at91/board-carmeva.c
  35. 52
      arch/arm/mach-at91/board-cpu9krea.c
  36. 40
      arch/arm/mach-at91/board-cpuat91.c
  37. 13
      arch/arm/mach-at91/board-csb337.c
  38. 8
      arch/arm/mach-at91/board-csb637.c
  39. 8
      arch/arm/mach-at91/board-dt.c
  40. 24
      arch/arm/mach-at91/board-eb9200.c
  41. 20
      arch/arm/mach-at91/board-ecbat91.c
  42. 13
      arch/arm/mach-at91/board-eco920.c
  43. 8
      arch/arm/mach-at91/board-flexibity.c
  44. 71
      arch/arm/mach-at91/board-foxg20.c
  45. 63
      arch/arm/mach-at91/board-gsia18s.c
  46. 20
      arch/arm/mach-at91/board-kafa.c
  47. 32
      arch/arm/mach-at91/board-kb9202.c
  48. 14
      arch/arm/mach-at91/board-neocore926.c
  49. 21
      arch/arm/mach-at91/board-pcontrol-g20.c
  50. 18
      arch/arm/mach-at91/board-picotux200.c
  51. 31
      arch/arm/mach-at91/board-qil-a9260.c
  52. 24
      arch/arm/mach-at91/board-rm9200dk.c
  53. 24
      arch/arm/mach-at91/board-rm9200ek.c
  54. 36
      arch/arm/mach-at91/board-rsi-ews.c
  55. 30
      arch/arm/mach-at91/board-sam9-l9260.c
  56. 24
      arch/arm/mach-at91/board-sam9260ek.c
  57. 14
      arch/arm/mach-at91/board-sam9261ek.c
  58. 14
      arch/arm/mach-at91/board-sam9263ek.c
  59. 24
      arch/arm/mach-at91/board-sam9g20ek.c
  60. 16
      arch/arm/mach-at91/board-sam9m10g45ek.c
  61. 14
      arch/arm/mach-at91/board-sam9rlek.c
  62. 18
      arch/arm/mach-at91/board-snapper9260.c
  63. 64
      arch/arm/mach-at91/board-stamp9g20.c
  64. 8
      arch/arm/mach-at91/board-usb-a926x.c
  65. 36
      arch/arm/mach-at91/board-yl-9200.c
  66. 8
      arch/arm/mach-at91/cpuidle.c
  67. 11
      arch/arm/mach-at91/generic.h
  68. 5
      arch/arm/mach-at91/include/mach/at91rm9200.h
  69. 7
      arch/arm/mach-at91/include/mach/at91sam9260.h
  70. 4
      arch/arm/mach-at91/include/mach/at91sam9261.h
  71. 4
      arch/arm/mach-at91/include/mach/at91sam9263.h
  72. 5
      arch/arm/mach-at91/include/mach/at91sam9g45.h
  73. 5
      arch/arm/mach-at91/include/mach/at91sam9rl.h
  74. 8
      arch/arm/mach-at91/include/mach/at91sam9x5.h
  75. 1
      arch/arm/mach-at91/include/mach/board.h
  76. 28
      arch/arm/mach-at91/include/mach/cpu.h
  77. 16
      arch/arm/mach-at91/include/mach/hardware.h
  78. 178
      arch/arm/mach-at91/include/mach/uncompress.h
  79. 12
      arch/arm/mach-at91/pm.c
  80. 15
      arch/arm/mach-at91/pm.h
  81. 2
      arch/arm/mach-at91/pm_slowclock.S
  82. 14
      arch/arm/mach-at91/soc.h
  83. 21
      arch/arm/mach-clps711x/Kconfig
  84. 17
      arch/arm/mach-clps711x/common.c
  85. 130
      arch/arm/mach-clps711x/include/mach/clps711x.h
  86. 5
      arch/arm/mach-clps711x/include/mach/debug-macro.S
  87. 3
      arch/arm/mach-clps711x/include/mach/entry-macro.S
  88. 59
      arch/arm/mach-clps711x/include/mach/hardware.h
  89. 5
      arch/arm/mach-clps711x/include/mach/irqs.h
  90. 49
      arch/arm/mach-clps711x/include/mach/time.h
  91. 21
      arch/arm/mach-clps711x/include/mach/uncompress.h
  92. 3
      arch/arm/mach-clps711x/p720t-leds.c
  93. 2
      arch/arm/mach-dove/common.c
  94. 8
      arch/arm/mach-dove/mpp.c
  95. 5
      arch/arm/mach-ep93xx/Kconfig
  96. 110
      arch/arm/mach-ep93xx/core.c
  97. 53
      arch/arm/mach-exynos/cpuidle.c
  98. 12
      arch/arm/mach-exynos/dev-ahci.c
  99. 156
      arch/arm/mach-exynos/dev-audio.c
  100. 16
      arch/arm/mach-exynos/mach-armlex4210.c
  101. Some files were not shown because too many files have changed in this diff Show More

@ -4,8 +4,6 @@ Booting
- requirements for booting
Interrupts
- ARM Interrupt subsystem documentation
IXP2000
- Release Notes for Linux on Intel's IXP2000 Network Processor
msm
- MSM specific documentation
Netwinder

@ -1,69 +0,0 @@
-------------------------------------------------------------------------
Release Notes for Linux on Intel's IXP2000 Network Processor
Maintained by Deepak Saxena <dsaxena@plexity.net>
-------------------------------------------------------------------------
1. Overview
Intel's IXP2000 family of NPUs (IXP2400, IXP2800, IXP2850) is designed
for high-performance network applications such high-availability
telecom systems. In addition to an XScale core, it contains up to 8
"MicroEngines" that run special code, several high-end networking
interfaces (UTOPIA, SPI, etc), a PCI host bridge, one serial port,
flash interface, and some other odds and ends. For more information, see:
http://developer.intel.com
2. Linux Support
Linux currently supports the following features on the IXP2000 NPUs:
- On-chip serial
- PCI
- Flash (MTD/JFFS2)
- I2C through GPIO
- Timers (watchdog, OS)
That is about all we can support under Linux ATM b/c the core networking
components of the chip are accessed via Intel's closed source SDK.
Please contact Intel directly on issues with using those. There is
also a mailing list run by some folks at Princeton University that might
be of help: https://lists.cs.princeton.edu/mailman/listinfo/ixp2xxx
WHATEVER YOU DO, DO NOT POST EMAIL TO THE LINUX-ARM OR LINUX-ARM-KERNEL
MAILING LISTS REGARDING THE INTEL SDK.
3. Supported Platforms
- Intel IXDP2400 Reference Platform
- Intel IXDP2800 Reference Platform
- Intel IXDP2401 Reference Platform
- Intel IXDP2801 Reference Platform
- RadiSys ENP-2611
4. Usage Notes
- The IXP2000 platforms usually have rather complex PCI bus topologies
with large memory space requirements. In addition, b/c of the way the
Intel SDK is designed, devices are enumerated in a very specific
way. B/c of this this, we use "pci=firmware" option in the kernel
command line so that we do not re-enumerate the bus.
- IXDP2x01 systems have variable clock tick rates that we cannot determine
via HW registers. The "ixdp2x01_clk=XXX" cmd line options allow you
to pass the clock rate to the board port.
5. Thanks
The IXP2000 work has been funded by Intel Corp. and MontaVista Software, Inc.
The following people have contributed patches/comments/etc:
Naeem F. Afzal
Lennert Buytenhek
Jeffrey Daly
-------------------------------------------------------------------------
Last Update: 8/09/2004

@ -640,13 +640,6 @@ S: Maintained
F: drivers/amba/
F: include/linux/amba/bus.h
ARM/ADI ROADRUNNER MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-ixp23xx/
F: arch/arm/mach-ixp23xx/include/mach/
ARM/ADS SPHERE MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -862,21 +855,11 @@ M: Dan Williams <dan.j.williams@intel.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXP2000 ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXDP2850 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXP23XX ARM ARCHITECTURE
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/INTEL IXP4XX ARM ARCHITECTURE
M: Imre Kaloz <kaloz@openwrt.org>
M: Krzysztof Halasa <khc@pm.waw.pl>

@ -336,8 +336,8 @@ config ARCH_AT91
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
help
This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 processors.
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
config ARCH_BCMRING
bool "Broadcom BCMRING"
@ -369,12 +369,12 @@ config ARCH_HIGHBANK
Support for the Calxeda Highbank SoC based boards.
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x-based"
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select CPU_ARM720T
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
help
Support for Cirrus Logic 711x/721x based boards.
Support for Cirrus Logic 711x/721x/731x based boards.
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
@ -524,28 +524,6 @@ config ARCH_IOP33X
help
Support for Intel's IOP33X (XScale) family of processors.
config ARCH_IXP23XX
bool "IXP23XX-based"
depends on MMU
select CPU_XSC3
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
Support for Intel's IXP23xx (XScale) family of processors.
config ARCH_IXP2000
bool "IXP2400/2800-based"
depends on MMU
select CPU_XSCALE
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
help
Support for Intel's IXP2400/2800 (XScale) family of processors.
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
@ -1039,10 +1017,6 @@ source "arch/arm/mach-iop13xx/Kconfig"
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-ixp2000/Kconfig"
source "arch/arm/mach-ixp23xx/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"

@ -147,8 +147,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
machine-$(CONFIG_ARCH_IOP13XX) := iop13xx
machine-$(CONFIG_ARCH_IOP32X) := iop32x
machine-$(CONFIG_ARCH_IOP33X) := iop33x
machine-$(CONFIG_ARCH_IXP2000) := ixp2000
machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
machine-$(CONFIG_ARCH_KS8695) := ks8695

@ -32,10 +32,3 @@ __XScale_start:
bic r0, r0, #0x1000 @ clear Icache
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_ARCH_IXP2000
mov r1, #-1
mov r0, #0xd6000000
str r1, [r0, #0x14]
str r1, [r0, #0x18]
#endif

@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_ARCH_IXP2000) += uengine.o
obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o

@ -1,507 +0,0 @@
/*
* Generic library functions for the microengines found on the Intel
* IXP2000 series of network processors.
*
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of the
* License, or (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/hardware/uengine.h>
#if defined(CONFIG_ARCH_IXP2000)
#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
#define IXP_RESET1 IXP2000_RESET1
#else
#if defined(CONFIG_ARCH_IXP23XX)
#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
#define IXP_RESET1 IXP23XX_RESET1
#else
#error unknown platform
#endif
#endif
#define USTORE_ADDRESS 0x000
#define USTORE_DATA_LOWER 0x004
#define USTORE_DATA_UPPER 0x008
#define CTX_ENABLES 0x018
#define CC_ENABLE 0x01c
#define CSR_CTX_POINTER 0x020
#define INDIRECT_CTX_STS 0x040
#define ACTIVE_CTX_STS 0x044
#define INDIRECT_CTX_SIG_EVENTS 0x048
#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
#define NN_PUT 0x080
#define NN_GET 0x084
#define TIMESTAMP_LOW 0x0c0
#define TIMESTAMP_HIGH 0x0c4
#define T_INDEX_BYTE_INDEX 0x0f4
#define LOCAL_CSR_STATUS 0x180
u32 ixp2000_uengine_mask;
static void *ixp2000_uengine_csr_area(int uengine)
{
return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
}
/*
* LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
* space means that the microengine we tried to access was also trying
* to access its own CSR space on the same clock cycle as we did. When
* this happens, we lose the arbitration process by default, and the
* read or write we tried to do was not actually performed, so we try
* again until it succeeds.
*/
u32 ixp2000_uengine_csr_read(int uengine, int offset)
{
void *uebase;
u32 *local_csr_status;
u32 *reg;
u32 value;
uebase = ixp2000_uengine_csr_area(uengine);
local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
reg = (u32 *)(uebase + offset);
do {
value = ixp2000_reg_read(reg);
} while (ixp2000_reg_read(local_csr_status) & 1);
return value;
}
EXPORT_SYMBOL(ixp2000_uengine_csr_read);
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
{
void *uebase;
u32 *local_csr_status;
u32 *reg;
uebase = ixp2000_uengine_csr_area(uengine);
local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
reg = (u32 *)(uebase + offset);
do {
ixp2000_reg_write(reg, value);
} while (ixp2000_reg_read(local_csr_status) & 1);
}
EXPORT_SYMBOL(ixp2000_uengine_csr_write);
void ixp2000_uengine_reset(u32 uengine_mask)
{
u32 value;
value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
uengine_mask &= ixp2000_uengine_mask;
ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
ixp2000_reg_wrb(IXP_RESET1, value);
}
EXPORT_SYMBOL(ixp2000_uengine_reset);
void ixp2000_uengine_set_mode(int uengine, u32 mode)
{
/*
* CTL_STR_PAR_EN: unconditionally enable parity checking on
* control store.
*/
mode |= 0x10000000;
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
/*
* Enable updating of condition codes.
*/
ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
/*
* Initialise other per-microengine registers.
*/
ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
}
EXPORT_SYMBOL(ixp2000_uengine_set_mode);
static int make_even_parity(u32 x)
{
return hweight32(x) & 1;
}
static void ustore_write(int uengine, u64 insn)
{
/*
* Generate even parity for top and bottom 20 bits.
*/
insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
/*
* Write to microstore. The second write auto-increments
* the USTORE_ADDRESS index register.
*/
ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
}
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
{
int i;
/*
* Start writing to microstore at address 0.
*/
ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
for (i = 0; i < insns; i++) {
u64 insn;
insn = (((u64)ucode[0]) << 32) |
(((u64)ucode[1]) << 24) |
(((u64)ucode[2]) << 16) |
(((u64)ucode[3]) << 8) |
((u64)ucode[4]);
ucode += 5;
ustore_write(uengine, insn);
}
/*
* Pad with a few NOPs at the end (to avoid the microengine
* aborting as it prefetches beyond the last instruction), unless
* we run off the end of the instruction store first, at which
* point the address register will wrap back to zero.
*/
for (i = 0; i < 4; i++) {
u32 addr;
addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
if (addr == 0x80000000)
break;
ustore_write(uengine, 0xf0000c0300ULL);
}
/*
* End programming.
*/
ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
}
EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
void ixp2000_uengine_init_context(int uengine, int context, int pc)
{
/*
* Select the right context for indirect access.
*/
ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
/*
* Initialise signal masks to immediately go to Ready state.
*/
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
/*
* Set program counter.
*/
ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
}
EXPORT_SYMBOL(ixp2000_uengine_init_context);
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
{
u32 mask;
/*
* Enable the specified context to go to Executing state.
*/
mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
mask |= ctx_mask << 8;
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
}
EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
{
u32 mask;
/*
* Disable the Ready->Executing transition. Note that this
* does not stop the context until it voluntarily yields.
*/
mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
mask &= ~(ctx_mask << 8);
ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
}
EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
static int check_ixp_type(struct ixp2000_uengine_code *c)
{
u32 product_id;
u32 rev;
product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
if (((product_id >> 16) & 0x1f) != 0)
return 0;
switch ((product_id >> 8) & 0xff) {
#ifdef CONFIG_ARCH_IXP2000
case 0: /* IXP2800 */
if (!(c->cpu_model_bitmask & 4))
return 0;
break;
case 1: /* IXP2850 */
if (!(c->cpu_model_bitmask & 8))
return 0;
break;
case 2: /* IXP2400 */
if (!(c->cpu_model_bitmask & 2))
return 0;
break;
#endif
#ifdef CONFIG_ARCH_IXP23XX
case 4: /* IXP23xx */
if (!(c->cpu_model_bitmask & 0x3f0))
return 0;
break;
#endif
default:
return 0;
}
rev = product_id & 0xff;
if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
return 0;
return 1;
}
static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
{
int offset;
int i;
offset = 0;
for (i = 0; i < 128; i++) {
u8 b3;
u8 b2;
u8 b1;
u8 b0;
b3 = (gpr_a[i] >> 24) & 0xff;
b2 = (gpr_a[i] >> 16) & 0xff;
b1 = (gpr_a[i] >> 8) & 0xff;
b0 = gpr_a[i] & 0xff;
/* immed[@ai, (b1 << 8) | b0] */
/* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
ucode[offset++] = 0xf0;
ucode[offset++] = (b1 >> 4);
ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
ucode[offset++] = (b0 << 2);
ucode[offset++] = 0x80 | i;
/* immed_w1[@ai, (b3 << 8) | b2] */
/* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
ucode[offset++] = 0xf4;
ucode[offset++] = 0x40 | (b3 >> 4);
ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
ucode[offset++] = (b2 << 2);
ucode[offset++] = 0x80 | i;
}
for (i = 0; i < 128; i++) {
u8 b3;
u8 b2;
u8 b1;
u8 b0;
b3 = (gpr_b[i] >> 24) & 0xff;
b2 = (gpr_b[i] >> 16) & 0xff;
b1 = (gpr_b[i] >> 8) & 0xff;
b0 = gpr_b[i] & 0xff;
/* immed[@bi, (b1 << 8) | b0] */
/* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
ucode[offset++] = 0xf0;
ucode[offset++] = (b1 >> 4);
ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
ucode[offset++] = (i << 2) | 0x03;
ucode[offset++] = b0;
/* immed_w1[@bi, (b3 << 8) | b2] */
/* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
ucode[offset++] = 0xf4;
ucode[offset++] = 0x40 | (b3 >> 4);
ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
ucode[offset++] = (i << 2) | 0x03;
ucode[offset++] = b2;
}
/* ctx_arb[kill] */
ucode[offset++] = 0xe0;
ucode[offset++] = 0x00;
ucode[offset++] = 0x01;
ucode[offset++] = 0x00;
ucode[offset++] = 0x00;
}
static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
{
int per_ctx_regs;
u32 *gpr_a;
u32 *gpr_b;
u8 *ucode;
int i;
gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
ucode = kmalloc(513 * 5, GFP_KERNEL);
if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
kfree(ucode);
kfree(gpr_b);
kfree(gpr_a);
return 1;
}
per_ctx_regs = 16;
if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
per_ctx_regs = 32;
for (i = 0; i < 256; i++) {
struct ixp2000_reg_value *r = c->initial_reg_values + i;
u32 *bank;
int inc;
int j;
if (r->reg == -1)
break;
bank = (r->reg & 0x400) ? gpr_b : gpr_a;
inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
j = r->reg & 0x7f;
while (j < 128) {
bank[j] = r->value;
j += inc;
}
}
generate_ucode(ucode, gpr_a, gpr_b);
ixp2000_uengine_load_microcode(uengine, ucode, 513);
ixp2000_uengine_init_context(uengine, 0, 0);
ixp2000_uengine_start_contexts(uengine, 0x01);
for (i = 0; i < 100; i++) {
u32 status;
status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
if (!(status & 0x80000000))
break;
}
ixp2000_uengine_stop_contexts(uengine, 0x01);
kfree(ucode);
kfree(gpr_b);
kfree(gpr_a);
return !!(i == 100);
}
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
{
int ctx;
if (!check_ixp_type(c))
return 1;
if (!(ixp2000_uengine_mask & (1 << uengine)))
return 1;
ixp2000_uengine_reset(1 << uengine);
ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
if (set_initial_registers(uengine, c))
return 1;
ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
for (ctx = 0; ctx < 8; ctx++)
ixp2000_uengine_init_context(uengine, ctx, 0);
return 0;
}
EXPORT_SYMBOL(ixp2000_uengine_load);
static int __init ixp2000_uengine_init(void)
{
int uengine;
u32 value;
/*
* Determine number of microengines present.
*/
switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
#ifdef CONFIG_ARCH_IXP2000
case 0: /* IXP2800 */
case 1: /* IXP2850 */
ixp2000_uengine_mask = 0x00ff00ff;
break;
case 2: /* IXP2400 */
ixp2000_uengine_mask = 0x000f000f;
break;
#endif
#ifdef CONFIG_ARCH_IXP23XX
case 4: /* IXP23xx */
ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
break;
#endif
default:
printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
(unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
ixp2000_uengine_mask = 0x00000000;
break;
}
/*
* Reset microengines.
*/
ixp2000_uengine_reset(ixp2000_uengine_mask);
/*
* Synchronise timestamp counters across all microengines.
*/
value = ixp2000_reg_read(IXP_MISC_CONTROL);
ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
for (uengine = 0; uengine < 32; uengine++) {
if (ixp2000_uengine_mask & (1 << uengine)) {
ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
}
}
ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
return 0;
}
subsys_initcall(ixp2000_uengine_init);

@ -0,0 +1,196 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
CONFIG_IPV6_SIT_6RD=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=4
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ATMEL_PWM=y
CONFIG_ATMEL_TCLIB=y
CONFIG_EEPROM_93CX6=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_DAVICOM_PHY=y
CONFIG_MICREL_PHY=y
# CONFIG_WLAN is not set
CONFIG_INPUT_POLLDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_SERIO is not set
CONFIG_LEGACY_PTY_COUNT=4
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_AT91SAM9X_WATCHDOG=y
CONFIG_SSB=m
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_ATMEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_ATMEL_LCDC=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_ACORN_8x8=y
CONFIG_FONT_MINI_4x6=y
CONFIG_LOGO=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_GADGET=y
CONFIG_USB_AT91=m
CONFIG_USB_ATMEL_USBA=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_USB_G_ACM_MS=m
CONFIG_USB_G_MULTI=m
CONFIG_USB_G_MULTI_CDC=y
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_RTC_DRV_AT91SAM9=y
CONFIG_DMADEVICES=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_FANOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ARC4=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_USER_API_HASH=m
CONFIG_CRYPTO_USER_API_SKCIPHER=m
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_CCITT=m
CONFIG_CRC_ITU_T=m
CONFIG_CRC7=m
CONFIG_AVERAGE=y

@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y
CONFIG_MACH_ONEARM=y
CONFIG_ARCH_AT91RM9200DK=y
CONFIG_MACH_AT91RM9200EK=y

@ -1,99 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_HOTPLUG is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_IXP2000=y
CONFIG_ARCH_ENP2611=y
CONFIG_ARCH_IXDP2400=y
CONFIG_ARCH_IXDP2800=y
CONFIG_ARCH_IXDP2401=y
CONFIG_ARCH_IXDP2801=y
# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0"
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_IXP2000=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_EEPROM_LEGACY=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_PCI=y
CONFIG_CS89x0=y
CONFIG_E100=y
CONFIG_ENP2611_MSF_NET=y
CONFIG_WAN=y
CONFIG_HDLC=y
CONFIG_HDLC_RAW=y
CONFIG_HDLC_CISCO=y
CONFIG_HDLC_FR=y
CONFIG_HDLC_PPP=y
CONFIG_DLCI=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IXP2000=y
CONFIG_WATCHDOG=y
CONFIG_IXP2000_WATCHDOG=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y

@ -1,105 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_IXP23XX=y
CONFIG_MACH_ESPRESSO=y
CONFIG_MACH_IXDP2351=y
CONFIG_MACH_ROADRUNNER=y
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
CONFIG_FPE_NWFPE=y
CONFIG_FPE_NWFPE_XP=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_EEPROM_LEGACY=y
CONFIG_IDE=y
CONFIG_BLK_DEV_SIIMAGE=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_NET_ETHERNET=y
CONFIG_NET_PCI=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_WAN=y
CONFIG_HDLC=y
CONFIG_HDLC_RAW=y
CONFIG_HDLC_CISCO=y
CONFIG_HDLC_FR=y
CONFIG_HDLC_PPP=y
CONFIG_DLCI=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_WATCHDOG=y
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_MON=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_INOTIFY=y
CONFIG_MSDOS_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y

@ -1,49 +0,0 @@
/*
* arch/arm/include/asm/hardware/cs89712.h
*
* This file contains the hardware definitions of the CS89712
* additional internal registers.
*
* Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_CS89712_H
#define __ASM_HARDWARE_CS89712_H
/*
* CS89712 additional registers
*/
#define PCDR 0x0002 /* Port C Data register ---------------------------- */
#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
#define SDCONF_ACTIVE (1 << 10)
#define SDCONF_CLKCTL (1 << 9)
#define SDCONF_WIDTH_4 (0 << 7)
#define SDCONF_WIDTH_8 (1 << 7)
#define SDCONF_WIDTH_16 (2 << 7)
#define SDCONF_WIDTH_32 (3 << 7)
#define SDCONF_SIZE_16 (0 << 5)
#define SDCONF_SIZE_64 (1 << 5)
#define SDCONF_SIZE_128 (2 << 5)
#define SDCONF_SIZE_256 (3 << 5)
#define SDCONF_CASLAT_2 (2)
#define SDCONF_CASLAT_3 (3)
#endif /* __ASM_HARDWARE_CS89712_H */

@ -1,40 +0,0 @@
/*
* arch/arm/include/asm/hardware/ep7211.h
*
* This file contains the hardware definitions of the EP7211 internal
* registers.
*
* Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_EP7211_H
#define __ASM_HARDWARE_EP7211_H
#include <asm/hardware/clps7111.h>
/*
* define EP7211_BASE to be the base address of the region
* you want to access.
*/
#define EP7211_PHYS_BASE (0x80000000)
/*
* XXX miket@bluemug.com: need to introduce EP7211 registers (those not
* present in 7212) here.
*/
#endif /* __ASM_HARDWARE_EP7211_H */

@ -1,83 +0,0 @@
/*
* arch/arm/include/asm/hardware/ep7212.h
*
* This file contains the hardware definitions of the EP7212 internal
* registers.
*
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_HARDWARE_EP7212_H
#define __ASM_HARDWARE_EP7212_H
/*
* define EP7212_BASE to be the base address of the region
* you want to access.
*/
#define EP7212_PHYS_BASE (0x80000000)
#ifndef __ASSEMBLY__
#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
#endif
/*
* These registers are specific to the EP7212 only
*/
#define DAIR 0x2000
#define DAIR0 0x2040
#define DAIDR1 0x2080
#define DAIDR2 0x20c0
#define DAISR 0x2100
#define SYSCON3 0x2200
#define INTSR3 0x2240
#define INTMR3 0x2280
#define LEDFLSH 0x22c0
#define DAIR_DAIEN (1 << 16)
#define DAIR_ECS (1 << 17)
#define DAIR_LCTM (1 << 19)
#define DAIR_LCRM (1 << 20)
#define DAIR_RCTM (1 << 21)
#define DAIR_RCRM (1 << 22)
#define DAIR_LBM (1 << 23)
#define DAIDR2_FIFOEN (1 << 15)
#define DAIDR2_FIFOLEFT (0x0d << 16)
#define DAIDR2_FIFORIGHT (0x11 << 16)
#define DAISR_RCTS (1 << 0)
#define DAISR_RCRS (1 << 1)
#define DAISR_LCTS (1 << 2)
#define DAISR_LCRS (1 << 3)
#define DAISR_RCTU (1 << 4)
#define DAISR_RCRO (1 << 5)
#define DAISR_LCTU (1 << 6)
#define DAISR_LCRO (1 << 7)
#define DAISR_RCNF (1 << 8)
#define DAISR_RCNE (1 << 9)
#define DAISR_LCNF (1 << 10)
#define DAISR_LCNE (1 << 11)
#define DAISR_FIFO (1 << 12)
#define SYSCON3_ADCCON (1 << 0)
#define SYSCON3_DAISEL (1 << 3)
#define SYSCON3_ADCCKNSEN (1 << 4)
#define SYSCON3_FASTWAKE (1 << 8)
#define SYSCON3_DAIEN (1 << 9)
#endif /* __ASM_HARDWARE_EP7212_H */

@ -1,62 +0,0 @@
/*
* Generic library functions for the microengines found on the Intel
* IXP2000 series of network processors.
*
* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
* Dedicated to Marija Kulikova.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as
* published by the Free Software Foundation; either version 2.1 of the
* License, or (at your option) any later version.
*/
#ifndef __IXP2000_UENGINE_H
#define __IXP2000_UENGINE_H
extern u32 ixp2000_uengine_mask;
struct ixp2000_uengine_code
{
u32 cpu_model_bitmask;
u8 cpu_min_revision;
u8 cpu_max_revision;
u32 uengine_parameters;
struct ixp2000_reg_value {
int reg;
u32 value;
} *initial_reg_values;
int num_insns;
u8 *insns;
};
u32 ixp2000_uengine_csr_read(int uengine, int offset);
void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
void ixp2000_uengine_reset(u32 uengine_mask);
void ixp2000_uengine_set_mode(int uengine, u32 mode);
void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
void ixp2000_uengine_init_context(int uengine, int context, int pc);
void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
#define IXP2000_UENGINE_8_CONTEXTS 0x00000000
#define IXP2000_UENGINE_4_CONTEXTS 0x80000000
#define IXP2000_UENGINE_PRN_UPDATE_EVERY 0x40000000
#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS 0x00000000
#define IXP2000_UENGINE_NN_FROM_SELF 0x00100000
#define IXP2000_UENGINE_NN_FROM_PREVIOUS 0x00000000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3 0x000c0000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2 0x00080000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1 0x00040000
#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0 0x00000000
#define IXP2000_UENGINE_LM_ADDR1_GLOBAL 0x00020000
#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT 0x00000000
#define IXP2000_UENGINE_LM_ADDR0_GLOBAL 0x00010000
#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT 0x00000000
#endif

@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0
config HAVE_AT91_DBGU1
bool
config HAVE_AT91_USART3
bool
config HAVE_AT91_USART4
bool
config HAVE_AT91_USART5
bool
config AT91_SAM9_ALT_RESET
bool
default !ARCH_AT91X40