Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (92 commits)
  powerpc: Remove unused 'protect4gb' boot parameter
  powerpc: Build-in e1000e for pseries & ppc64_defconfig
  powerpc/pseries: Make request_ras_irqs() available to other pseries code
  powerpc/numa: Use ibm,architecture-vec-5 to detect form 1 affinity
  powerpc/numa: Set a smaller value for RECLAIM_DISTANCE to enable zone reclaim
  powerpc: Use smt_snooze_delay=-1 to always busy loop
  powerpc: Remove check of ibm,smt-snooze-delay OF property
  powerpc/kdump: Fix race in kdump shutdown
  powerpc/kexec: Fix race in kexec shutdown
  powerpc/kexec: Speedup kexec hash PTE tear down
  powerpc/pseries: Add hcall to read 4 ptes at a time in real mode
  powerpc: Use more accurate limit for first segment memory allocations
  powerpc/kdump: Use chip->shutdown to disable IRQs
  powerpc/kdump: CPUs assume the context of the oopsing CPU
  powerpc/crashdump: Do not fail on NULL pointer dereferencing
  powerpc/eeh: Fix oops when probing in early boot
  powerpc/pci: Check devices status property when scanning OF tree
  powerpc/vio: Switch VIO Bus PM to use generic helpers
  powerpc: Avoid bad relocations in iSeries code
  powerpc: Use common cpu_die (fixes SMP+SUSPEND build)
  ...
master
Linus Torvalds 13 years ago
commit 79c4581262
  1. 18
      Documentation/powerpc/dts-bindings/4xx/reboot.txt
  2. 22
      Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt
  3. 1
      arch/powerpc/Kconfig
  4. 12
      arch/powerpc/Kconfig.debug
  5. 9
      arch/powerpc/boot/Makefile
  6. 155
      arch/powerpc/boot/dts/iss4xx-mpic.dts
  7. 116
      arch/powerpc/boot/dts/iss4xx.dts
  8. 16
      arch/powerpc/boot/dts/mpc8315erdb.dts
  9. 14
      arch/powerpc/boot/dts/mpc8377_rdb.dts
  10. 14
      arch/powerpc/boot/dts/mpc8378_rdb.dts
  11. 14
      arch/powerpc/boot/dts/mpc8379_rdb.dts
  12. 125
      arch/powerpc/boot/dts/p1020rdb.dts
  13. 56
      arch/powerpc/boot/treeboot-iss4xx.c
  14. 9
      arch/powerpc/boot/wrapper
  15. 1026
      arch/powerpc/configs/44x/iss476-smp_defconfig
  16. 2
      arch/powerpc/configs/ppc64_defconfig
  17. 2
      arch/powerpc/configs/pseries_defconfig
  18. 6
      arch/powerpc/include/asm/cache.h
  19. 5
      arch/powerpc/include/asm/cputable.h
  20. 2
      arch/powerpc/include/asm/hvcall.h
  21. 4
      arch/powerpc/include/asm/kexec.h
  22. 51
      arch/powerpc/include/asm/mmu-44x.h
  23. 1
      arch/powerpc/include/asm/mmu.h
  24. 2
      arch/powerpc/include/asm/mmzone.h
  25. 3
      arch/powerpc/include/asm/mpic.h
  26. 1
      arch/powerpc/include/asm/paca.h
  27. 11
      arch/powerpc/include/asm/parport.h
  28. 6
      arch/powerpc/include/asm/pgalloc-64.h
  29. 2
      arch/powerpc/include/asm/pgtable-ppc32.h
  30. 64
      arch/powerpc/include/asm/ptrace.h
  31. 4
      arch/powerpc/include/asm/reg.h
  32. 24
      arch/powerpc/include/asm/reg_booke.h
  33. 18
      arch/powerpc/include/asm/smp.h
  34. 26
      arch/powerpc/include/asm/topology.h
  35. 9
      arch/powerpc/kernel/asm-offsets.c
  36. 29
      arch/powerpc/kernel/cputable.c
  37. 38
      arch/powerpc/kernel/crash.c
  38. 5
      arch/powerpc/kernel/entry_32.S
  39. 13
      arch/powerpc/kernel/exceptions-64s.S
  40. 944
      arch/powerpc/kernel/head_44x.S
  41. 70
      arch/powerpc/kernel/head_8xx.S
  42. 4
      arch/powerpc/kernel/head_booke.h
  43. 13
      arch/powerpc/kernel/head_fsl_booke.S
  44. 12
      arch/powerpc/kernel/iommu.c
  45. 17
      arch/powerpc/kernel/irq.c
  46. 3
      arch/powerpc/kernel/kprobes.c
  47. 12
      arch/powerpc/kernel/lparcfg.c
  48. 48
      arch/powerpc/kernel/machine_kexec_64.c
  49. 9
      arch/powerpc/kernel/misc_32.S
  50. 8
      arch/powerpc/kernel/misc_64.S
  51. 2
      arch/powerpc/kernel/paca.c
  52. 2
      arch/powerpc/kernel/pci_of_scan.c
  53. 3
      arch/powerpc/kernel/process.c
  54. 103
      arch/powerpc/kernel/ptrace.c
  55. 15
      arch/powerpc/kernel/rtas.c
  56. 16
      arch/powerpc/kernel/rtasd.c
  57. 86
      arch/powerpc/kernel/setup-common.c
  58. 23
      arch/powerpc/kernel/setup_64.c
  59. 73
      arch/powerpc/kernel/smp.c
  60. 46
      arch/powerpc/kernel/sysfs.c
  61. 40
      arch/powerpc/kernel/traps.c
  62. 26
      arch/powerpc/kernel/vio.c
  63. 18
      arch/powerpc/lib/string.S
  64. 144
      arch/powerpc/mm/44x_mmu.c
  65. 19
      arch/powerpc/mm/fault.c
  66. 25
      arch/powerpc/mm/fsl_booke_mmu.c
  67. 43
      arch/powerpc/mm/init_64.c
  68. 8
      arch/powerpc/mm/mmu_context_nohash.c
  69. 17
      arch/powerpc/mm/mmu_decl.h
  70. 78
      arch/powerpc/mm/numa.c
  71. 12
      arch/powerpc/mm/pgtable_32.c
  72. 8
      arch/powerpc/mm/pgtable_64.c
  73. 146
      arch/powerpc/mm/tlb_nohash_low.S
  74. 20
      arch/powerpc/platforms/44x/Kconfig
  75. 1
      arch/powerpc/platforms/44x/Makefile
  76. 167
      arch/powerpc/platforms/44x/iss4xx.c
  77. 1
      arch/powerpc/platforms/83xx/mpc831x_rdb.c
  78. 1
      arch/powerpc/platforms/83xx/mpc837x_rdb.c
  79. 3
      arch/powerpc/platforms/86xx/mpc8610_hpcd.c
  80. 5
      arch/powerpc/platforms/Kconfig.cputype
  81. 2
      arch/powerpc/platforms/cell/cbe_cpufreq.c
  82. 4
      arch/powerpc/platforms/iseries/exception.S
  83. 10
      arch/powerpc/platforms/iseries/pci.c
  84. 2
      arch/powerpc/platforms/iseries/smp.c
  85. 2
      arch/powerpc/platforms/pasemi/cpufreq.c
  86. 2
      arch/powerpc/platforms/powermac/cpufreq_64.c
  87. 7
      arch/powerpc/platforms/powermac/low_i2c.c
  88. 2
      arch/powerpc/platforms/powermac/pmac.h
  89. 13
      arch/powerpc/platforms/powermac/setup.c
  90. 9
      arch/powerpc/platforms/powermac/smp.c
  91. 2
      arch/powerpc/platforms/pseries/Makefile
  92. 8
      arch/powerpc/platforms/pseries/dlpar.c
  93. 2
      arch/powerpc/platforms/pseries/eeh.c
  94. 79
      arch/powerpc/platforms/pseries/event_sources.c
  95. 67
      arch/powerpc/platforms/pseries/hotplug-cpu.c
  96. 38
      arch/powerpc/platforms/pseries/hvCall.S
  97. 33
      arch/powerpc/platforms/pseries/lpar.c
  98. 26
      arch/powerpc/platforms/pseries/plpar_wrappers.h
  99. 7
      arch/powerpc/platforms/pseries/pseries.h
  100. 62
      arch/powerpc/platforms/pseries/ras.c
  101. Some files were not shown because too many files have changed in this diff Show More

@ -0,0 +1,18 @@
Reboot property to control system reboot on PPC4xx systems:
By setting "reset_type" to one of the following values, the default
software reset mechanism may be overidden. Here the possible values of
"reset_type":
1 - PPC4xx core reset
2 - PPC4xx chip reset
3 - PPC4xx system reset (default)
Example:
cpu@0 {
device_type = "cpu";
model = "PowerPC,440SPe";
...
reset-type = <2>; /* Use chip-reset */
};

@ -11,7 +11,7 @@ Required properties:
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- interrupts : Interrupt mapping for GPIO IRQ (currently unused).
- interrupts : Interrupt mapping for GPIO IRQ.
- interrupt-parent : Phandle for the interrupt controller that
services interrupts for this device.
- gpio-controller : Marks the port as GPIO controller.
@ -38,3 +38,23 @@ Example of gpio-controller nodes for a MPC8347 SoC:
See booting-without-of.txt for details of how to specify GPIO
information for devices.
To use GPIO pins as interrupt sources for peripherals, specify the
GPIO controller as the interrupt parent and define GPIO number +
trigger mode using the interrupts property, which is defined like
this:
interrupts = <number trigger>, where:
- number: GPIO pin (0..31)
- trigger: trigger mode:
2 = trigger on falling edge
3 = trigger on both edges
Example of device using this is:
funkyfpga@0 {
compatible = "funky-fpga";
...
interrupts = <4 3>;
interrupt-parent = <&gpio1>;
};

@ -140,6 +140,7 @@ config PPC
select HAVE_SYSCALL_WRAPPERS if PPC64
select GENERIC_ATOMIC64 if PPC32
select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API
config EARLY_PRINTK
bool

@ -44,6 +44,18 @@ config DEBUG_STACK_USAGE
This option will slow down process creation somewhat.
config DEBUG_PER_CPU_MAPS
bool "Debug access to per_cpu maps"
depends on DEBUG_KERNEL
depends on SMP
default n
---help---
Say Y to verify that the per_cpu map being accessed has
been setup. Adds a fair amount of code to kernel memory
and decreases performance.
Say N if unsure.
config HCALL_STATS
bool "Hypervisor call instrumentation"
depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS

@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
@ -77,7 +78,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
gamecube-head.S gamecube.c wii-head.S wii.c
gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@ -169,7 +170,7 @@ quiet_cmd_wrap = WRAP $@
$(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) vmlinux
image-$(CONFIG_PPC_PSERIES) += zImage.pseries
image-$(CONFIG_PPC_MAPLE) += zImage.pseries
image-$(CONFIG_PPC_MAPLE) += zImage.maple
image-$(CONFIG_PPC_IBM_CELL_BLADE) += zImage.pseries
image-$(CONFIG_PPC_PS3) += dtbImage.ps3
image-$(CONFIG_PPC_CELLEB) += zImage.pseries
@ -206,6 +207,8 @@ image-$(CONFIG_TAISHAN) += cuImage.taishan
image-$(CONFIG_KATMAI) += cuImage.katmai
image-$(CONFIG_WARP) += cuImage.warp
image-$(CONFIG_YOSEMITE) += cuImage.yosemite
image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
treeImage.iss4xx-mpic
# Board ports in arch/powerpc/platform/8xx/Kconfig
image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
@ -351,7 +354,7 @@ install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y))
clean-files += $(image-) $(initrd-) cuImage.* dtbImage.* treeImage.* \
zImage zImage.initrd zImage.chrp zImage.coff zImage.holly \
zImage.iseries zImage.miboot zImage.pmac zImage.pseries \
simpleImage.* otheros.bld *.dtb
zImage.maple simpleImage.* otheros.bld *.dtb
# clean up files cached by wrapper
clean-kernel := vmlinux.strip vmlinux.bin

@ -0,0 +1,155 @@
/*
* Device Tree Source for IBM Embedded PPC 476 Platform
*
* Copyright 2010 Torez Smith, IBM Corporation.
*
* Based on earlier code:
* Copyright (c) 2006, 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/dts-v1/;
/memreserve/ 0x01f00000 0x00100000;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "ibm,iss-4xx";
compatible = "ibm,iss-4xx";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <0>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "ok";
};
cpu@1 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <1>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0 0x01f00100>;
};
cpu@2 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <2>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0 0x01f00200>;
};
cpu@3 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <3>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
status = "disabled";
enable-method = "spin-table";
cpu-release-addr = <0 0x01f00300>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
};
MPIC: interrupt-controller {
compatible = "chrp,open-pic";
interrupt-controller;
dcr-reg = <0xffc00000 0x00030000>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
plb {
compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; // Filled in by zImage
POB0: opb {
compatible = "ibm,opb-4xx", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
/* Wish there was a nicer way of specifying a full 32-bit
range */
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
0x80000000 0x00000001 0x80000000 0x80000000>;
clock-frequency = <0>; // Filled in by zImage
UART0: serial@40000200 {
device_type = "serial";
compatible = "ns16550a";
reg = <0x40000200 0x00000008>;
virtual-reg = <0xe0000200>;
clock-frequency = <11059200>;
current-speed = <115200>;
interrupt-parent = <&MPIC>;
interrupts = <0x0 0x2>;
};
};
};
nvrtc {
compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
reg = <0 0xEF703000 0x2000>;
};
iss-block {
compatible = "ibm,iss-sim-block-device";
reg = <0 0xEF701000 0x1000>;
};
chosen {
linux,stdout-path = "/plb/opb/serial@40000200";
};
};

@ -0,0 +1,116 @@
/*
* Device Tree Source for IBM Embedded PPC 476 Platform
*
* Copyright 2010 Torez Smith, IBM Corporation.
*
* Based on earlier code:
* Copyright (c) 2006, 2007 IBM Corp.
* Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "ibm,iss-4xx";
compatible = "ibm,iss-4xx";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
serial0 = &UART0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,4xx"; // real CPU changed in sim
reg = <0x00000000>;
clock-frequency = <100000000>; // 100Mhz :-)
timebase-frequency = <100000000>;
i-cache-line-size = <32>; // may need fixup in sim
d-cache-line-size = <32>; // may need fixup in sim
i-cache-size = <32768>; /* may need fixup in sim */
d-cache-size = <32768>; /* may need fixup in sim */
dcr-controller;
dcr-access-method = "native";
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-4xx", "ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0x0c0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-4xx", "ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0x0d0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
plb {
compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; // Filled in by zImage
POB0: opb {
compatible = "ibm,opb-4xx", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
/* Wish there was a nicer way of specifying a full 32-bit
range */
ranges = <0x00000000 0x00000001 0x00000000 0x80000000
0x80000000 0x00000001 0x80000000 0x80000000>;
clock-frequency = <0>; // Filled in by zImage
UART0: serial@40000200 {
device_type = "serial";
compatible = "ns16550a";
reg = <0x40000200 0x00000008>;
virtual-reg = <0xe0000200>;
clock-frequency = <11059200>;
current-speed = <115200>;
interrupt-parent = <&UIC0>;
interrupts = <0x0 0x4>;
};
};
};
nvrtc {
compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
reg = <0 0xEF703000 0x2000>;
};
iss-block {
compatible = "ibm,iss-sim-block-device";
reg = <0 0xEF701000 0x1000>;
};
chosen {
linux,stdout-path = "/plb/opb/serial@40000200";
};
};

@ -292,7 +292,7 @@
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x97c>;
fsl,descriptor-types-mask = <0x3ab0abf>;
fsl,descriptor-types-mask = <0x3a30abf>;
};
sata@18000 {
@ -463,4 +463,18 @@
0 0x00800000>;
};
};
leds {
compatible = "gpio-leds";
pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "ide-disk";
};
};
};

@ -486,4 +486,18 @@
0 0x00800000>;
};
};
leds {
compatible = "gpio-leds";
pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "ide-disk";
};
};
};

@ -470,4 +470,18 @@
0 0x00800000>;
};
};
leds {
compatible = "gpio-leds";
pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "ide-disk";
};
};
};

@ -436,4 +436,18 @@
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
leds {
compatible = "gpio-leds";
pwr {
gpios = <&mcu_pio 0 0>;
default-state = "on";
};
hdd {
gpios = <&mcu_pio 1 0>;
linux,default-trigger = "ide-disk";
};
};
};

@ -19,6 +19,9 @@
aliases {
serial0 = &serial0;
serial1 = &serial1;
ethernet0 = &enet0;
ethernet1 = &enet1;
ethernet2 = &enet2;
pci0 = &pci0;
pci1 = &pci1;
};
@ -346,6 +349,122 @@
};
};
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x1>;
};
};
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000 0x1000>;
interrupts = <29 2 30 2 34 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb4000 0x1000>;
interrupts = <17 2 18 2 24 2>;
};
};
enet1: ethernet@b1000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb1000 0x1000>;
interrupts = <35 2 36 2 40 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb5000 0x1000>;
interrupts = <51 2 52 2 67 2>;
};
};
enet2: ethernet@b2000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
queue-group@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb2000 0x1000>;
interrupts = <31 2 32 2 33 2>;
};
queue-group@1 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb6000 0x1000>;
interrupts = <25 2 26 2 27 2>;
};
};
usb@22000 {
#address-cells = <1>;
#size-cells = <0>;
@ -356,6 +475,11 @@
phy_type = "ulpi";
};
/* USB2 is shared with localbus, so it must be disabled
by default. We can't put 'status = "disabled";' here
since U-Boot doesn't clear the status property when
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
#address-cells = <1>;
#size-cells = <0>;
@ -365,6 +489,7 @@
interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
sdhci@2e000 {
compatible = "fsl,p1020-esdhc", "fsl,esdhc";

@ -0,0 +1,56 @@
/*
* Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
*
* Based on earlier code:
* Copyright (C) Paul Mackerras 1997.
*
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2002-2005 MontaVista Software Inc.
*
* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
* Copyright (c) 2003, 2004 Zultys Technologies
*
* Copyright 2007 David Gibson, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <stdarg.h>
#include <stddef.h>
#include "types.h"
#include "elf.h"
#include "string.h"
#include "stdio.h"
#include "page.h"
#include "ops.h"
#include "reg.h"
#include "io.h"
#include "dcr.h"
#include "4xx.h"
#include "44x.h"
#include "libfdt.h"
BSS_STACK(4096);
static void iss_4xx_fixups(void)
{
ibm4xx_sdram_fixup_memsize();
}
#define SPRN_PIR 0x11E /* Processor Indentification Register */
void platform_init(void)
{
unsigned long end_of_ram = 0x08000000;
unsigned long avail_ram = end_of_ram - (unsigned long)_end;
u32 pir_reg;
simple_alloc_init(_end, avail_ram, 128, 64);
platform_ops.fixups = iss_4xx_fixups;
platform_ops.exit = ibm44x_dbcr_reset;
pir_reg = mfspr(SPRN_PIR);
fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
fdt_init(_dtb_start);
serial_console_init();
}

@ -149,6 +149,10 @@ pseries)
platformo=$object/of.o
link_address='0x4000000'
;;
maple)
platformo=$object/of.o
link_address='0x400000'
;;
pmac|chrp)
platformo=$object/of.o
;;
@ -237,6 +241,9 @@ gamecube|wii)
link_address='0x600000'
platformo="$object/$platform-head.o $object/$platform.o"
;;
treeboot-iss4xx-mpic)
platformo="$object/treeboot-iss4xx.o"
;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
@ -321,7 +328,7 @@ fi
# post-processing needed for some platforms
case "$platform" in
pseries|chrp)
pseries|chrp|maple)
$objbin/addnote "$ofile"
;;
coff)

File diff suppressed because it is too large Load Diff

@ -988,7 +988,7 @@ CONFIG_ACENIC=m
CONFIG_ACENIC_OMIT_TIGON_I=y
# CONFIG_DL2K is not set
CONFIG_E1000=y
CONFIG_E1000E=m
CONFIG_E1000E=y
# CONFIG_IP1000 is not set
# CONFIG_IGB is not set
# CONFIG_NS83820 is not set

@ -804,7 +804,7 @@ CONFIG_ACENIC=m
CONFIG_ACENIC_OMIT_TIGON_I=y
# CONFIG_DL2K is not set
CONFIG_E1000=y
CONFIG_E1000E=m
CONFIG_E1000E=y
# CONFIG_IP1000 is not set
# CONFIG_IGB is not set
# CONFIG_NS83820 is not set

@ -12,8 +12,12 @@
#define L1_CACHE_SHIFT 6
#define MAX_COPY_PREFETCH 4
#elif defined(CONFIG_PPC32)
#define L1_CACHE_SHIFT 5
#define MAX_COPY_PREFETCH 4
#if defined(CONFIG_PPC_47x)
#define L1_CACHE_SHIFT 7
#else
#define L1_CACHE_SHIFT 5
#endif
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT 7
#endif

@ -72,6 +72,7 @@ extern int machine_check_4xx(struct pt_regs *regs);
extern int machine_check_440A(struct pt_regs *regs);
extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs);
/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
struct cpu_spec {
@ -365,6 +366,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
#define CPU_FTRS_47X (CPU_FTRS_440x6)
#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
@ -453,6 +455,9 @@ enum {
#ifdef CONFIG_44x
CPU_FTRS_44X | CPU_FTRS_440x6 |
#endif
#ifdef CONFIG_PPC_47x
CPU_FTRS_47X |
#endif
#ifdef CONFIG_E200
CPU_FTRS_E200 |
#endif

@ -228,6 +228,7 @@
#define H_JOIN 0x298
#define H_VASI_STATE 0x2A4
#define H_ENABLE_CRQ 0x2B0
#define H_GET_EM_PARMS 0x2B8
#define H_SET_MPP 0x2D0
#define H_GET_MPP 0x2D4
#define MAX_HCALL_OPCODE H_GET_MPP
@ -281,6 +282,7 @@ long plpar_hcall_raw(unsigned long opcode, unsigned long *retbuf, ...);
*/
#define PLPAR_HCALL9_BUFSIZE 9
long plpar_hcall9(unsigned long opcode, unsigned long *retbuf, ...);
long plpar_hcall9_raw(unsigned long opcode, unsigned long *retbuf, ...);
/* For hcall instrumentation. One structure per-hcall, per-CPU */
struct hcall_stats {

@ -31,6 +31,10 @@
#define KEXEC_ARCH KEXEC_ARCH_PPC
#endif
#define KEXEC_STATE_NONE 0
#define KEXEC_STATE_IRQS_OFF 1
#define KEXEC_STATE_REAL_MODE 2
#ifndef __ASSEMBLY__
#include <linux/cpumask.h>
#include <asm/reg.h>

@ -40,7 +40,7 @@
#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
#define PPC44x_TLB_E 0x00000080 /* Memory is little endian */
#define PPC44x_TLB_PERM_MASK 0x0000003f
#define PPC44x_TLB_UX 0x00000020 /* User execution */
@ -53,6 +53,52 @@
/* Number of TLB entries */
#define PPC44x_TLB_SIZE 64
/* 47x bits */
#define PPC47x_MMUCR_TID 0x0000ffff
#define PPC47x_MMUCR_STS 0x00010000
/* Page identification fields */
#define PPC47x_TLB0_EPN_MASK 0xfffff000 /* Effective Page Number */
#define PPC47x_TLB0_VALID 0x00000800 /* Valid flag */
#define PPC47x_TLB0_TS 0x00000400 /* Translation address space */
#define PPC47x_TLB0_4K 0x00000000
#define PPC47x_TLB0_16K 0x00000010
#define PPC47x_TLB0_64K 0x00000030
#define PPC47x_TLB0_1M 0x00000070
#define PPC47x_TLB0_16M 0x000000f0
#define PPC47x_TLB0_256M 0x000001f0
#define PPC47x_TLB0_1G 0x000003f0
#define PPC47x_TLB0_BOLTED_R 0x00000008 /* tlbre only */
/* Translation fields */
#define PPC47x_TLB1_RPN_MASK 0xfffff000 /* Real Page Number */
#define PPC47x_TLB1_ERPN_MASK 0x000003ff
/* Storage attribute and access control fields */
#define PPC47x_TLB2_ATTR_MASK 0x0003ff80
#define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */
#define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */
#define PPC47x_TLB2_U0 0x00008000 /* User 0 */
#define PPC47x_TLB2_U1 0x00004000 /* User 1 */
#define PPC47x_TLB2_U2 0x00002000 /* User 2 */
#define PPC47x_TLB2_U3 0x00001000 /* User 3 */
#define PPC47x_TLB2_W 0x00000800 /* Caching is write-through */
#define PPC47x_TLB2_I 0x00000400 /* Caching is inhibited */
#define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */
#define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */
#define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */
#define PPC47x_TLB2_PERM_MASK 0x0000003f
#define PPC47x_TLB2_UX 0x00000020 /* User execution */
#define PPC47x_TLB2_UW 0x00000010 /* User write */
#define PPC47x_TLB2_UR 0x00000008 /* User read */
#define PPC47x_TLB2_SX 0x00000004 /* Super execution */
#define PPC47x_TLB2_SW 0x00000002 /* Super write */
#define PPC47x_TLB2_SR 0x00000001 /* Super read */
#define PPC47x_TLB2_U_RWX (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
#define PPC47x_TLB2_S_RWX (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
#define PPC47x_TLB2_S_RW (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
#define PPC47x_TLB2_IMG (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
#ifndef __ASSEMBLY__
extern unsigned int tlb_44x_hwater;
@ -79,12 +125,15 @@ typedef struct {
#if (PAGE_SHIFT == 12)
#define PPC44x_TLBE_SIZE PPC44x_TLB_4K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_4K
#define mmu_virtual_psize MMU_PAGE_4K
#elif (PAGE_SHIFT == 14)
#define PPC44x_TLBE_SIZE PPC44x_TLB_16K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_16K
#define mmu_virtual_psize MMU_PAGE_16K
#elif (PAGE_SHIFT == 16)
#define PPC44x_TLBE_SIZE PPC44x_TLB_64K
#define PPC47x_TLBE_SIZE PPC47x_TLB0_64K
#define mmu_virtual_psize MMU_PAGE_64K
#elif (PAGE_SHIFT == 18)
#define PPC44x_TLBE_SIZE PPC44x_TLB_256K

@ -18,6 +18,7 @@
#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
#define MMU_FTR_TYPE_47x ASM_CONST(0x00000040)
/*
* This is individual features

@ -30,7 +30,7 @@ extern struct pglist_data *node_data[];
*/
extern int numa_cpu_lookup_table[];
extern cpumask_t numa_cpumask_lookup_table[];
extern cpumask_var_t node_to_cpumask_map[];
#ifdef CONFIG_MEMORY_HOTPLUG
extern unsigned long max_pfn;
#endif

@ -463,9 +463,6 @@ extern void mpic_cpu_set_priority(int prio);
/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);
/* Send an IPI (non offseted number 0..3) */
extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
/* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg);

@ -82,6 +82,7 @@ struct paca_struct {
s16 hw_cpu_id; /* Physical processor number */
u8 cpu_start; /* At startup, processor spins until */
/* this becomes non-zero. */
u8 kexec_state; /* set when kexec down has irqs off */
#ifdef CONFIG_PPC_STD_MMU_64
struct slb_shadow *slb_shadow_ptr;

@ -19,6 +19,8 @@ static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
u32 io1, io2;
int propsize;
int count = 0;
int virq;
for (np = NULL; (np = of_find_compatible_node(np,
"parallel",
"pnpPNP,400")) != NULL;) {
@ -26,10 +28,13 @@ static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
if (!prop || propsize > 6*sizeof(u32))
continue;
io1 = prop[1]; io2 = prop[2];
prop = of_get_property(np, "interrupts", NULL);
if (!prop)
virq = irq_of_parse_and_map(np, 0);
if (virq == NO_IRQ)
continue;
if (parport_pc_probe_port(io1, io2, prop[0], autodma, NULL, 0) != NULL)
if (parport_pc_probe_port(io1, io2, virq, autodma, NULL, 0)
!= NULL)
count++;
}
return count;

@ -11,6 +11,12 @@
#include <linux/cpumask.h>
#include <linux/percpu.h>
struct vmemmap_backing {
struct vmemmap_backing *list;
unsigned long phys;
unsigned long virt_addr;
};
/*
* Functions that deal with pagetables that could be at any level of
* the table need to be passed an "index_size" so they know how to

@ -287,7 +287,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
#define pmd_page_vaddr(pmd) \
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
(mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
#else
#define pmd_page_vaddr(pmd) \
((unsigned long) (pmd_val(pmd) & PAGE_MASK))

@ -89,6 +89,7 @@ struct pt_regs {
#define instruction_pointer(regs) ((regs)->nip)
#define user_stack_pointer(regs) ((regs)->gpr[1])
#define kernel_stack_pointer(regs) ((regs)->gpr[1])
#define regs_return_value(regs) ((regs)->gpr[3])
#ifdef CONFIG_SMP
@ -141,6 +142,69 @@ do { \
#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601))
#define ARCH_HAS_USER_SINGLE_STEP_INFO
/*
* kprobe-based event tracer support
*/
#include <linux/stddef.h>
#include <linux/thread_info.h>
extern int regs_query_register_offset(const char *name);
extern const char *regs_query_register_name(unsigned int offset);
#define MAX_REG_OFFSET (offsetof(struct pt_regs, dsisr))
/**
* regs_get_register() - get register value from its offset
* @regs: pt_regs from which register value is gotten
* @offset: offset number of the register.
*
* regs_get_register returns the value of a register whose offset from @regs.
* The @offset is the offset of the register in struct pt_regs.
* If @offset is bigger than MAX_REG_OFFSET, this returns 0.
*/
static inline unsigned long regs_get_register(struct pt_regs *regs,
unsigned int offset)
{
if (unlikely(offset > MAX_REG_OFFSET))
return 0;
return *(unsigned long *)((unsigned long)regs + offset);
}
/**
* regs_within_kernel_stack() - check the address in the stack
* @regs: pt_regs which contains kernel stack pointer.
* @addr: address which is checked.
*
* regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
* If @addr is within the kernel stack, it returns true. If not, returns false.
*/
static inline bool regs_within_kernel_stack(struct pt_regs *regs,
unsigned long addr)
{
return ((addr & ~(THREAD_SIZE - 1)) ==
(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
}
/**
* regs_get_kernel_stack_nth() - get Nth entry of the stack
* @regs: pt_regs which contains kernel stack pointer.
* @n: stack entry number.
*
* regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
* is specified by @regs. If the @n th entry is NOT in the kernel stack,
* this returns 0.
*/
static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
unsigned int n)
{
unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
addr += n;
if (regs_within_kernel_stack(regs, (unsigned long)addr))
return *addr;
else
return 0;
}
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */

@ -817,6 +817,7 @@
#define PVR_403GC 0x00200200
#define PVR_403GCX 0x00201400
#define PVR_405GP 0x40110000
#define PVR_476 0x11a52000
#define PVR_STB03XXX 0x40310000
#define PVR_NP405H 0x41410000
#define PVR_NP405L 0x41610000
@ -853,6 +854,9 @@
#define PVR_8245 0x80811014
#define PVR_8260 PVR_8240
/* 476 Simulator seems to currently have the PVR of the 602... */
#define PVR_476_ISS 0x00052000
/* 64-bit processors */
/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
#define PV_NORTHSTAR 0x0033

@ -191,6 +191,10 @@
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */
#define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
#define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
#ifdef CONFIG_E500
#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
@ -604,5 +608,25 @@
#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
#endif /* 403GCX */
/* Some 476 specific registers */
#define SPRN_SSPCR 830
#define SPRN_USPCR 831
#define SPRN_ISPCR 829
#define SPRN_MMUBE0 820
#define MMUBE0_IBE0_SHIFT 24
#define MMUBE0_IBE1_SHIFT 16
#define MMUBE0_IBE2_SHIFT 8
#define MMUBE0_VBE0 0x00000004
#define MMUBE0_VBE1 0x00000002
#define MMUBE0_VBE2 0x00000001
#define SPRN_MMUBE1 821
#define MMUBE1_IBE3_SHIFT 24
#define MMUBE1_IBE4_SHIFT 16
#define MMUBE1_IBE5_SHIFT 8
#define MMUBE1_VBE3 0x00000004
#define MMUBE1_VBE4 0x00000002
#define MMUBE1_VBE5 0x00000001
#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
#endif /* __KERNEL__ */

@ -40,7 +40,7 @@ extern void smp_message_recv(int);
DECLARE_PER_CPU(unsigned int, cpu_pvr);
#ifdef CONFIG_HOTPLUG_CPU
extern void fixup_irqs(cpumask_t map);
extern void fixup_irqs(const struct cpumask *map);
int generic_cpu_disable(void);
int generic_cpu_enable(unsigned int cpu);
void generic_cpu_die(unsigned int cpu);
@ -68,8 +68,19 @@ static inline void set_hard_smp_processor_id(int cpu, int phys)
}
#endif
DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
DECLARE_PER_CPU(cpumask_t, cpu_core_map);
DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
static inline struct cpumask *cpu_sibling_mask(int cpu)
{
return per_cpu(cpu_sibling_map, cpu);
}
static inline struct cpumask *cpu_core_mask(int cpu)
{
return per_cpu(cpu_core_map, cpu);
}
extern int cpu_to_core_id(int cpu);
/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
@ -93,7 +104,6 @@ void smp_init_pSeries(void);
void smp_init_cell(void);
void smp_init_celleb(void);
void smp_setup_cpu_maps(void);
void smp_setup_cpu_sibling_map(void);
extern int __cpu_disable(void);
extern void __cpu_die(unsigned int cpu);

@ -8,6 +8,26 @@ struct device_node;
#ifdef CONFIG_NUMA
/*
* Before going off node we want the VM to try and reclaim from the local
* node. It does this if the remote distance is larger than RECLAIM_DISTANCE.
* With the default REMOTE_DISTANCE of 20 and the default RECLAIM_DISTANCE of
* 20, we never reclaim and go off node straight away.
*
* To fix this we choose a smaller value of RECLAIM_DISTANCE.
*/
#define RECLAIM_DISTANCE 10
/*
* Before going off node we want the VM to try and reclaim from the local
* node. It does this if the remote distance is larger than RECLAIM_DISTANCE.
* With the default REMOTE_DISTANCE of 20 and the default RECLAIM_DISTANCE of
* 20, we never reclaim and go off node straight away.
*
* To fix this we choose a smaller value of RECLAIM_DISTANCE.
*/
#define RECLAIM_DISTANCE 10
#include <asm/mmzone.h>
static inline int cpu_to_node(int cpu)
@ -19,7 +39,7 @@ static inline int cpu_to_node(int cpu)
#define cpumask_of_node(node) ((node) == -1 ? \
cpu_all_mask : \
&numa_cpumask_lookup_table[node])
node_to_cpumask_map[node])
int of_node_to_nid(struct device_node *device);
@ -102,8 +122,8 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
#ifdef CONFIG_PPC64
#include <asm/smp.h>
#define topology_thread_cpumask(cpu) (&per_cpu(cpu_sibling_map, cpu))
#define topology_core_cpumask(cpu) (&per_cpu(cpu_core_map, cpu))
#define topology_thread_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))
#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
#define topology_core_id(cpu) (cpu_to_core_id(cpu))
#endif
#endif

@ -183,6 +183,7 @@ int main(void)
#endif /* CONFIG_PPC_STD_MMU_64 */
DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
DEFINE(PACA_STARTPURR, offsetof(struct paca_struct, startpurr));
DEFINE(PACA_STARTSPURR, offsetof(struct paca_struct, startspurr));
DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
@ -447,6 +448,14 @@ int main(void)
DEFINE(PGD_T_LOG2, PGD_T_LOG2);
DEFINE(PTE_T_LOG2, PTE_T_LOG2);
#endif
#ifdef CONFIG_FSL_BOOKE
DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
#endif
#ifdef CONFIG_KVM_EXIT_TIMING
DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,

@ -1701,6 +1701,35 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = "ppc440",
},
{ /* 476 core */
.pvr_mask = 0xffff0000,
.pvr_value = 0x11a50000,
.cpu_name = "476",
.cpu_features = CPU_FTRS_47X,
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_FPU,
.mmu_features = MMU_FTR_TYPE_47x |
MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
.icache_bsize = 32,
.dcache_bsize = 128,
.machine_check = machine_check_47x,
.platform = "ppc470",
},
{ /* 476 iss */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00050000,
.cpu_name = "476",
.cpu_features = CPU_FTRS_47X,
.cpu_user_features = COMMON_USER_BOOKE |
PPC_FEATURE_HAS_FPU,
.cpu_user_features = COMMON_USER_BOOKE,