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ARM: SoC late changes for v3.12

These are changes that arrived a little late before the merge window,
 or had dependencies on previous branches.
 
 Highlights:
 - ux500: misc. cleanup, fixup I2C devices
 - exynos: DT updates for RTC; PM updates
 - at91: DT updates for NAND; new platforms added to generic defconfig
 - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
 - highbank: LPAE fixes, select necessary ARM errata
 - omap: PM fixes and improvements; OMAP5 mailbox support
 - omap: basic support for new DRA7xx SoCs
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Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC late changes from Kevin Hilman:
 "These are changes that arrived a little late before the merge window,
  or had dependencies on previous branches.

  Highlights:
   - ux500: misc.  cleanup, fixup I2C devices
   - exynos: DT updates for RTC; PM updates
   - at91: DT updates for NAND; new platforms added to generic defconfig
   - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
   - highbank: LPAE fixes, select necessary ARM errata
   - omap: PM fixes and improvements; OMAP5 mailbox support
   - omap: basic support for new DRA7xx SoCs"

* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
  ARM: dts: vexpress: Add CCI node to TC2 device-tree
  ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
  ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
  ARM: highbank: clean-up some unused includes
  ARM: sun7i: Enable the A20 clocks in the DTSI
  ARM: sun6i: Enable clock support in the DTSI
  ARM: sun5i: dt: Use the A10s gates in the DTSI
  ARM: at91: at91_dt_defconfig: enable rm9200 support
  ARM: dts: add ADC device tree node for exynos5420/5250
  ARM: dts: Add RTC DT node to Exynos5420 SoC
  ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
  ARM: dts: Fix the RTC DT node name for Exynos5250
  irqchip: mmp: avoid to include irqs head file
  ARM: mmp: avoid to include head file in mach-mmp
  irqchip: mmp: support irqchip
  irqchip: move mmp irq driver
  ARM: OMAP: AM33xx: clock: Add RNG clock data
  ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
  ARM: OMAP4: clock: Lock PLLs in the right sequence
  ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
  ...
master
Linus Torvalds 8 years ago
parent
commit
6404141718
  1. 1
      arch/arm/Kconfig
  2. 1
      arch/arm/boot/dts/Makefile
  3. 2
      arch/arm/boot/dts/exynos5.dtsi
  4. 4
      arch/arm/boot/dts/exynos5250-arndale.dts
  5. 4
      arch/arm/boot/dts/exynos5250-snow.dts
  6. 14
      arch/arm/boot/dts/exynos5250.dtsi
  7. 17
      arch/arm/boot/dts/exynos5420.dtsi
  8. 19
      arch/arm/boot/dts/sama5d3.dtsi
  9. 2
      arch/arm/boot/dts/sama5d3xcm.dtsi
  10. 36
      arch/arm/boot/dts/sun5i-a10s.dtsi
  11. 2
      arch/arm/boot/dts/sun6i-a31-colombus.dts
  12. 161
      arch/arm/boot/dts/sun6i-a31.dtsi
  13. 53
      arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
  14. 27
      arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
  15. 157
      arch/arm/boot/dts/sun7i-a20.dtsi
  16. 25
      arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
  17. 4
      arch/arm/configs/at91_dt_defconfig
  18. 2
      arch/arm/include/asm/mach/arch.h
  19. 4
      arch/arm/include/asm/outercache.h
  20. 1
      arch/arm/mach-at91/include/mach/hardware.h
  21. 8
      arch/arm/mach-at91/include/mach/sama5d3.h
  22. 13
      arch/arm/mach-at91/include/mach/uncompress.h
  23. 7
      arch/arm/mach-exynos/Kconfig
  24. 3
      arch/arm/mach-exynos/cpuidle.c
  25. 6
      arch/arm/mach-highbank/Kconfig
  26. 20
      arch/arm/mach-highbank/highbank.c
  27. 2
      arch/arm/mach-mmp/Makefile
  28. 1
      arch/arm/mach-mmp/common.h
  29. 26
      arch/arm/mach-mmp/include/mach/entry-macro.S
  30. 1
      arch/arm/mach-mmp/include/mach/pxa168.h
  31. 1
      arch/arm/mach-mmp/include/mach/pxa910.h
  32. 8
      arch/arm/mach-mmp/mmp-dt.c
  33. 8
      arch/arm/mach-mmp/mmp2-dt.c
  34. 6
      arch/arm/mach-mmp/mmp2.c
  35. 7
      arch/arm/mach-mmp/pxa910.c
  36. 4
      arch/arm/mach-omap2/Makefile
  37. 1
      arch/arm/mach-omap2/board-generic.c
  38. 5
      arch/arm/mach-omap2/cclock33xx_data.c
  39. 20
      arch/arm/mach-omap2/cclock44xx_data.c
  40. 1
      arch/arm/mach-omap2/clockdomain.h
  41. 740
      arch/arm/mach-omap2/clockdomains7xx_data.c
  42. 51
      arch/arm/mach-omap2/cm-regbits-7xx.h
  43. 324
      arch/arm/mach-omap2/cm1_7xx.h
  44. 513
      arch/arm/mach-omap2/cm2_7xx.h
  45. 5
      arch/arm/mach-omap2/io.c
  46. 4
      arch/arm/mach-omap2/omap_hwmod.c
  47. 1
      arch/arm/mach-omap2/omap_hwmod.h
  48. 69
      arch/arm/mach-omap2/omap_hwmod_33xx_data.c
  49. 42
      arch/arm/mach-omap2/omap_hwmod_54xx_data.c
  50. 2724
      arch/arm/mach-omap2/omap_hwmod_7xx_data.c
  51. 1
      arch/arm/mach-omap2/powerdomain.h
  52. 8
      arch/arm/mach-omap2/powerdomains3xxx_data.c
  53. 454
      arch/arm/mach-omap2/powerdomains7xx_data.c
  54. 1
      arch/arm/mach-omap2/prcm-common.h
  55. 5
      arch/arm/mach-omap2/prcm44xx.h
  56. 78
      arch/arm/mach-omap2/prcm_mpu7xx.h
  57. 12
      arch/arm/mach-omap2/prm44xx.c
  58. 678
      arch/arm/mach-omap2/prm7xx.h
  59. 20
      arch/arm/mach-omap2/prminst44xx.c
  60. 1
      arch/arm/mach-ux500/board-mop500-audio.c
  61. 1
      arch/arm/mach-ux500/board-mop500-pins.c
  62. 33
      arch/arm/mach-ux500/board-mop500.c
  63. 3
      arch/arm/mach-ux500/cpu-db8500.c
  64. 746
      arch/arm/mach-ux500/pins-db8500.h
  65. 2
      arch/arm/mm/init.c
  66. 23
      drivers/dma/amba-pl08x.c
  67. 1
      drivers/irqchip/Makefile
  68. 338
      drivers/irqchip/irq-mmp.c
  69. 6
      include/linux/irqchip/mmp.h

1
arch/arm/Kconfig

@ -557,6 +557,7 @@ config ARCH_MMP
select GENERIC_CLOCKEVENTS
select GPIO_PXA
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
select NEED_MACH_GPIO_H
select PINCTRL
select PLAT_PXA

1
arch/arm/boot/dts/Makefile

@ -231,6 +231,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a13-olinuxino.dtb \
sun6i-a31-colombus.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-olinuxino-micro.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \

2
arch/arm/boot/dts/exynos5.dtsi

@ -95,7 +95,7 @@
interrupts = <0 54 0>;
};
rtc {
rtc@101E0000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;

4
arch/arm/boot/dts/exynos5250-arndale.dts

@ -538,10 +538,6 @@
};
};
rtc {
status = "okay";
};
usb_hub_bus {
compatible = "simple-bus";
#address-cells = <1>;

4
arch/arm/boot/dts/exynos5250-snow.dts

@ -171,10 +171,6 @@
};
};
rtc {
status = "okay";
};
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.

14
arch/arm/boot/dts/exynos5250.dtsi

@ -180,9 +180,10 @@
clock-names = "mfc";
};
rtc {
rtc@101E0000 {
clocks = <&clock 337>;
clock-names = "rtc";
status = "okay";
};
tmu@10060000 {
@ -638,4 +639,15 @@
clocks = <&clock 133>, <&clock 339>;
clock-names = "sclk_fimd", "fimd";
};
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v1";
reg = <0x12D10000 0x100>, <0x10040718 0x4>;
interrupts = <0 106 0>;
clocks = <&clock 303>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
};

17
arch/arm/boot/dts/exynos5420.dtsi

@ -180,6 +180,12 @@
interrupts = <0 47 0>;
};
rtc@101E0000 {
clocks = <&clock 317>;
clock-names = "rtc";
status = "okay";
};
serial@12C00000 {
clocks = <&clock 257>, <&clock 128>;
clock-names = "uart", "clk_uart_baud0";
@ -218,4 +224,15 @@
clocks = <&clock 147>, <&clock 421>;
clock-names = "sclk_fimd", "fimd";
};
adc: adc@12D10000 {
compatible = "samsung,exynos-adc-v2";
reg = <0x12D10000 0x100>, <0x10040720 0x4>;
interrupts = <0 106 0>;
clocks = <&clock 270>;
clock-names = "adc";
#io-channel-cells = <1>;
io-channel-ranges;
status = "disabled";
};
};

19
arch/arm/boot/dts/sama5d3.dtsi

@ -1034,21 +1034,30 @@
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = < 0x60000000 0x01000000 /* EBI CS3 */
0xffffc070 0x00000490 /* SMC PMECC regs */
0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
0x00100000 0x00100000 /* ROM code */
0x70000000 0x10000000 /* NFC Command Registers */
0xffffc000 0x00000070 /* NFC HSMC regs */
0x00200000 0x00100000 /* NFC SRAM banks */
0x00110000 0x00018000 /* ROM code */
>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand0_ale_cle>;
atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
status = "disabled";
nfc@70000000 {
compatible = "atmel,sama5d3-nfc";
#address-cells = <1>;
#size-cells = <1>;
reg = <
0x70000000 0x10000000 /* NFC Command Registers */
0xffffc000 0x00000070 /* NFC HSMC regs */
0x00200000 0x00100000 /* NFC SRAM banks */
>;
};
};
};
};

2
arch/arm/boot/dts/sama5d3xcm.dtsi

@ -47,8 +47,6 @@
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
atmel,has-nfc;
atmel,use-nfc-sram;
nand-on-flash-bbt;
status = "okay";

36
arch/arm/boot/dts/sun5i-a10s.dtsi

@ -95,20 +95,16 @@
ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-ahb-gates-clk";
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
"ahb_de_fe1", "ahb_mp", "ahb_mali400";
clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
"ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
"ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
"ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
};
apb0: apb0@01c20054 {
@ -120,12 +116,11 @@
apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb0-gates-clk";
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
"apb0_ir1", "apb0_keypad";
clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
"apb0_ir", "apb0_keypad";
};
/* dummy is pll62 */
@ -145,15 +140,12 @@
apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun4i-apb1-gates-clk";
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_can", "apb1_scr",
"apb1_ps20", "apb1_ps21", "apb1_uart0",
"apb1_uart1", "apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5", "apb1_uart6",
"apb1_uart7";
"apb1_i2c2", "apb1_uart0", "apb1_uart1",
"apb1_uart2", "apb1_uart3";
};
};

2
arch/arm/boot/dts/sun6i-a31-colombus.dts

@ -24,6 +24,8 @@
soc@01c00000 {
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};

161
arch/arm/boot/dts/sun6i-a31.dtsi

@ -51,13 +51,137 @@
clocks {
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges;
osc: oscillator {
osc24M: osc24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
osc32k: osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
pll6: pll6 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cpu: cpu@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20050 0x4>;
/*
* PLL1 is listed twice here.
* While it looks suspicious, it's actually documented
* that way both in the datasheet and in the code from
* Allwinner.
*/
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
};
axi: axi@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
reg = <0x01c20050 0x4>;
clocks = <&cpu>;
};
ahb1_mux: ahb1_mux@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
};
ahb1: ahb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1_mux>;
};
ahb1_gates: ahb1_gates@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
"ahb1_nand0", "ahb1_sdram",
"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
"ahb1_ehci1", "ahb1_ohci0",
"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
"ahb1_drc0", "ahb1_drc1";
};
apb1: apb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb1>;
};
apb1_gates: apb1_gates@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
};
apb2_mux: apb2_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
};
apb2: apb2@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun6i-a31-apb2-div-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb2_mux>;
};
apb2_gates: apb2_gates@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x8>;
clocks = <&apb2>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
"apb2_uart1", "apb2_uart2", "apb2_uart3",
"apb2_uart4", "apb2_uart5";
};
};
soc@01c00000 {
@ -66,6 +190,25 @@
#size-cells = <1>;
ranges;
pio: pinctrl@01c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
clocks = <&apb1_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PH20", "PH21";
allwinner,function = "uart0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
timer@01c20c00 {
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0xa0>;
@ -74,7 +217,7 @@
<0 20 1>,
<0 21 1>,
<0 22 1>;
clocks = <&osc>;
clocks = <&osc24M>;
};
wdt1: watchdog@01c20ca0 {
@ -88,7 +231,7 @@
interrupts = <0 0 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 16>;
status = "disabled";
};
@ -98,7 +241,7 @@
interrupts = <0 1 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 17>;
status = "disabled";
};
@ -108,7 +251,7 @@
interrupts = <0 2 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 18>;
status = "disabled";
};
@ -118,7 +261,7 @@
interrupts = <0 3 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 19>;
status = "disabled";
};
@ -128,7 +271,7 @@
interrupts = <0 4 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 20>;
status = "disabled";
};
@ -138,7 +281,7 @@
interrupts = <0 5 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc>;
clocks = <&apb2_gates 21>;
status = "disabled";
};

53
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts

@ -0,0 +1,53 @@
/*
* Copyright 2013 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun7i-a20.dtsi"
/ {
model = "Cubietech Cubieboard2";
compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
soc@01c00000 {
pinctrl@01c20800 {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = "PH20", "PH21";
allwinner,function = "gpio_out";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_cubieboard2>;
blue {
label = "cubieboard2:blue:usr";
gpios = <&pio 7 21 0>;
};
green {
label = "cubieboard2:green:usr";
gpios = <&pio 7 20 0>;
};
};
};

27
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts

@ -19,16 +19,43 @@
compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
soc@01c00000 {
pinctrl@01c20800 {
led_pins_olinuxino: led_pins@0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
allwinner,drive = <1>;
allwinner,pull = <0>;
};
};
uart0: serial@01c28000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
uart6: serial@01c29800 {
pinctrl-names = "default";
pinctrl-0 = <&uart6_pins_a>;
status = "okay";
};
uart7: serial@01c29c00 {
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
green {
label = "a20-olinuxino-micro:green:usr";
gpios = <&pio 7 2 0>;
default-state = "on";
};
};
};

157
arch/arm/boot/dts/sun7i-a20.dtsi

@ -44,7 +44,8 @@
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "fixed-clock";
compatible = "allwinner,sun4i-osc-clk";
reg = <0x01c20050 0x4>;
clock-frequency = <24000000>;
};
@ -53,6 +54,111 @@
compatible = "fixed-clock";
clock-frequency = <32768>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
/*
* This is a dummy clock, to be used as placeholder on
* other mux clocks when a specific parent clock is not
* yet implemented. It should be dropped when the driver
* is complete.
*/
pll6: pll6 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
};
axi: axi@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-axi-clk";
reg = <0x01c20054 0x4>;
clocks = <&cpu>;
};
ahb: ahb@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-ahb-clk";
reg = <0x01c20054 0x4>;
clocks = <&axi>;
};
ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
"ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
"ahb_nand", "ahb_sdram", "ahb_ace",
"ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
"ahb_spi2", "ahb_spi3", "ahb_sata",
"ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
"ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
"ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
"ahb_de_fe1", "ahb_gmac", "ahb_mp",
"ahb_mali";
};
apb0: apb0@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
reg = <0x01c20054 0x4>;
clocks = <&ahb>;
};
apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
"apb0_iis2", "apb0_keypad";
};
apb1_mux: apb1_mux@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-mux-clk";
reg = <0x01c20058 0x4>;
clocks = <&osc24M>, <&pll6>, <&osc32k>;
};
apb1: apb1@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb1-clk";
reg = <0x01c20058 0x4>;
clocks = <&apb1_mux>;
};
apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
"apb1_i2c4", "apb1_uart0", "apb1_uart1",
"apb1_uart2", "apb1_uart3", "apb1_uart4",
"apb1_uart5", "apb1_uart6", "apb1_uart7";
};
};
soc@01c00000 {
@ -61,6 +167,39 @@
#size-cells = <1>;
ranges;
pio: pinctrl@01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <0 28 1>;
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <3>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PB22", "PB23";
allwinner,function = "uart0";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart6_pins_a: uart6@0 {
allwinner,pins = "PI12", "PI13";
allwinner,function = "uart6";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
uart7_pins_a: uart7@0 {
allwinner,pins = "PI20", "PI21";
allwinner,function = "uart7";
allwinner,drive = <0>;
allwinner,pull = <0>;
};
};
timer@01c20c00 {
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0x90>;
@ -84,7 +223,7 @@
interrupts = <0 1 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 16>;
status = "disabled";
};
@ -94,7 +233,7 @@
interrupts = <0 2 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 17>;
status = "disabled";
};
@ -104,7 +243,7 @@
interrupts = <0 3 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 18>;
status = "disabled";
};
@ -114,7 +253,7 @@
interrupts = <0 4 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 19>;
status = "disabled";
};
@ -124,7 +263,7 @@
interrupts = <0 17 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 20>;
status = "disabled";
};
@ -134,7 +273,7 @@
interrupts = <0 18 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 21>;
status = "disabled";
};
@ -144,7 +283,7 @@
interrupts = <0 19 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 22>;
status = "disabled";
};
@ -154,7 +293,7 @@
interrupts = <0 20 1>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&apb1_gates 23>;
status = "disabled";
};

25
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

@ -37,30 +37,35 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
cci-control-port = <&cci_control1>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
cci-control-port = <&cci_control1>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control2>;
};
cpu4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control2>;
};
};
@ -104,6 +109,26 @@
interrupts = <1 9 0xf04>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x2c090000 0 0x1000>;
ranges = <0x0 0x0 0x2c090000 0x10000>;
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
};
memory-controller@7ffd0000 {
compatible = "arm,pl354", "arm,primecell";
reg = <0 0x7ffd0000 0 0x1000>;

4
arch/arm/configs/at91_dt_defconfig

@ -14,11 +14,13 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_SOC_AT91RM9200=y
CONFIG_SOC_AT91SAM9260=y
CONFIG_SOC_AT91SAM9263=y
CONFIG_SOC_AT91SAM9G45=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_SOC_AT91SAM9N12=y
CONFIG_MACH_AT91RM9200_DT=y
CONFIG_MACH_AT91SAM9_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=128
@ -62,6 +64,7 @@ CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
@ -78,7 +81,6 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_MACB=y
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_FARADAY is not set

2
arch/arm/include/asm/mach/arch.h

@ -35,7 +35,7 @@ struct machine_desc {
unsigned int nr_irqs; /* number of IRQs */
#ifdef CONFIG_ZONE_DMA
unsigned long dma_zone_size; /* size of DMA-able area */
phys_addr_t dma_zone_size; /* size of DMA-able area */
#endif
unsigned int video_start; /* start of video RAM */

4
arch/arm/include/asm/outercache.h

@ -37,10 +37,10 @@ struct outer_cache_fns {
void (*resume)(void);
};
#ifdef CONFIG_OUTER_CACHE
extern struct outer_cache_fns outer_cache;
#ifdef CONFIG_OUTER_CACHE
static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
{
if (outer_cache.inv_range)

1
arch/arm/mach-at91/include/mach/hardware.h

@ -33,6 +33,7 @@
#include <mach/at91sam9g45.h>
#include <mach/at91sam9x5.h>
#include <mach/at91sam9n12.h>
#include <mach/sama5d3.h>
/*
* On all at91 except rm9200 and x40 have the System Controller starts

8
arch/arm/mach-at91/include/mach/sama5d3.h

@ -64,6 +64,14 @@
#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
/*
* User Peripheral physical base addresses.
*/
#define SAMA5D3_BASE_USART0 0xf001c000
#define SAMA5D3_BASE_USART1 0xf0020000
#define SAMA5D3_BASE_USART2 0xf8020000
#define SAMA5D3_BASE_USART3 0xf8024000
/*
* Internal Memory
*/

13
arch/arm/mach-at91/include/mach/uncompress.h

@ -94,6 +94,15 @@ static const u32 uarts_sam9x5[] = {
0,
};
static const u32 uarts_sama5[] = {
AT91_BASE_DBGU1,
SAMA5D3_BASE_USART0,
SAMA5D3_BASE_USART1,
SAMA5D3_BASE_USART2,
SAMA5D3_BASE_USART3,
0,
};
static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{
u32 cidr, socid;
@ -121,8 +130,12 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
case ARCH_ID_AT91SAM9RL64:
return uarts_sam9rl;
case ARCH_ID_AT91SAM9N12:
case ARCH_ID_AT91SAM9X5:
return uarts_sam9x5;
case ARCH_ID_SAMA5D3:
return uarts_sama5;
}
/* at91sam9g10 */

7
arch/arm/mach-exynos/Kconfig

@ -36,6 +36,7 @@ config CPU_EXYNOS4210
bool "SAMSUNG EXYNOS4210"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select ARM_CPU_SUSPEND if PM
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
@ -49,7 +50,9 @@ config SOC_EXYNOS4212
bool "SAMSUNG EXYNOS4212"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
@ -60,7 +63,9 @@ config SOC_EXYNOS4412
bool "SAMSUNG EXYNOS4412"
default y
depends on ARCH_EXYNOS4
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
select SAMSUNG_DMADEV
help
Enable EXYNOS4412 SoC support
@ -69,6 +74,7 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
select ARCH_HAS_BANDGAP
select PINCTRL_EXYNOS
select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM
@ -93,6 +99,7 @@ config SOC_EXYNOS5440
default y
depends on ARCH_EXYNOS5
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_HAS_BANDGAP
select ARCH_HAS_OPP
select HAVE_ARM_ARCH_TIMER
select AUTO_ZRELADDR

3
arch/arm/mach-exynos/cpuidle.c

@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
if (soc_is_exynos5250())
exynos5_core_down_clk();
if (soc_is_exynos5440())
exynos4_idle_driver.state_count = 1;
ret = cpuidle_register_driver(&exynos4_idle_driver);
if (ret) {
printk(KERN_ERR "CPUidle failed to register driver\n");

6
arch/arm/mach-highbank/Kconfig

@ -1,9 +1,14 @@
config ARCH_HIGHBANK
bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARCH_HAS_CPUFREQ
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_HAS_OPP
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_ERRATA_764369
select ARM_ERRATA_775420
select ARM_ERRATA_798181
select ARM_GIC
select ARM_TIMER_SP804
select CACHE_L2X0
@ -18,3 +23,4 @@ config ARCH_HIGHBANK
select PL320_MBOX
select SPARSE_IRQ
select USE_OF
select ZONE_DMA if ARM_LPAE

20
arch/arm/mach-highbank/highbank.c

@ -18,14 +18,11 @@
#include <linux/clocksource.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/amba/bus.h>
#include <linux/clk-provider.h>
@ -35,7 +32,6 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "core.h"
#include "sysregs.h"
@ -65,13 +61,11 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
HB_JUMP_TABLE_PHYS(cpu) + 15);
}
#ifdef CONFIG_CACHE_L2X0
static void highbank_l2x0_disable(void)
{
/* Disable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x0);
}
#endif
static void __init highbank_init_irq(void)
{
@ -80,12 +74,13 @@ static void __init highbank_init_irq(void)
if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
highbank_scu_map_io();
#ifdef CONFIG_CACHE_L2X0
/* Enable PL310 L2 Cache controller */
highbank_smc1(0x102, 0x1);
l2x0_of_init(0, ~0UL);
outer_cache.disable = highbank_l2x0_disable;
#endif
if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
highbank_smc1(0x102, 0x1);
l2x0_of_init(0, ~0UL);
outer_cache.disable = highbank_l2x0_disable;
}
}
static void __init highbank_timer_init(void)
@ -176,6 +171,9 @@ static const char *highbank_match[] __initconst = {
};
DT_MACHINE_START(HIGHBANK, "Highbank")
#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
.dma_zone_size = (4ULL * SZ_1G),
#endif
.smp = smp_ops(highbank_smp_ops),
.init_irq = highbank_init_irq,
.init_time = highbank_timer_init,

2
arch/arm/mach-mmp/Makefile

@ -2,7 +2,7 @@
# Makefile for Marvell's PXA168 processors line
#
obj-y += common.o devices.o time.o irq.o
obj-y += common.o devices.o time.o
# SoC support
obj-$(CONFIG_CPU_PXA168) += pxa168.o

1
arch/arm/mach-mmp/common.h

@ -3,7 +3,6 @@
extern void timer_init(int irq);
extern void __init icu_init_irq(void);
extern void __init mmp_map_io(void);
extern void mmp_restart(enum reboot_mode, const char *);
extern void __init pxa168_clk_init(void);

26
arch/arm/mach-mmp/include/mach/entry-macro.S

@ -1,26 +0,0 @@
/*
* linux/arch/arm/mach-mmp/include/mach/entry-macro.S
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/irq.h>
#include <mach/regs-icu.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
and \tmp, \tmp, #0xff00
cmp \tmp, #0x5800
ldr \base, =mmp_icu_base
ldr \base, [\base, #0]
addne \base, \base, #0x10c @ PJ1 AP INT SEL register
addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \tmp, [\base, #0]
and \irqnr, \tmp, #0x3f
tst \tmp, #(1 << 6)
.endm

1
arch/arm/mach-mmp/include/mach/pxa168.h

@ -4,6 +4,7 @@
#include <linux/reboot.h>
extern void pxa168_timer_init(void);
extern void __init icu_init_irq(void);
extern void __init pxa168_init_irq(void);
extern void pxa168_restart(enum reboot_mode, const char *);
extern void pxa168_clear_keypad_wakeup(void);

1
arch/arm/mach-mmp/include/mach/pxa910.h

@ -2,6 +2,7 @@
#define __ASM_MACH_PXA910_H
extern void pxa910_timer_init(void);
extern void __init icu_init_irq(void);
extern void __init pxa910_init_irq(void);
#include <linux/i2c.h>

8
arch/arm/mach-mmp/mmp-dt.c

@ -9,17 +9,13 @@
* publishhed by the Free Software Foundation.
*/
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include "common.h"
extern void __init mmp_dt_irq_init(void);
extern void __init mmp_dt_init_timer(void);
static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = {
DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = mmp_dt_irq_init,
.init_time = mmp_dt_init_timer,
.init_machine = pxa168_dt_init,
.dt_compat = mmp_dt_board_compat,
@ -72,7 +67,6 @@ MACHINE_END
DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = mmp_dt_irq_init,
.init_time = mmp_dt_init_timer,
.init_machine = pxa910_dt_init,
.dt_compat = mmp_dt_board_compat,

8
arch/arm/mach-mmp/mmp2-dt.c

@ -10,18 +10,13 @@
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include <mach/regs-apbc.h>
#include "common.h"
extern void __init mmp_dt_irq_init(void);
extern void __init mmp_dt_init_timer(void);
static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
.map_io = mmp_map_io,
.init_irq = mmp_dt_irq_init,
.init_time = mmp_dt_init_timer,
.init_machine = mmp2_dt_init,
.dt_compat = mmp2_dt_board_compat,

6
arch/arm/mach-mmp/mmp2.c

@ -13,6 +13,8 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/mmp.h>
#include <linux/platform_device.h>
#include <asm/hardware/cache-tauros2.h>
@ -26,6 +28,7 @@
#include <mach/mfp.h>
#include <mach/devices.h>
#include <mach/mmp2.h>
#include <mach/pm-mmp2.h>
#include "common.h"
@ -94,6 +97,9 @@ void mmp2_clear_pmic_int(void)
void __init mmp2_init_irq(void)
{
mmp2_init_icu();
#ifdef CONFIG_PM
icu_irq_chip.irq_set_wake = mmp2_set_wake;
#endif
}
static int __init mmp2_init(void)

7
arch/arm/mach-mmp/pxa910.c

@ -12,6 +12,8 @@
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/mmp.h>
#include <linux/platform_device.h>
#include <asm/hardware/cache-tauros2.h>
@ -23,6 +25,8 @@
#include <mach/dma.h>
#include <mach/mfp.h>
#include <mach/devices.h>
#include <mach/pm-pxa910.h>
#include <mach/pxa910.h>
#include "common.h"
@ -79,6 +83,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
void __init pxa910_init_irq(void)
{
icu_init_irq();
#ifdef CONFIG_PM
icu_irq_chip.irq_set_wake = pxa910_set_wake;
#endif
}
static int __init pxa910_init(void)

4
arch/arm/mach-omap2/Makefile

@ -63,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@ -148,6 +149,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@ -166,6 +168,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@ -209,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o

1
arch/arm/mach-omap2/board-generic.c

@ -238,5 +238,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
.init_machine = omap_generic_init,
.init_time = omap5_realtime_timer_init,
.dt_compat = dra7xx_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
#endif

5
arch/arm/mach-omap2/cclock33xx_data.c

@ -421,6 +421,10 @@ static struct clk aes0_fck;
DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
static struct clk rng_fck;
DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
/*
* Modules clock nodes
*
@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
CLK(NULL, "sha0_fck", &sha0_fck),
CLK(NULL, "aes0_fck", &aes0_fck),
CLK(NULL, "rng_fck", &rng_fck),
CLK(NULL, "timer1_fck", &timer1_fck),
CLK(NULL, "timer2_fck", &timer2_fck),
CLK(NULL, "timer3_fck", &timer3_fck),

20
arch/arm/mach-omap2/cclock44xx_data.c

@ -1706,6 +1706,18 @@ int __init omap4xxx_clk_init(void)
omap2_clk_disable_autoidle_all();
/*
* A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
* when its in bypass. So always lock USB before ABE DPLL.
*/
/*
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
/*
* On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
* state when turning the ABE clock domain. Workaround this by
@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
/*
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
* domain can transition to retention state when not in use.
*/
rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
if (rc)
pr_err("%s: failed to configure USB DPLL!\n", __func__);
return 0;
}

1
arch/arm/mach-omap2/clockdomain.h

@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);

740
arch/arm/mach-omap2/clockdomains7xx_data.c

@ -0,0 +1,740 @@
/*
* DRA7xx Clock domains framework
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Generated by code originally written by:
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "cm-regbits-7xx.h"
#include "prm7xx.h"
#include "prcm44xx.h"
#include "prcm_mpu7xx.h"
/* Static Dependencies for DRA7xx Clock Domains */
static struct clkdm_dep cam_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ NULL },
};
static struct clkdm_dep dma_wkup_sleep_deps[] = {
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },