original development tree for Linux kernel GTP module; now long in mainline.
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linux-gtp/drivers/pinctrl/spear/pinctrl-spear320.c

3469 lines
89 KiB

/*
* Driver for the ST Microelectronics SPEAr320 pinmux
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.linux@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear3xx.h"
#define DRIVER_NAME "spear320-pinmux"
/* addresses */
#define PMX_CONFIG_REG 0x0C
#define MODE_CONFIG_REG 0x10
#define MODE_EXT_CONFIG_REG 0x18
/* modes */
#define AUTO_NET_SMII_MODE (1 << 0)
#define AUTO_NET_MII_MODE (1 << 1)
#define AUTO_EXP_MODE (1 << 2)
#define SMALL_PRINTERS_MODE (1 << 3)
#define EXTENDED_MODE (1 << 4)
static struct spear_pmx_mode pmx_mode_auto_net_smii = {
.name = "Automation Networking SMII mode",
.mode = AUTO_NET_SMII_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x0,
};
static struct spear_pmx_mode pmx_mode_auto_net_mii = {
.name = "Automation Networking MII mode",
.mode = AUTO_NET_MII_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x1,
};
static struct spear_pmx_mode pmx_mode_auto_exp = {
.name = "Automation Expanded mode",
.mode = AUTO_EXP_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x2,
};
static struct spear_pmx_mode pmx_mode_small_printers = {
.name = "Small Printers mode",
.mode = SMALL_PRINTERS_MODE,
.reg = MODE_CONFIG_REG,
.mask = 0x00000007,
.val = 0x3,
};
static struct spear_pmx_mode pmx_mode_extended = {
.name = "extended mode",
.mode = EXTENDED_MODE,
.reg = MODE_EXT_CONFIG_REG,
.mask = 0x00000001,
.val = 0x1,
};
static struct spear_pmx_mode *spear320_pmx_modes[] = {
&pmx_mode_auto_net_smii,
&pmx_mode_auto_net_mii,
&pmx_mode_auto_exp,
&pmx_mode_small_printers,
&pmx_mode_extended,
};
/* Extended mode registers and their offsets */
#define EXT_CTRL_REG 0x0018
#define MII_MDIO_MASK (1 << 4)
#define MII_MDIO_10_11_VAL 0
#define MII_MDIO_81_VAL (1 << 4)
#define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
#define MAC_MODE_MII 0
#define MAC_MODE_RMII 1
#define MAC_MODE_SMII 2
#define MAC_MODE_SS_SMII 3
#define MAC_MODE_MASK 0x3
#define MAC1_MODE_SHIFT 16
#define MAC2_MODE_SHIFT 18
#define IP_SEL_PAD_0_9_REG 0x00A4
#define PMX_PL_0_1_MASK (0x3F << 0)
#define PMX_UART2_PL_0_1_VAL 0x0
#define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
#define PMX_PL_2_3_MASK (0x3F << 6)
#define PMX_I2C2_PL_2_3_VAL 0x0
#define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
#define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_4_5_MASK (0x3F << 12)
#define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
#define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_5_MASK (0x7 << 15)
#define PMX_TOUCH_Y_PL_5_VAL 0x0
#define PMX_PL_6_7_MASK (0x3F << 18)
#define PMX_PL_6_MASK (0x7 << 18)
#define PMX_PL_7_MASK (0x7 << 21)
#define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_PWM_3_PL_6_VAL (0x2 << 18)
#define PMX_PWM_2_PL_7_VAL (0x2 << 21)
#define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_8_9_MASK (0x3F << 24)
#define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
#define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_10_19_REG 0x00A8
#define PMX_PL_10_11_MASK (0x3F << 0)
#define PMX_SMII_PL_10_11_VAL 0
#define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_12_MASK (0x7 << 6)
#define PMX_PWM3_PL_12_VAL 0
#define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
#define PMX_PL_13_14_MASK (0x3F << 9)
#define PMX_PL_13_MASK (0x7 << 9)
#define PMX_PL_14_MASK (0x7 << 12)
#define PMX_SSP2_PL_13_14_15_16_VAL 0
#define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
#define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
#define PMX_PWM2_PL_13_VAL (0x2 << 9)
#define PMX_PWM1_PL_14_VAL (0x2 << 12)
#define PMX_PL_15_MASK (0x7 << 15)
#define PMX_PWM0_PL_15_VAL (0x2 << 15)
#define PMX_PL_15_16_MASK (0x3F << 15)
#define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
#define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
#define PMX_PL_17_18_MASK (0x3F << 21)
#define PMX_SSP1_PL_17_18_19_20_VAL 0
#define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
#define PMX_PL_19_MASK (0x7 << 27)
#define PMX_I2C2_PL_19_VAL (0x1 << 27)
#define PMX_RMII_PL_19_VAL (0x4 << 27)
#define IP_SEL_PAD_20_29_REG 0x00AC
#define PMX_PL_20_MASK (0x7 << 0)
#define PMX_I2C2_PL_20_VAL (0x1 << 0)
#define PMX_RMII_PL_20_VAL (0x4 << 0)
#define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
#define PMX_SMII_PL_21_TO_27_VAL 0
#define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
#define PMX_PL_28_29_MASK (0x3F << 24)
#define PMX_PL_28_MASK (0x7 << 24)
#define PMX_PL_29_MASK (0x7 << 27)
#define PMX_UART1_PL_28_29_VAL 0
#define PMX_PWM_3_PL_28_VAL (0x4 << 24)
#define PMX_PWM_2_PL_29_VAL (0x4 << 27)
#define IP_SEL_PAD_30_39_REG 0x00B0
#define PMX_PL_30_31_MASK (0x3F << 0)
#define PMX_CAN1_PL_30_31_VAL (0)
#define PMX_PL_30_MASK (0x7 << 0)
#define PMX_PL_31_MASK (0x7 << 3)
#define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
#define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
#define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
#define PMX_PL_32_33_MASK (0x3F << 6)
#define PMX_CAN0_PL_32_33_VAL 0
#define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
#define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_34_MASK (0x7 << 12)
#define PMX_PWM2_PL_34_VAL 0
#define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
#define PMX_SSP2_PL_34_VAL (0x4 << 12)
#define PMX_PL_35_MASK (0x7 << 15)
#define PMX_I2S_REF_CLK_PL_35_VAL 0
#define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
#define PMX_SSP2_PL_35_VAL (0x4 << 15)
#define PMX_PL_36_MASK (0x7 << 18)
#define PMX_TOUCH_X_PL_36_VAL 0
#define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
#define PMX_SSP1_PL_36_VAL (0x4 << 18)
#define PMX_PL_37_38_MASK (0x3F << 21)
#define PMX_PWM0_1_PL_37_38_VAL 0
#define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
#define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
#define PMX_PL_39_MASK (0x7 << 27)
#define PMX_I2S_PL_39_VAL 0
#define PMX_UART4_PL_39_VAL (0x2 << 27)
#define PMX_SSP1_PL_39_VAL (0x4 << 27)
#define IP_SEL_PAD_40_49_REG 0x00B4
#define PMX_PL_40_MASK (0x7 << 0)
#define PMX_I2S_PL_40_VAL 0
#define PMX_UART4_PL_40_VAL (0x2 << 0)
#define PMX_PWM3_PL_40_VAL (0x4 << 0)
#define PMX_PL_41_42_MASK (0x3F << 3)
#define PMX_PL_41_MASK (0x7 << 3)
#define PMX_PL_42_MASK (0x7 << 6)
#define PMX_I2S_PL_41_42_VAL 0
#define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
#define PMX_PWM2_PL_41_VAL (0x4 << 3)
#define PMX_PWM1_PL_42_VAL (0x4 << 6)
#define PMX_PL_43_MASK (0x7 << 9)
#define PMX_SDHCI_PL_43_VAL 0
#define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
#define PMX_PWM0_PL_43_VAL (0x4 << 9)
#define PMX_PL_44_45_MASK (0x3F << 12)
#define PMX_SDHCI_PL_44_45_VAL 0
#define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
#define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_46_47_MASK (0x3F << 18)
#define PMX_SDHCI_PL_46_47_VAL 0
#define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_48_49_MASK (0x3F << 24)
#define PMX_SDHCI_PL_48_49_VAL 0
#define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_50_59_REG 0x00B8
#define PMX_PL_50_51_MASK (0x3F << 0)
#define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
#define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_50_MASK (0x7 << 0)
#define PMX_PL_51_MASK (0x7 << 3)
#define PMX_SDHCI_PL_50_VAL 0
#define PMX_SDHCI_CD_PL_51_VAL 0
#define PMX_PL_52_53_MASK (0x3F << 6)
#define PMX_FSMC_PL_52_53_VAL 0
#define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
#define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_54_55_56_MASK (0x1FF << 12)
#define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
#define PMX_PL_57_MASK (0x7 << 21)
#define PMX_FSMC_PL_57_VAL 0
#define PMX_PWM3_PL_57_VAL (0x4 << 21)
#define PMX_PL_58_59_MASK (0x3F << 24)
#define PMX_PL_58_MASK (0x7 << 24)
#define PMX_PL_59_MASK (0x7 << 27)
#define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_PWM2_PL_58_VAL (0x4 << 24)
#define PMX_PWM1_PL_59_VAL (0x4 << 27)
#define IP_SEL_PAD_60_69_REG 0x00BC
#define PMX_PL_60_MASK (0x7 << 0)
#define PMX_FSMC_PL_60_VAL 0
#define PMX_PWM0_PL_60_VAL (0x4 << 0)
#define PMX_PL_61_TO_64_MASK (0xFFF << 3)
#define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
#define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
#define PMX_PL_65_TO_68_MASK (0xFFF << 15)
#define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
#define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
#define PMX_PL_69_MASK (0x7 << 27)
#define PMX_CLCD_PL_69_VAL (0)
#define PMX_EMI_PL_69_VAL (0x2 << 27)
#define PMX_SPP_PL_69_VAL (0x3 << 27)
#define PMX_UART5_PL_69_VAL (0x4 << 27)
#define IP_SEL_PAD_70_79_REG 0x00C0
#define PMX_PL_70_MASK (0x7 << 0)
#define PMX_CLCD_PL_70_VAL (0)
#define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
#define PMX_SPP_PL_70_VAL (0x3 << 0)
#define PMX_UART5_PL_70_VAL (0x4 << 0)
#define PMX_PL_71_72_MASK (0x3F << 3)
#define PMX_CLCD_PL_71_72_VAL (0)
#define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
#define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
#define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
#define PMX_PL_73_MASK (0x7 << 9)
#define PMX_CLCD_PL_73_VAL (0)
#define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
#define PMX_SPP_PL_73_VAL (0x3 << 9)
#define PMX_UART3_PL_73_VAL (0x4 << 9)
#define PMX_PL_74_MASK (0x7 << 12)
#define PMX_CLCD_PL_74_VAL (0)
#define PMX_EMI_PL_74_VAL (0x2 << 12)
#define PMX_SPP_PL_74_VAL (0x3 << 12)
#define PMX_UART3_PL_74_VAL (0x4 << 12)
#define PMX_PL_75_76_MASK (0x3F << 15)
#define PMX_CLCD_PL_75_76_VAL (0)
#define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
#define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
#define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
#define PMX_PL_77_78_79_MASK (0x1FF << 21)
#define PMX_CLCD_PL_77_78_79_VAL (0)
#define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
#define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
#define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_80_89_REG 0x00C4
#define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
#define PMX_CLCD_PL_80_TO_85_VAL 0
#define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
#define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
#define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
#define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
#define PMX_PL_86_87_MASK (0x3F << 18)
#define PMX_PL_86_MASK (0x7 << 18)
#define PMX_PL_87_MASK (0x7 << 21)
#define PMX_CLCD_PL_86_87_VAL 0
#define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_PWM3_PL_86_VAL (0x4 << 18)
#define PMX_PWM2_PL_87_VAL (0x4 << 21)
#define PMX_PL_88_89_MASK (0x3F << 24)
#define PMX_CLCD_PL_88_89_VAL 0
#define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
#define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
#define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
#define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
#define IP_SEL_PAD_90_99_REG 0x00C8
#define PMX_PL_90_91_MASK (0x3F << 0)
#define PMX_CLCD_PL_90_91_VAL 0
#define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
#define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
#define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
#define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_PL_92_93_MASK (0x3F << 6)
#define PMX_CLCD_PL_92_93_VAL 0
#define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
#define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
#define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
#define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
#define PMX_PL_94_95_MASK (0x3F << 12)
#define PMX_CLCD_PL_94_95_VAL 0
#define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
#define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
#define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
#define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
#define PMX_PL_96_97_MASK (0x3F << 18)
#define PMX_CLCD_PL_96_97_VAL 0
#define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
#define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
#define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
#define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
#define PMX_PL_98_MASK (0x7 << 24)
#define PMX_CLCD_PL_98_VAL 0
#define PMX_I2C1_PL_98_VAL (0x2 << 24)
#define PMX_UART3_PL_98_VAL (0x4 << 24)
#define PMX_PL_99_MASK (0x7 << 27)
#define PMX_SDHCI_PL_99_VAL 0
#define PMX_I2C1_PL_99_VAL (0x2 << 27)
#define PMX_UART3_PL_99_VAL (0x4 << 27)
#define IP_SEL_MIX_PAD_REG 0x00CC
#define PMX_PL_100_101_MASK (0x3F << 0)
#define PMX_SDHCI_PL_100_101_VAL 0
#define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
#define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
#define PMX_SSP1_PORT_94_TO_97_VAL 0
#define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
#define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
#define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
#define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
#define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
#define PMX_SSP2_PORT_90_TO_93_VAL 0
#define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
#define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
#define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
#define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
#define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
#define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
#define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
#define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
#define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
#define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
#define PMX_UART3_PORT_94_VAL 0
#define PMX_UART3_PORT_73_VAL (0x1 << 16)
#define PMX_UART3_PORT_52_VAL (0x2 << 16)
#define PMX_UART3_PORT_41_VAL (0x3 << 16)
#define PMX_UART3_PORT_15_VAL (0x4 << 16)
#define PMX_UART3_PORT_8_VAL (0x5 << 16)
#define PMX_UART3_PORT_99_VAL (0x6 << 16)
#define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
#define PMX_UART4_PORT_92_VAL 0
#define PMX_UART4_PORT_71_VAL (0x1 << 19)
#define PMX_UART4_PORT_39_VAL (0x2 << 19)
#define PMX_UART4_PORT_13_VAL (0x3 << 19)
#define PMX_UART4_PORT_6_VAL (0x4 << 19)
#define PMX_UART4_PORT_101_VAL (0x5 << 19)
#define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
#define PMX_UART5_PORT_90_VAL 0
#define PMX_UART5_PORT_69_VAL (0x1 << 22)
#define PMX_UART5_PORT_37_VAL (0x2 << 22)
#define PMX_UART5_PORT_4_VAL (0x3 << 22)
#define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
#define PMX_UART6_PORT_88_VAL 0
#define PMX_UART6_PORT_2_VAL (0x1 << 24)
#define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
#define PMX_I2C1_PORT_8_9_VAL 0
#define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
#define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
#define PMX_I2C2_PORT_96_97_VAL 0
#define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
#define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
#define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
#define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
#define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
#define PMX_SDHCI_CD_PORT_12_VAL 0
#define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
/* Pad multiplexing for CLCD device */
static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
97 };
static struct spear_muxreg clcd_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_CLCD_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
PMX_PL_88_89_MASK,
.val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
PMX_CLCD_PL_88_89_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
.val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
PMX_CLCD_PL_98_VAL,
},
};
static struct spear_modemux clcd_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = clcd_muxreg,
.nmuxregs = ARRAY_SIZE(clcd_muxreg),
},
};
static struct spear_pingroup clcd_pingroup = {
.name = "clcd_grp",
.pins = clcd_pins,
.npins = ARRAY_SIZE(clcd_pins),
.modemuxs = clcd_modemux,
.nmodemuxs = ARRAY_SIZE(clcd_modemux),
};
static const char *const clcd_grps[] = { "clcd_grp" };
static struct spear_function clcd_function = {
.name = "clcd",
.groups = clcd_grps,
.ngroups = ARRAY_SIZE(clcd_grps),
};
/* Pad multiplexing for EMI (Parallel NOR flash) device */
static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
93, 94, 95, 96, 97 };
static struct spear_muxreg emi_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg emi_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
.val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
PMX_FSMC_EMI_PL_54_55_56_VAL |
PMX_FSMC_EMI_PL_58_59_VAL,
}, {
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_EMI_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
PMX_PL_88_89_MASK,
.val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
PMX_EMI_PL_88_89_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
.val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
},
};
static struct spear_modemux emi_modemux[] = {
{
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
.muxregs = emi_muxreg,
.nmuxregs = ARRAY_SIZE(emi_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = emi_ext_muxreg,
.nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
},
};
static struct spear_pingroup emi_pingroup = {
.name = "emi_grp",
.pins = emi_pins,
.npins = ARRAY_SIZE(emi_pins),
.modemuxs = emi_modemux,
.nmodemuxs = ARRAY_SIZE(emi_modemux),
};
static const char *const emi_grps[] = { "emi_grp" };
static struct spear_function emi_function = {
.name = "emi",
.groups = emi_grps,
.ngroups = ARRAY_SIZE(emi_grps),
};
/* Pad multiplexing for FSMC (NAND flash) device */
static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66, 67, 68 };
static struct spear_muxreg fsmc_8bit_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
PMX_PL_57_MASK | PMX_PL_58_59_MASK,
.val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
}, {
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
PMX_PL_65_TO_68_MASK,
.val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
PMX_FSMC_PL_65_TO_68_VAL,
}, {
.reg = EXT_CTRL_REG,
.mask = EMI_FSMC_DYNAMIC_MUX_MASK,
.val = EMI_FSMC_DYNAMIC_MUX_MASK,
},
};
static struct spear_modemux fsmc_8bit_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
},
};
static struct spear_pingroup fsmc_8bit_pingroup = {
.name = "fsmc_8bit_grp",
.pins = fsmc_8bit_pins,
.npins = ARRAY_SIZE(fsmc_8bit_pins),
.modemuxs = fsmc_8bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
};
static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg fsmc_16bit_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
.val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
.val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
PMX_FSMC_EMI_PL_73_VAL,
}
};
static struct spear_modemux fsmc_16bit_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = fsmc_8bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
}, {
.modes = AUTO_EXP_MODE | EXTENDED_MODE,
.muxregs = fsmc_16bit_autoexp_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = fsmc_16bit_muxreg,
.nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
},
};
static struct spear_pingroup fsmc_16bit_pingroup = {
.name = "fsmc_16bit_grp",
.pins = fsmc_16bit_pins,
.npins = ARRAY_SIZE(fsmc_16bit_pins),
.modemuxs = fsmc_16bit_modemux,
.nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
};
static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
static struct spear_function fsmc_function = {
.name = "fsmc",
.groups = fsmc_grps,
.ngroups = ARRAY_SIZE(fsmc_grps),
};
/* Pad multiplexing for SPP device */
static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80, 81, 82, 83, 84, 85 };
static struct spear_muxreg spp_muxreg[] = {
{
.reg = IP_SEL_PAD_60_69_REG,
.mask = PMX_PL_69_MASK,
.val = PMX_SPP_PL_69_VAL,
}, {
.reg = IP_SEL_PAD_70_79_REG,
.mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
PMX_PL_74_MASK | PMX_PL_75_76_MASK |
PMX_PL_77_78_79_MASK,
.val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
}, {
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK,
.val = PMX_SPP_PL_80_TO_85_VAL,
},
};
static struct spear_modemux spp_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = spp_muxreg,
.nmuxregs = ARRAY_SIZE(spp_muxreg),
},
};
static struct spear_pingroup spp_pingroup = {
.name = "spp_grp",
.pins = spp_pins,
.npins = ARRAY_SIZE(spp_pins),
.modemuxs = spp_modemux,
.nmodemuxs = ARRAY_SIZE(spp_modemux),
};
static const char *const spp_grps[] = { "spp_grp" };
static struct spear_function spp_function = {
.name = "spp",
.groups = spp_grps,
.ngroups = ARRAY_SIZE(spp_grps),
};
/* Pad multiplexing for SDHCI device */
static const unsigned sdhci_led_pins[] = { 34 };
static struct spear_muxreg sdhci_led_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg sdhci_led_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_34_MASK,
.val = PMX_PWM2_PL_34_VAL,
},
};
static struct spear_modemux sdhci_led_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = sdhci_led_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = sdhci_led_ext_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
},
};
static struct spear_pingroup sdhci_led_pingroup = {
.name = "sdhci_led_grp",
.pins = sdhci_led_pins,
.npins = ARRAY_SIZE(sdhci_led_pins),
.modemuxs = sdhci_led_modemux,
.nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
};
static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
50};
static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
};
static struct spear_muxreg sdhci_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
.val = 0,
},
};
static struct spear_muxreg sdhci_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
PMX_PL_48_49_MASK,
.val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
}, {
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_50_MASK,
.val = PMX_SDHCI_PL_50_VAL,
}, {
.reg = IP_SEL_PAD_90_99_REG,
.mask = PMX_PL_99_MASK,
.val = PMX_SDHCI_PL_99_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_PL_100_101_MASK,
.val = PMX_SDHCI_PL_100_101_VAL,
},
};
static struct spear_muxreg sdhci_cd_12_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_MII_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_10_19_REG,
.mask = PMX_PL_12_MASK,
.val = PMX_SDHCI_CD_PL_12_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
.val = PMX_SDHCI_CD_PORT_12_VAL,
},
};
static struct spear_muxreg sdhci_cd_51_muxreg[] = {
{
.reg = IP_SEL_PAD_50_59_REG,
.mask = PMX_PL_51_MASK,
.val = PMX_SDHCI_CD_PL_51_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_SDHCI_CD_PORT_SEL_MASK,
.val = PMX_SDHCI_CD_PORT_51_VAL,
},
};
#define pmx_sdhci_common_modemux \
{ \
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
SMALL_PRINTERS_MODE | EXTENDED_MODE, \
.muxregs = sdhci_muxreg, \
.nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
}, { \
.modes = EXTENDED_MODE, \
.muxregs = sdhci_ext_muxreg, \
.nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
}
static struct spear_modemux sdhci_modemux[][3] = {
{
/* select pin 12 for cd */
pmx_sdhci_common_modemux,
{
.modes = EXTENDED_MODE,
.muxregs = sdhci_cd_12_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
},
}, {
/* select pin 51 for cd */
pmx_sdhci_common_modemux,
{
.modes = EXTENDED_MODE,
.muxregs = sdhci_cd_51_muxreg,
.nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
},
}
};
static struct spear_pingroup sdhci_pingroup[] = {
{
.name = "sdhci_cd_12_grp",
.pins = sdhci_cd_12_pins,
.npins = ARRAY_SIZE(sdhci_cd_12_pins),
.modemuxs = sdhci_modemux[0],
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
}, {
.name = "sdhci_cd_51_grp",
.pins = sdhci_cd_51_pins,
.npins = ARRAY_SIZE(sdhci_cd_51_pins),
.modemuxs = sdhci_modemux[1],
.nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
},
};
static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
"sdhci_led_grp" };
static struct spear_function sdhci_function = {
.name = "sdhci",
.groups = sdhci_grps,
.ngroups = ARRAY_SIZE(sdhci_grps),
};
/* Pad multiplexing for I2S device */
static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
static struct spear_muxreg i2s_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_SSP_CS_MASK,
.val = 0,
}, {
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MODEM_MASK,
.val = 0,
},
};
static struct spear_muxreg i2s_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
.val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
.val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
},
};
static struct spear_modemux i2s_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
.muxregs = i2s_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = i2s_ext_muxreg,
.nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
},
};
static struct spear_pingroup i2s_pingroup = {
.name = "i2s_grp",
.pins = i2s_pins,
.npins = ARRAY_SIZE(i2s_pins),
.modemuxs = i2s_modemux,
.nmodemuxs = ARRAY_SIZE(i2s_modemux),
};
static const char *const i2s_grps[] = { "i2s_grp" };
static struct spear_function i2s_function = {
.name = "i2s",
.groups = i2s_grps,
.ngroups = ARRAY_SIZE(i2s_grps),
};
/* Pad multiplexing for UART1 device */
static const unsigned uart1_pins[] = { 28, 29 };
static struct spear_muxreg uart1_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_ext_muxreg[] = {
{
.reg = IP_SEL_PAD_20_29_REG,
.mask = PMX_PL_28_29_MASK,
.val = PMX_UART1_PL_28_29_VAL,
},
};
static struct spear_modemux uart1_modemux[] = {
{
.modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
| SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = uart1_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart1_ext_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
},
};
static struct spear_pingroup uart1_pingroup = {
.name = "uart1_grp",
.pins = uart1_pins,
.npins = ARRAY_SIZE(uart1_pins),
.modemuxs = uart1_modemux,
.nmodemuxs = ARRAY_SIZE(uart1_modemux),
};
static const char *const uart1_grps[] = { "uart1_grp" };
static struct spear_function uart1_function = {
.name = "uart1",
.groups = uart1_grps,
.ngroups = ARRAY_SIZE(uart1_grps),
};
/* Pad multiplexing for UART1 Modem device */
static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
.val = 0,
}, {
.reg = IP_SEL_PAD_0_9_REG,
.mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
.val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
PMX_UART1_ENH_PL_6_7_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
},
};
static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
PMX_PL_35_MASK | PMX_PL_36_MASK,
.val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
PMX_UART1_ENH_PL_36_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
},
};
static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
{
.reg = PMX_CONFIG_REG,
.mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
PMX_SSP_CS_MASK,
.val = 0,
},
};
static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
{
.reg = IP_SEL_PAD_30_39_REG,
.mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
.val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
PMX_UART1_ENH_PL_36_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
},
};
static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
{
.reg = IP_SEL_PAD_80_89_REG,
.mask = PMX_PL_80_TO_85_MASK,
.val = PMX_UART1_ENH_PL_80_TO_85_VAL,
}, {
.reg = IP_SEL_PAD_40_49_REG,
.mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
.val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
}, {
.reg = IP_SEL_MIX_PAD_REG,
.mask = PMX_UART1_ENH_PORT_SEL_MASK,
.val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
},
};
static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
{
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_2_to_7_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
},
};
static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
{
.modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
.muxregs = uart1_modem_31_to_36_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
}, {
.modes = EXTENDED_MODE,
.muxregs = uart1_modem_ext_31_to_36_muxreg,
.nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
},
};
static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
{
.modes = AUTO_EXP_MODE | EXTENDED_MODE,