466 lines
14 KiB
C
466 lines
14 KiB
C
/*
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* davinci.h - common DaVinci platform definitions
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*
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* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
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*
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* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
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* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef _DAVINCI_H_
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#define _DAVINCI_H_
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#include "common.h"
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#if defined(DM644x)
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#include "dm644x.h"
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#elif defined(DM35x)
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#include "dm35x.h"
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#endif
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/* -------------------------------------------------------------------------- *
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* System Control Module register structure - See sprue14.pdf, Chapter 10 *
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* for more details. *
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* -------------------------------------------------------------------------- */
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struct sys_module_regs_t {
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#if defined(DM644x)
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uint32_t PINMUX[2]; //0x00
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uint32_t DSPBOOTADDR; //0x08
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uint32_t SUSPSRC; //0x0C
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uint32_t INTGEN; //0x10
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#elif defined(DM35x)
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uint32_t PINMUX[5]; //0x00
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#endif
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uint32_t BOOTCFG; //0x14
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uint32_t ARM_INTMUX; //0x18 - ONLY ON DM35x
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uint32_t EDMA_EVTMUX; //0x1C - ONLY ON DM35x
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uint32_t DDR_SLEW; //0x20 - ONLY ON DM35x
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uint32_t CLKOUT; //0x24 - ONLY ON DM35x
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uint32_t DEVICE_ID; //0x28
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uint32_t VDAC_CONFIG; //0x2C - ONLY ON DM35x
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uint32_t TIMER64_CTL; //0x30 - ONLY ON DM35x
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uint32_t USBPHY_CTL; //0x34
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#if defined(DM644x)
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uint32_t CHP_SHRTSW; //0x38
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#elif defined(DM35x)
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uint32_t MISC; //0x38
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#endif
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uint32_t MSTPRI[2]; //0x3C
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uint32_t VPSS_CLKCTL; //0x44
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#if defined(DM644x)
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uint32_t VDD3P3V_PWDN; //0x48
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uint32_t DDRVTPER; //0x4C
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uint32_t RSVD2[8]; //0x50
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#elif defined(DM35x)
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uint32_t DEEPSLEEP; //0x48
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uint32_t RSVD0; //0x4C
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uint32_t DEBOUNCE[8]; //0x50
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uint32_t VTPIOCR; //0x70
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#endif
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};
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#define SYSTEM ((volatile struct sys_module_regs_t *) 0x01C40000)
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/* -------------------------------------------------------------------------- *
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* ARM Interrupt Controller register structure - See sprue26.pdf for more *
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* details. *
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* -------------------------------------------------------------------------- */
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struct aintc_regs_t {
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uint32_t FIQ0;
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uint32_t FIQ1;
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uint32_t IRQ0;
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uint32_t IRQ1;
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uint32_t FIQENTRY;
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uint32_t IRQENTRY;
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uint32_t EINT0;
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uint32_t EINT1;
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uint32_t INTCTL;
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uint32_t EABASE;
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uint32_t RSVD0[2];
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uint32_t INTPRI0;
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uint32_t INTPRI1;
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uint32_t INTPRI2;
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uint32_t INTPRI3;
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uint32_t INTPRI4;
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uint32_t INTPRI5;
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uint32_t INTPRI6;
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uint32_t INTPRI7;
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};
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#define AINTC ((volatile struct aintc_regs_t *) 0x01C48000)
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/* -------------------------------------------------------------------------- *
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* PLL Register structure - See sprue14.pdf, Chapter 6 for more details. *
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* -------------------------------------------------------------------------- */
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struct pll_regs_t {
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uint32_t PID;
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uint32_t RSVD0[56];
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uint32_t RSTYPE; /* 0x0E4 */
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uint32_t RSVD1[6];
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uint32_t PLLCTL; /* 0x100 */
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uint32_t RSVD2[3];
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uint32_t PLLM; /* 0x110 */
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uint32_t RSVD3;
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uint32_t PLLDIV1; /* 0x118 */
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uint32_t PLLDIV2;
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uint32_t PLLDIV3;
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uint32_t RSVD4;
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uint32_t POSTDIV; /* 0x128 */
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uint32_t BPDIV;
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uint32_t RSVD5[2];
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uint32_t PLLCMD; /* 0x138 */
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uint32_t PLLSTAT;
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uint32_t ALNCTL;
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uint32_t DCHANGE;
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uint32_t CKEN;
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uint32_t CKSTAT;
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uint32_t SYSTAT;
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uint32_t RSVD6[3];
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uint32_t PLLDIV4; /* 0x160 - Only on DM35x */
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uint32_t PLLDIV5; /* 0x164 - Only on DM644x */
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};
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#define PLL1 ((volatile struct pll_regs_t *) 0x01C40800)
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#define PLL2 ((volatile struct pll_regs_t *) 0x01C40C00)
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#define DEVICE_PLLCTL_CLKMODE_MASK 0x00000100
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#define DEVICE_PLLCTL_PLLEN_MASK 0x00000001
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#define DEVICE_PLLCTL_PLLPWRDN_MASK 0x00000002
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#define DEVICE_PLLCTL_PLLRST_MASK 0x00000008
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#define DEVICE_PLLCTL_PLLDIS_MASK 0x00000010
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#define DEVICE_PLLCTL_PLLENSRC_MASK 0x00000020
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#define DEVICE_PLLCMD_GOSET_MASK 0x00000001
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#define DEVICE_PLLSTAT_GOSTAT_MASK 0x00000001
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#define DEVICE_PLLDIV_EN_MASK 0x00008000
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#define DEVICE_PLLSTAT_LOCK_MASK 0x00000002
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/* -------------------------------------------------------------------------- *
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* Power/Sleep Ctrl Register structure - See sprue14.pdf, Chapter 7 *
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* for more details. *
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* -------------------------------------------------------------------------- */
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struct psc_regs_t {
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uint32_t PID; // 0x000
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uint32_t RSVD0[3]; // 0x004
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uint32_t GBLCTL; // 0x010 - NOT ON DM35x
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uint32_t RSVD1; // 0x014
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uint32_t INTEVAL; // 0x018
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uint32_t RSVD2[9]; // 0x01C
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uint32_t MERRPR0; // 0x040
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uint32_t MERRPR1; // 0x044
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uint32_t RSVD3[2]; // 0x048
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uint32_t MERRCR0; // 0x050
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uint32_t MERRCR1; // 0x054
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uint32_t RSVD4[2]; // 0x058
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uint32_t PERRPR; // 0x060
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uint32_t RSVD5; // 0x064
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uint32_t PERRCR; // 0x068
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uint32_t RSVD6; // 0x06C
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uint32_t EPCPR; // 0x070
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uint32_t RSVD7; // 0x074
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uint32_t EPCCR; // 0x078
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uint32_t RSVD8[33]; // 0x07C
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uint32_t RAILSTAT; // 0x100 - NOT ON DM35x
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uint32_t RAILCTL; // 0x104 - NOT ON DM35x
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uint32_t RAILSEL; // 0x108 - NOT ON DM35x
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uint32_t RSVD9[5]; // 0x10C
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uint32_t PTCMD; // 0x120
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uint32_t RSVD10; // 0x124
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uint32_t PTSTAT; // 0x128
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uint32_t RSVD11[53]; // 0x12C
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uint32_t PDSTAT0; // 0x200
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uint32_t PDSTAT1; // 0x204
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uint32_t RSVD12[62]; // 0x208
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uint32_t PDCTL0; // 0x300
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uint32_t PDCTL1; // 0x304
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uint32_t RSVD13[134]; // 0x308
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uint32_t MCKOUT0; // 0x520
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uint32_t MCKOUT1; // 0x524
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uint32_t RSVD14[182]; // 0x528
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uint32_t MDSTAT[41]; // 0x800
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uint32_t RSVD15[87]; // 0x8A4
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uint32_t MDCTL[41]; // 0xA00
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};
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#define PSC ((volatile struct psc_regs_t*) 0x01C41000)
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#if defined(DM644x)
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/* See TMS320DM6446 errata 1.3.22 */
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#define PSC_PTSTAT_WORKAROUND_REG (*((volatile uint32_t*) 0x01C41A20))
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#endif
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#define PD0 0
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/* PSC constants */
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#define LPSC_VPSS_MAST 0
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#define LPSC_VPSS_SLV 1
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#define LPSC_EDMACC 2
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#define LPSC_EDMATC0 3
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#define LPSC_EDMATC1 4
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#if defined(DM644x)
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#define LPSC_EMAC 5
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#define LPSC_EMAC_MEM_CTL 6
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#define LPSC_MDIO 7
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#define LPSC_RESERVED0 8
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#elif defined(DM35x)
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#define LPSC_TIMER3 5
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#define LPSC_SPI1 6
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#define LPSC_MMC_SD1 7
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#define LPSC_ASP1 8
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#endif
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#define LPSC_USB 9
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#if defined(DM644x)
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#define LPSC_ATA 10
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#define LPSC_VLYNQ 11
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#define LPSC_HPI 12
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#elif defined(DM35x)
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#define LPSC_PWM3 10
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#define LPSC_SPI2 11
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#define LPSC_RTO 12
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#endif
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#define LPSC_DDR2 13
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#define LPSC_AEMIF 14
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#define LPSC_MMC_SD0 15
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#if defined(DM644x)
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#define LPSC_RESERVED1 16
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#elif defined(DM35x)
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#define LPSC_MEMSTK 16
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#endif
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#define LPSC_ASP0 17
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#define LPSC_I2C 18
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#define LPSC_UART0 19
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#if defined(DM35x)
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#define LPSC_UART1 20
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#define LPSC_UART2 21
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#define LPSC_SPIO 22
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#define LPSC_PWM0 23
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#define LPSC_PWM1 24
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#define LPSC_PWM2 25
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#endif
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#define LPSC_GPIO 26
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#define LPSC_TIMER0 27
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#define LPSC_TIMER1 28
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#if defined(DM35x)
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#define LPSC_TIMER2 29
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#define LPSC_SYSMOD 30
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#endif
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#define LPSC_ARM 31
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#if defined(DM644x)
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#define LPSC_DSP 39
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#define LPSC_IMCOP 40
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#elif defined(DM35x)
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#define LPSC_VPSS_DAC 40
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#endif
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#define EMURSTIE_MASK 0x00000200
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#define PSC_ENABLE 0x3
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#define PSC_DISABLE 0x2
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#define PSC_SYNCRESET 0x1
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#define PSC_SWRSTDISABLE 0x0
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/* -------------------------------------------------------------------------- *
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* DDR2 Memory Ctrl Register structure - See sprue22b.pdf for more details.*
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* -------------------------------------------------------------------------- */
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struct ddr_mem_ctl_regs_t {
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uint32_t RSVD0;
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uint32_t SDRSTAT;
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uint32_t SDBCR;
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uint32_t SDRCR;
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uint32_t SDTIMR;
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uint32_t SDTIMR2;
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#if defined(DM644x)
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uint32_t RSVD1[2];
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#elif defined(DM35x)
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uint32_t RSVD1;
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uint32_t SDBCR2;
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#endif
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uint32_t PBBPR; /* 0x20 */
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uint32_t RSVD2[39];
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uint32_t IRR; /* 0xC0 */
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uint32_t IMR;
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uint32_t IMSR;
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uint32_t IMCR;
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uint32_t RSVD3[5];
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uint32_t DDRPHYCR;
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uint32_t RSVD4[2];
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#if defined(DM644x)
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uint32_t VTPIOCR; /* 0xF0 - In system control module for DM35x */
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#endif
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};
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#define DDR ((volatile struct ddr_mem_ctl_regs_t *) 0x20000000)
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#define DDR_TEST_PATTERN 0xA55AA55A
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#define SDBCR_TIMUNLOCK (1 << 15)
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#if defined(DM644x)
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#define DDRVTPR (*((volatile uint32_t*) 0x01C42030))
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#define DDRPHYCR_DEFAULT 0x50006400 /* Default value with reserved fields */
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#define DDRPHYCR_READLAT_MASK (0x7 << 0)
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#define SDBCR_DEFAULT 0x00130000 /* Default value with reserved fields */
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#elif defined(DM35x)
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#define DDRPHYCR_DEFAULT 0x28006400 /* Default value with reserved fields */
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#define DDRPHYCR_READLAT_MASK (0xF << 0)
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#define SDBCR_DEFAULT 0x00170000 /* Default value with reserved fields */
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#endif
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/* -------------------------------------------------------------------------- *
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* AEMIF Register structure - See sprue20a.pdf for more details. *
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* -------------------------------------------------------------------------- */
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struct emif_regs_t {
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uint32_t ERCSR; // 0x00
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uint32_t AWCCR; // 0x04
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uint32_t SDBCR; // 0x08 - NOT ON DM35x
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uint32_t SDRCR; // 0x0C - NOT ON DM35x
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uint32_t A1CR; // 0x10
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uint32_t A2CR; // 0x14
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uint32_t A3CR; // 0x18 - NOT ON DM35x
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uint32_t A4CR; // 0x1C - NOT ON DM35x
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uint32_t SDTIMR; // 0x20 - NOT ON DM35x
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uint32_t DDRSR; // 0x24 - NOT ON DM35x
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uint32_t DDRPHYCR; // 0x28 - NOT ON DM35x
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uint32_t DDRPHYSR; // 0x2C - NOT ON DM35x
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uint32_t TOTAR; // 0x30 - NOT ON DM35x
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uint32_t TOTACTR; // 0x34 - NOT ON DM35x
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uint32_t DDRPHYID_REV; // 0x38 - NOT ON DM35x
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uint32_t SDSRETR; // 0x3C - NOT ON DM35x
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uint32_t EIRR; // 0x40
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uint32_t EIMR;
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uint32_t EIMSR;
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uint32_t EIMCR;
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uint32_t IOCTRLR; // 0x50 - NOT ON DM35x
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uint32_t IOSTATR; // 0x54 - NOT ON DM35x
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uint32_t RSVD0;
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uint32_t ONENANDCTL; // 0x5C - ONLY ON DM35x
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uint32_t NANDFCR; // 0x60
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uint32_t NANDFSR; // 0x64
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uint32_t RSVD1[2];
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uint32_t NANDF1ECC; // 0x70
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uint32_t NANDF2ECC; // 0x74
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uint32_t NANDF3ECC; // 0x78 - NOT ON DM35x
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uint32_t NANDF4ECC; // 0x7C - NOT ON DM35x
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uint32_t RSVD2; // 0x80
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uint32_t IODFTECR;
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uint32_t IODFTGCR;
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uint32_t RSVD3;
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uint32_t IODFTMRLR; // 0x90
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uint32_t IODFTMRMR; // 0x94
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uint32_t IODFTMRMSBR; // 0x98
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uint32_t RSVD4[5];
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uint32_t MODRNR; // 0xB0
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uint32_t RSVD5[2];
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uint32_t NAND4BITECCLOAD; // 0xBC - ONLY ON DM35x
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uint32_t NAND4BITECC1; // 0xC0 - ONLY ON DM35x
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uint32_t NAND4BITECC2; // 0xC4 - ONLY ON DM35x
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uint32_t NAND4BITECC3; // 0xC8 - ONLY ON DM35x
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uint32_t NAND4BITECC4; // 0xCC - ONLY ON DM35x
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uint32_t NANDERRADD1; // 0xD0 - ONLY ON DM35x
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uint32_t NANDERRADD2; // 0xD4 - ONLY ON DM35x
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uint32_t NANDERRVAL1; // 0xD8 - ONLY ON DM35x
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uint32_t NANDERRVAL2; // 0xDC - ONLY ON DM35x
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};
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#if defined(DM644x)
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#define AEMIF ((volatile struct emif_regs_t *) 0x01E00000)
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#elif defined(DM35x)
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#define AEMIF ((volatile struct emif_regs_t *) 0x01E10000)
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#endif
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/* -------------------------------------------------------------------------- *
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* UART Register structure - See sprue33.pdf for more details. *
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* -------------------------------------------------------------------------- */
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struct uart_regs_t {
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uint32_t RBR;
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uint32_t IER;
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uint32_t IIR;
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uint32_t LCR;
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uint32_t MCR;
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uint32_t LSR;
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uint32_t MSR; /* NOT ON DM35x */
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uint32_t SCR; /* NOT ON DM35x */
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uint32_t DLL;
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uint32_t DLH;
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uint32_t PID1;
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uint32_t PID2;
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uint32_t PWREMU_MGNT;
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};
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#define THR RBR
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#define FCR IIR
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#define UART0 ((volatile struct uart_regs_t *) 0x01C20000)
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#define UART_BCLK_RATIO 16 /* BCLK is 16 times the baudrate */
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#define UART_BAUDRATE 115200
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/* -------------------------------------------------------------------------- *
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* Timer Register structure - See sprue26.pdf for more details. *
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* -------------------------------------------------------------------------- */
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struct timer_regs_t {
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uint32_t PID12;
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uint32_t EMUMGT_CLKSPD;
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uint32_t GPINT_GPEN; // NOT ON DM35x
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uint32_t GPTDAT_GPDIR; // NOT ON DM35x
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uint32_t TIM12;
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uint32_t TIM34;
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uint32_t PRD12;
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uint32_t PRD34;
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uint32_t TCR;
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uint32_t TGCR;
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uint32_t WDTCR;
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uint32_t RSVD1[3]; // 0x2C - ONLY ON DM35x
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uint32_t REL12; // 0x34 - ONLY ON DM35x
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uint32_t REL34; // 0x38 - ONLY ON DM35x
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uint32_t CAP12; // 0x3C - ONLY ON DM35x
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uint32_t CAP34; // 0x40 - ONLY ON DM35x
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uint32_t INTCTL_STAT; // 0x44 - ONLY ON DM35x
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};
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#define TIMER0 ((volatile struct timer_regs_t *) 0x01C21400)
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struct gpio_controller {
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uint32_t dir;
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uint32_t out_data;
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uint32_t set_data;
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uint32_t clr_data;
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uint32_t in_data;
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uint32_t set_rising;
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uint32_t clr_rising;
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uint32_t set_falling;
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uint32_t clr_falling;
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uint32_t intstat;
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};
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#define DAVINCI_GPIO_BASE 0x01C67000
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#define GPIOC ((volatile struct gpio_controller *) DAVINCI_GPIO_BASE)
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int davinci_platform_init(char *version);
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void ddr_vtp_calibration(void);
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void timer0_start(void);
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uint32_t timer0_status(void);
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void timer0_settimeout(uint8_t timeout);
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int timer0_setdefault_timeout(void);
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#endif /* _DAVINCI_H_ */
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