From 8bb73db43ad50db13ebb44aa28ea75ceda57ba52 Mon Sep 17 00:00:00 2001 From: Holger Hans Peter Freyther Date: Wed, 25 Apr 2012 09:19:54 +0200 Subject: [PATCH] sysmobts_v2: Add sysmobts_v2 with runtime detection of DDR/NAND Add the sysmobts_v2 board, move the DDR type detection into the ubl with a fallback for the sysmobts_v1 with the current type of ram. --- Makefile | 15 ++- common.h | 5 + davinci.c | 258 ++++++++++++++++++++++++++++++++++------ ddr.h | 341 ++--------------------------------------------------- dm644x.h | 16 +-- nand.c | 6 + nand.h | 6 +- uart.c | 1 - uartboot.c | 11 +- ubl.lds | 2 +- 10 files changed, 261 insertions(+), 400 deletions(-) diff --git a/Makefile b/Makefile index e639d12..602dccc 100644 --- a/Makefile +++ b/Makefile @@ -28,17 +28,17 @@ LDFLAGS := -Map ubl.map -nostdlib SOURCES := davinci.c uart.c uartboot.c ubl.c util.c gpio.c crc.c # Boards setup +ifeq ($(BOARD),sysmobts_v2) + PLATFORM := DM644x + FLASH_TYPE := FLASH_TYPE_NAND +endif ifeq ($(BOARD),sysmobts_v1) PLATFORM := DM644x FLASH_TYPE := FLASH_TYPE_NAND - DDR_TYPE := MICRON_MT47H32M16BN_3_162MHZ - DDR_SIZE := 0x08000000 # 128MB endif ifeq ($(BOARD),sffsdr) PLATFORM := DM644x FLASH_TYPE := FLASH_TYPE_NAND - DDR_TYPE := MICRON_MT47H32M16BN_3_162MHZ - DDR_SIZE := 0x08000000 # 128MB endif # Generate a config.h file based on the board selected. @@ -48,7 +48,7 @@ ifneq ($(OLDBOARD),$(BOARD)) $(shell echo "$(BOARD)" > config.h) endif -CFLAGS += -D${PLATFORM} -D${FLASH_TYPE} -D$(DDR_TYPE) -Dboard_$(BOARD) +CFLAGS += -D${PLATFORM} -D${FLASH_TYPE} -Dboard_$(BOARD) # Processor type setup # The Instruction and Data accesses are differentiated via accessing different @@ -61,8 +61,7 @@ ifeq ($(PLATFORM),DM644x) DRAM_SIZE := 0x00004000 endif -LDFLAGS += --defsym __DDR_SIZE=$(DDR_SIZE) \ - --defsym __IRAM_SIZE=$(IRAM_SIZE) \ +LDFLAGS += --defsym __IRAM_SIZE=$(IRAM_SIZE) \ --defsym __DRAM_START=$(DRAM_START) \ --defsym __DRAM_SIZE=$(DRAM_SIZE) \ -T ubl.lds @@ -87,7 +86,7 @@ ifneq ($(MAKECMDGOALS),clean) ifndef BOARD all: @echo "You must select a board." - @echo "List of supported boards: sysmobts_v1 sffsdr" + @echo "List of supported boards: sysmobts_v2 sysmobts_v1 sffsdr" @echo "Example:" @echo " make BOARD=sffsdr"; exit 1 else diff --git a/common.h b/common.h index 76d52ac..f364ec6 100644 --- a/common.h +++ b/common.h @@ -41,7 +41,12 @@ /* Define this to write a RAMP into NAND for debugging. */ /* #define NAND_DEBUG_WRITE_RAMP 1 */ +#if defined(board_sysmobts_v2) +#define UBL_VERSION_STR "sysmobts_v2 Loader v1.1.0 (" __DATE__ "-" __TIME__ ")" +#else #define UBL_VERSION_STR "HV-UBL v0.2.11" +#endif + /* Define this for bypassing the ECC check when reading from the NAND. * This is useful for debugging or during development. */ diff --git a/davinci.c b/davinci.c index 0a398b7..2a96c58 100644 --- a/davinci.c +++ b/davinci.c @@ -34,8 +34,157 @@ extern const int8_t lpsc_emurstie_list[]; extern const size_t lpsc_en_list_len; extern const size_t lpsc_emurstie_list_len; +/* Table of supported PLL settings */ +#define PLL_DAVINCI_594_CFG 0 +#define PLL_DAVINCI_810_CFG 1 +static const struct pll_settings_t pll1_settings[] = { + { 22 }, /* DSP=594 MHz ARM=297 MHz */ + { 30 }, /* DSP=810 MHz ARM=405 MHz */ +}; +static const struct pll_settings_t pll2_settings[] = { + { 24 }, /* DDRPHY=324 MHz DDRCLK=162 MHz */ + { 28 }, /* DDRPHY=378 MHz DDRCLK=189 MHz */ +}; + +/* Table of supported DDR devices */ +#define DDR_MT47H32M16BN_3_162MHz_CFG 0 +#define DDR_MT47H64M16HR_3IT_162MHz_CFG 1 +#define DDR_MT47H64M16HR_3IT_189MHz_CFG 2 +static const struct ddr_timing_infos_t ddr_timing_infos[] = { + { + /* Micron MT47H32M16BN-3 @ 162 MHz settings: + * TCK = 6.17 nS -> 1 / 162 MHz + * T_REF = 7.8 uS (varies with commercial vs industrial) + * T_RFC = 105 nS (varies with capacity) + * T_RP = 15 nS + * T_RCD = 15 nS + * T_WR = 15 nS + * T_RAS = 40 nS + * T_RASMAX = 70 uS + * T_RTP = 7.5 nS + * T_RC = 55 nS + * T_RRD = 10 nS + * T_WTR = 7.5 nS + * T_XSRD = 200 nS + * T_XSNR = 115 nS -> T_RFC(MIN) + 10 + * T_CKE = 3 TCK + * T_XP = 2 TCK + */ + .SDBCR = SDBCR_DEFAULT + | (0 << 14) /* NM = 0; {32-bit bus with} */ + | (3 << 9) /* CL = 3; */ + | (2 << 4) /* IBANK = 2; {4 banks} */ + | (2 << 0), /* PAGESIZE = 2; {1024-word} */ + + .SDTIMR = (16 << 25) /* T_RFC = 16; {(T_RFC * DDRCLK) - 1} */ + | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ + | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ + | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ + | ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */ + | ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */ + | ( 1 << 3) /* T_RRD = 1; {(T_RRD * DDRCLK) - 1} */ + | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ + + .SDTIMR2 = ( 18 << 16) /* T_XSNR = 18; {(T_XSNR * DDRCLK) - 1} */ + | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ + | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ + | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ + + .SDRCR = 1265, /* RR = 1265; {DDRCLK * T_REF} */ + + .READ_Latency = 4, + }, + { + /* Micron MT47H64M16HR-3IT @ 162 MHz settings: + * TCK = 6.17 nS -> 1 / 162 MHz + * T_REF = 3.9 uS (varies with commercial vs industrial) + * T_RFC = 127.5 nS (varies with capacity) + * T_RP = 15 nS + * T_RCD = 15 nS + * T_WR = 15 nS + * T_RAS = 40 nS + * T_RASMAX = 70 uS + * T_RTP = 7.5 nS + * T_RC = 55 nS + * T_RRD = 10 nS + * T_WTR = 7.5 nS + * T_XSRD = 200 nS + * T_XSNR = 138 nS -> T_RFC(MIN) + 10 + * T_CKE = 3 TCK + * T_XP = 2 TCK + */ + .SDBCR = SDBCR_DEFAULT + | (0 << 14) /* NM = 0; {32-bit bus with} */ + | (3 << 9) /* CL = 3; */ + | (3 << 4) /* IBANK = 3; {8 banks} */ + | (2 << 0), /* PAGESIZE = 2; {1024-word} */ + + .SDTIMR = (20 << 25) /* T_RFC = 20; {(T_RFC * DDRCLK) - 1} */ + | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ + | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ + | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ + | ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */ + | ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */ + | ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */ + | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ + + .SDTIMR2 = ( 32 << 16) /* T_XSNR = 32; {(T_XSNR * DDRCLK) - 1} */ + | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ + | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ + | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ + + .SDRCR = 632, /* RR = 632; {DDRCLK * T_REF} */ + + .READ_Latency = 4, + }, + { + /* Micron MT47H64M16HR-3IT @ 189 MHz settings: + * TCK = 5.291 nS -> 1 / 189 MHz + * T_REF = 3.9 uS (varies with commercial vs industrial) + * T_RFC = 127.5 nS (varies with capacity) + * T_RP = 15 nS + * T_RCD = 15 nS + * T_WR = 15 nS + * T_RAS = 40 nS + * T_RASMAX = 70 uS + * T_RTP = 7.5 nS + * T_RC = 55 nS + * T_RRD = 10 nS + * T_WTR = 7.5 nS + * T_XSRD = 200 nS + * T_XSNR = 138 nS -> T_RFC(MIN) + 10 + * T_CKE = 3 TCK + * T_XP = 2 TCK + */ + .SDBCR = SDBCR_DEFAULT + | (0 << 14) /* NM = 0; {32-bit bus with} */ + | (3 << 9) /* CL = 3; */ + | (3 << 4) /* IBANK = 3; {8 banks} */ + | (2 << 0), /* PAGESIZE = 2; {1024-word} */ + + .SDTIMR = (24 << 25) /* T_RFC = 24; {(T_RFC * DDRCLK) - 1} */ + | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */ + | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */ + | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */ + | ( 7 << 11) /* T_RAS = 7; {(T_RAS * DDRCLK) - 1} */ + | (10 << 6) /* T_RC = 10; {(T_RC * DDRCLK) - 1} */ + | ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */ + | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */ + + .SDTIMR2 = ( 26 << 16) /* T_XSNR = 26; {(T_XSNR * DDRCLK) - 1} */ + | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */ + | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */ + | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */ + + .SDRCR = 738, /* RR = 738; {DDRCLK * T_REF} */ + + .READ_Latency = 4, + } +}; + /* Symbol from linker script */ extern uint32_t __DDR_START; +uint32_t DDR_SIZE = (128 << 20); static void pinmuxControl(uint32_t regOffset, uint32_t mask, uint32_t value) @@ -247,7 +396,7 @@ pll_init(volatile struct pll_regs_t *pll, int pll_mult, int plldiv_ratio[5]) } static int -pll1_init(void) +pll1_init(int cfg) { int plldiv_ratio[5]; @@ -264,12 +413,12 @@ pll1_init(void) /* Calculate PLL divider ratio for divider 3 (feeds VPBE) */ plldiv_ratio[2] = 0; while ((plldiv_ratio[2] * VPBE_CLK_HZ) < - (SYSTEM_CLK_HZ * (PLL1_Mult >> 3))) + (SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3))) plldiv_ratio[2]++; /* Check to make sure we can supply accurate VPBE clock */ if ((plldiv_ratio[2] * VPBE_CLK_HZ) != - (SYSTEM_CLK_HZ * (PLL1_Mult >> 3))) + (SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3))) return E_FAIL; /* See the device datasheet for more info (must be 2 or 4) */ @@ -277,11 +426,11 @@ pll1_init(void) plldiv_ratio[4] = -1; /* PLLDIV5 not used */ #endif - return pll_init(PLL1, PLL1_Mult, plldiv_ratio); + return pll_init(PLL1, pll1_settings[cfg].mult, plldiv_ratio); } static int -pll2_init(void) +pll2_init(int cfg) { int plldiv_ratio[5]; @@ -291,17 +440,17 @@ pll2_init(void) plldiv_ratio[3] = -1; /* PLLDIV4 not used */ plldiv_ratio[4] = -1; /* PLLDIV5 not used */ - return pll_init(PLL2, PLL2_Mult, plldiv_ratio); + return pll_init(PLL2, pll2_settings[cfg].mult, plldiv_ratio); } static void -ddr_timing_setup(void) +ddr_timing_setup(int cfg) { /* The configuration of DDRPHYCR is not dependent on the DDR2 device * specification but rather on the board layout. * Setup the read latency and clear DLLPWRDN */ DDR->DDRPHYCR = DDRPHYCR_DEFAULT | - (DDR_READ_Latency & DDRPHYCR_READLAT_MASK); + (ddr_timing_infos[cfg].READ_Latency & DDRPHYCR_READLAT_MASK); /* * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) @@ -314,37 +463,17 @@ ddr_timing_setup(void) DDR->PBBPR = DDR_PBBPR_PR_OLD_COUNT; /* TIMUNLOCK (unlocked), CAS Latency, number of banks and page size */ - DDR->SDBCR = SDBCR_DEFAULT | - SDBCR_TIMUNLOCK | - (DDR_NM << 14) | - (DDR_CL << 9) | - (DDR_IBANK << 4) | - (DDR_PAGESIZE << 0); + DDR->SDBCR = SDBCR_TIMUNLOCK | ddr_timing_infos[cfg].SDBCR; /* Program timing registers */ - DDR->SDTIMR = (DDR_T_RFC << 25) | - (DDR_T_RP << 22) | - (DDR_T_RCD << 19) | - (DDR_T_WR << 16) | - (DDR_T_RAS << 11) | - (DDR_T_RC << 6) | - (DDR_T_RRD << 3) | - (DDR_T_WTR << 0); - - DDR->SDTIMR2 = (DDR_T_XSNR << 16) | - (DDR_T_XSRD << 8) | - (DDR_T_RTP << 5) | - (DDR_T_CKE << 0); -#if defined(DM35x) - DDR->SDTIMR2 |= (DDR_T_RASMAX << 27) | - (DDR_T_XP << 25); -#endif + DDR->SDTIMR = ddr_timing_infos[cfg].SDTIMR; + DDR->SDTIMR2 = ddr_timing_infos[cfg].SDTIMR2; /* Clear the TIMUNLOCK bit (locked) */ DDR->SDBCR &= ~SDBCR_TIMUNLOCK; /* Set the refresh rate */ - DDR->SDRCR = DDR_RR; + DDR->SDRCR = ddr_timing_infos[cfg].SDRCR; } static void @@ -357,7 +486,7 @@ ddr_reset(void) } static int -ddr_init(void) +ddr_init(int cfg) { volatile uint32_t *ddr_start = &__DDR_START; /* For reading/writing dummy value in order to apply timing settings */ @@ -371,7 +500,7 @@ ddr_init(void) ddr_reset(); #endif - ddr_timing_setup(); + ddr_timing_setup(cfg); /* Dummy read to apply timing settings */ ddr_dummy_read = ddr_start[0]; @@ -450,7 +579,10 @@ psc_init(void) int davinci_platform_init(char *version) { + int pllCfg; + int ddrCfg; int status = E_PASS; + unsigned *gpio01 = (unsigned *)(DAVINCI_GPIO_BASE + 0x20); psc_init(); @@ -482,8 +614,48 @@ davinci_platform_init(char *version) pinmuxControl(4, 0xFFFFFFFF, PINMUX4_DEFAULT); #endif + /* Init board configuration */ +#if defined(board_sysmobts_v2) + char boardVer; + char boardCfg; + boardCfg = (*gpio01 >> 10) & 0x001F; + boardVer = (*gpio01 >> 15) & 0x0007; + if ( (boardVer == 1) && ((boardCfg == 0x02) || (boardCfg == 0x04) || (boardCfg == 0x05)) ) + { + /* Davinci @ 405/810 MHz */ + pllCfg = PLL_DAVINCI_810_CFG; + + /* Micron MT47H64M16HR-3IT @ 189 MHz */ + ddrCfg = DDR_MT47H64M16HR_3IT_189MHz_CFG; + } + else if ( (boardVer == 0) && (boardCfg != 0x00) ) + { + DDR_SIZE = (256 << 20); + + /* Davinci @ 297/594 MHz */ + pllCfg = PLL_DAVINCI_594_CFG; + + /* Micron MT47H32M16BN-3 @ 162 MHz */ + ddrCfg = DDR_MT47H64M16HR_3IT_162MHz_CFG; + } + else +#endif + { +#if defined(board_sysmobts_v2) + DDR_SIZE = (256 << 20); +#else + DDR_SIZE = (128 << 20); +#endif + + /* Davinci @ 297/594 MHz */ + pllCfg = PLL_DAVINCI_594_CFG; + + /* Micron MT47H32M16BN-3 @ 162 MHz */ + ddrCfg = DDR_MT47H32M16BN_3_162MHz_CFG; + } + if (status == E_PASS) - status |= pll1_init(); + status |= pll1_init(pllCfg); if (status == E_PASS) status |= uart0_init(); @@ -494,11 +666,21 @@ davinci_platform_init(char *version) uart_send_lf(); log_info(version); - if (status == E_PASS) - status |= pll2_init(); +#if defined(board_sysmobts_v2) + char str[4]; + uart_send_str("Board revision: "); + str[0] = 'A' + boardVer; + str[1] = '.'; + str[2] = '0' + boardCfg; + str[3] = '\0'; + uart_send_str_lf(str); +#endif if (status == E_PASS) - status |= ddr_init(); + status |= pll2_init(pllCfg); + + if (status == E_PASS) + status |= ddr_init(ddrCfg); #ifdef STATUS_LED gpio_direction_out(STATUS_LED, 1); diff --git a/ddr.h b/ddr.h index 00eae70..16cfd69 100644 --- a/ddr.h +++ b/ddr.h @@ -26,339 +26,12 @@ #include -#if defined(MICRON_MT47H32M16BN_3_171MHZ) -/* Micron MT47H32M16BN-3 @ 171 MHz settings: - * TCK = 5.85 nS -> 1 / 171MHz - * T_REF = 7.8 uS (varies with commercial vs industrial) - * T_RFC = 105 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 115 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 2; /* 4 banks. */ -static const uint16_t DDR_RR = 1336; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 17; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 8; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 19; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H32M16BN_3_162MHZ) /* SFFSDR */ -/* Micron MT47H32M16BN-3 @ 162 MHz settings: - * TCK = 6.17 nS -> 1 / 162 MHz - * T_REF = 7.8 uS (varies with commercial vs industrial) - * T_RFC = 105 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 115 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 2; /* 4 banks. */ -static const uint16_t DDR_RR = 1265; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 16; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 8; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 18; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H64M16BT_37E_171MHZ) /* EVM DM355 */ -/* Micron MT47H64M16BT-37E @ 171 MHz */ -static const uint8_t DDR_IBANK = 3; /* 8 banks. */ -static const uint16_t DDR_RR = 1336; -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 21; -static const uint8_t DDR_T_RP = 2; -static const uint8_t DDR_T_RCD = 2; -static const uint8_t DDR_T_WR = 2; -static const uint8_t DDR_T_RAS = 6; -static const uint8_t DDR_T_RC = 9; -static const uint8_t DDR_T_RRD = 1; -static const uint8_t DDR_T_WTR = 1; -static const uint8_t DDR_T_RASMAX = 7; -static const uint8_t DDR_T_XP = 2; -static const uint8_t DDR_T_XSNR = 23; -static const uint8_t DDR_T_XSRD = 199; -static const uint8_t DDR_T_RTP = 3; -static const uint8_t DDR_T_CKE = 3; -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H64M16HR_3_162MHZ) /* DAS Commercial */ -/* Micron MT47H64M16HR-3 @ 162 MHz settings: - * TCK = 6.17 nS -> 1 / 162 MHz - * T_REF = 7.8 uS (varies with commercial vs industrial) - * T_RFC = 127.5 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 138 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 3; /* 8 banks. */ -static const uint16_t DDR_RR = 1265; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 20; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 2; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 8; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 21; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H64M16HR_3IT_162MHZ) /* DAS industrial */ -/* Micron MT47H64M16HR-3IT @ 162 MHz settings: - * TCK = 6.17 nS -> 1 / 162 MHz - * T_REF = 3.9 uS (varies with commercial vs industrial) - * T_RFC = 127.5 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 138 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 3; /* 8 banks. */ -static const uint16_t DDR_RR = 635; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 20; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 8; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 2; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 15; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 21; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H64M16BT_3_162MHZ) -/* Micron MT47H64M16HR-3IT @ 162 MHz settings: - * TCK = 5.85 nS -> 1 / 162 MHz - * T_REF = 3.9 uS (varies with commercial vs industrial) - * T_RFC = 198 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 208 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 3; /* 8 banks. */ -static const uint16_t DDR_RR = 667; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 33; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 15; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 34; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#elif defined(MICRON_MT47H128M16HG_3IT_171MHZ) -/* Micron MT47H128M16HG-3IT @ 171 MHz settings: - * TCK = 5.85 nS -> 1 / 171MHz - * T_REF = 3.9 uS (varies with commercial vs industrial) - * T_RFC = 198 nS (varies with capacity) - * T_RP = 15 nS - * T_RCD = 15 nS - * T_WR = 15 nS - * T_RAS = 40 nS - * T_RASMAX = 70 uS - * T_RTP = 7.5 nS - * T_RC = 55 nS - * T_RRD = 10 nS - * T_WTR = 7.5 nS - * T_XSRD = 200 nS - * T_XSNR = 208 nS -> T_RFC(MIN) + 10 - * T_CKE = 3 TCK - * T_XP = 2 TCK - */ -static const uint8_t DDR_IBANK = 3; /* 8 banks. */ -static const uint16_t DDR_RR = 667; /* DDRCLK * T_REF */ -static const uint8_t DDR_CL = 3; -static const uint8_t DDR_T_RFC = 33; /* (T_RFC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */ -static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */ -static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */ -static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */ -static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */ -/* - * Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories - * with less than 8 banks the T_RRD field should be calculated using: - * (T_RRD * DDRCLK) - 1. - */ -static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */ -static const uint8_t DDR_T_RASMAX = 15; /* - * (T_RASMAX(uS) / T_REF) - 1 - * Should be 17 but max. value - * is 15 (4 bits) - */ -static const uint8_t DDR_T_XP = 2; /* - * If T_XP > T_CKE then - * T_XP = T_XP - 1 - * else - * T_XP = T_CKE - 1 - */ -static const uint8_t DDR_T_XSNR = 34; /* (T_XSNR * DDRCLK) - 1 */ -static const uint8_t DDR_T_XSRD = 199; /* T_XSRD - 1 */ -static const uint8_t DDR_T_RTP = 1; /* (T_RTP * DDRCLK) - 1 */ -static const uint8_t DDR_T_CKE = 2; /* T_CKE - 1 */ -static const uint8_t DDR_READ_Latency = 4; /* Board specific */ - -#endif +struct ddr_timing_infos_t { + uint32_t SDBCR; + uint32_t SDTIMR; + uint32_t SDTIMR2; + uint32_t SDRCR; + uint8_t READ_Latency; +}; #endif /* _DDDR_H_ */ diff --git a/dm644x.h b/dm644x.h index 511d202..04de9f2 100644 --- a/dm644x.h +++ b/dm644x.h @@ -28,17 +28,13 @@ #define SYSTEM_CLK_HZ 27000000 -#define PLL1_Mult 22 /* DSP=594 MHz ARM=297 MHz */ +struct pll_settings_t { + uint8_t mult; +}; +#define PLL2_Div1 12 +#define PLL2_Div2 2 -#define PLL2_Mult 24 /* DDRPHY=324 MHz DDRCLK=162 MHz */ -#define PLL2_Div1 12 -#define PLL2_Div2 2 - -#define UBL_IMAGE_SIZE 0x3800 /* 14 kB UBL (2Kb reserved for RBL stack) */ - -/* Global Memory Timing and PLL Settings */ -static const uint8_t DDR_NM = 0; /* 32-bit bus width by default. */ -static const uint8_t DDR_PAGESIZE = 2; /* 1024-word page size. */ +#define UBL_IMAGE_SIZE 0x3000 /* 12 kB UBL */ /* * See TMS320DM6446 errata 2.1.2: diff --git a/nand.c b/nand.c index bede077..f708a5f 100644 --- a/nand.c +++ b/nand.c @@ -973,3 +973,9 @@ nand_get_bytes_per_page(void) { return nand_info.bytes_per_page; } + +int +nand_get_bytes_per_block(void) +{ + return nand_info.pages_per_block * nand_info.bytes_per_page; +} diff --git a/nand.h b/nand.h index e1d3165..8fa1c37 100644 --- a/nand.h +++ b/nand.h @@ -29,8 +29,8 @@ /* Define which blocks are valid for writing UBL and APP data */ #define START_UBL_BLOCK_NUM 1 -#define END_UBL_BLOCK_NUM 5 -#define START_APP_BLOCK_NUM 6 +#define END_UBL_BLOCK_NUM (START_APP_BLOCK_NUM - 1) +#define START_APP_BLOCK_NUM ((nand_get_bytes_per_block() == 16384) ? 32 : 4) #define MAX_PAGE_SIZE (2048+64) /* Data bytes + spare area */ @@ -61,4 +61,6 @@ int nand_get_pages_per_block(void); int nand_get_bytes_per_page(void); +int nand_get_bytes_per_block(void); + #endif /* _NAND_H_ */ diff --git a/uart.c b/uart.c index e58b514..f14fbfd 100644 --- a/uart.c +++ b/uart.c @@ -29,7 +29,6 @@ /* Symbol from linker script */ extern uint32_t __DDR_FREE; /* Start of free DDR memory region. */ -extern uint32_t __DDR_END; /* Last DDR memory address. */ /* Receive data from UART */ static int diff --git a/uartboot.c b/uartboot.c index f0437c0..2ce0b32 100644 --- a/uartboot.c +++ b/uartboot.c @@ -34,23 +34,22 @@ /* Symbols from linker script */ extern uint32_t __DDR_START; -extern uint32_t __DDR_SIZE; +extern uint32_t DDR_SIZE; static int ddr_memory_test(void) { int k; volatile uint32_t *ddr_start = &__DDR_START; - const uint32_t ddr_size32 = ((uint32_t) &__DDR_SIZE) / 4; uint32_t read32; log_info("DDR tests"); log_info("1. RAMP test:"); - for (k = 0; k < ddr_size32; k++) + for (k = 0; k < DDR_SIZE/4; k++) ddr_start[k] = k; /* Write */ - for (k = 0; k < ddr_size32; k++) { + for (k = 0; k < DDR_SIZE/4; k++) { read32 = ddr_start[k]; /* Read */ if (read32 != k) goto error; @@ -58,10 +57,10 @@ ddr_memory_test(void) log_info(" Success"); log_info("2. PATTERN test:"); - for (k = 0; k < ddr_size32; k++) + for (k = 0; k < DDR_SIZE/4; k++) ddr_start[k] = DDR_TEST_PATTERN; /* Write */ - for (k = 0; k < ddr_size32; k++) { + for (k = 0; k < DDR_SIZE/4; k++) { read32 = ddr_start[k]; /* Read */ if (read32 != DDR_TEST_PATTERN) goto error; diff --git a/ubl.lds b/ubl.lds index f6af652..352946f 100644 --- a/ubl.lds +++ b/ubl.lds @@ -99,5 +99,5 @@ SECTIONS { *(.ddrram) } __DDR_FREE = .; - __DDR_END = __DDR_START + __DDR_SIZE - 1; + /*__DDR_END = __DDR_START + __DDR_SIZE - 1;*/ }