Browse Source

dvnixload/ubl copy as of pre 0.2.6 svn

master
Holger Hans Peter Freyther 10 years ago
commit
4b779cf0d2
  1. 18
      ChangeLog
  2. 201
      Makefile
  3. 21
      README
  4. 7
      TODO
  5. 76
      board.h
  6. 98
      common.h
  7. 78
      crc.c
  8. 34
      crc.h
  9. 528
      davinci.c
  10. 463
      davinci.h
  11. 364
      ddr.h
  12. 121
      dm35x.c
  13. 64
      dm35x.h
  14. 113
      dm644x.c
  15. 87
      dm644x.h
  16. 91
      gpio.c
  17. 40
      gpio.h
  18. 868
      gunzip.c
  19. 30
      gunzip.h
  20. 975
      nand.c
  21. 64
      nand.h
  22. 125
      nandboot.c
  23. 1187
      nor.c
  24. 44
      nor.h
  25. 72
      norboot.c
  26. 287
      uart.c
  27. 48
      uart.h
  28. 261
      uartboot.c
  29. 251
      ubl.c
  30. 103
      ubl.lds
  31. 83
      util.c
  32. 35
      util.h

18
ChangeLog

@ -0,0 +1,18 @@
v0.2.3
Mini-DAS: Enable DSP1 & DSP2 power.
v0.2.4
Mini-DAS: Enable DSP1 & DSP2 power.
Deactivate DSP1 & DSP2 reset lines.
v0.2.5
Mini-DAS: Enable all power supplys and deactivate
all peripheral reset lines.
v0.2.6
Mini-DAS: Add delay after applying DSP power and
before releasing DSP reset lines.
v0.2.7
Mini-DAS: Open-drain output for CAMERA RESET.

201
Makefile

@ -0,0 +1,201 @@
#
# Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
ifndef CROSS_COMPILE
CROSS_COMPILE=arm-linux-
endif
.PHONY : clean check
CC=$(CROSS_COMPILE)gcc
LD=$(CROSS_COMPILE)ld
CFLAGS := -c -Os -Wall
LDFLAGS := -Map ubl.map -nostdlib
SOURCES := davinci.c uart.c uartboot.c ubl.c util.c gpio.c crc.c gunzip.c
# Boards setup
ifeq ($(BOARD),dvevm)
# EVM for DM6446
PLATFORM := DM644x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H64M16BT_3_162MHZ
DDR_SIZE := 0x10000000 # 256MB
endif
ifeq ($(BOARD),sffsdr)
PLATFORM := DM644x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H32M16BN_3_162MHZ
DDR_SIZE := 0x08000000 # 128MB
endif
ifeq ($(BOARD),das)
PLATFORM := DM644x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H64M16HR_3_162MHZ
DDR_SIZE := 0x10000000 # 256MB
endif
ifeq ($(BOARD),minidas)
PLATFORM := DM35x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H128M16HG_3IT_171MHZ
DDR_SIZE := 0x10000000 # 256MB
endif
ifeq ($(BOARD),afeusb)
PLATFORM := DM35x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H32M16BN_3_171MHZ
DDR_SIZE := 0x04000000 # 64MB
endif
ifeq ($(BOARD),dm355evm)
PLATFORM := DM35x
FLASH_TYPE := FLASH_TYPE_NAND
DDR_TYPE := MICRON_MT47H64M16BT_37E_171MHZ
DDR_SIZE := 0x08000000 # 128MB
endif
ifeq ($(BOARD),nor)
# Only for testing NOR flash compilation
PLATFORM := DM35x
FLASH_TYPE := FLASH_TYPE_NOR
DDR_TYPE := MICRON_MT47H64M16BT_37E_171MHZ
DDR_SIZE := 0x08000000 # 128MB
endif
# Generate a config.h file based on the board selected.
# Only update this file if the selected board is different.
OLDBOARD = $(shell cat config.h 2> /dev/null | grep "$(BOARD)")
ifneq ($(OLDBOARD),$(BOARD))
$(shell echo "$(BOARD)" > config.h)
endif
CFLAGS += -D${PLATFORM} -D${FLASH_TYPE} -D$(DDR_TYPE) -Dboard_$(BOARD)
# Processor type setup
# The Instruction and Data accesses are differentiated via accessing different
# memory map regions. The instruction region at 0x0000 and data region at
# 0x8000 (0x10000 for DM35x) map to the same physical TCM RAM.
ifeq ($(PLATFORM),DM644x)
SOURCES += dm644x.c
IRAM_SIZE := 0x00004000
DRAM_START := 0x00008000
DRAM_SIZE := 0x00004000
endif
ifeq ($(PLATFORM),DM35x)
SOURCES += dm35x.c
IRAM_SIZE := 0x00008000
DRAM_START := 0x00010000
DRAM_SIZE := 0x00008000
endif
LDFLAGS += --defsym __DDR_SIZE=$(DDR_SIZE) \
--defsym __IRAM_SIZE=$(IRAM_SIZE) \
--defsym __DRAM_START=$(DRAM_START) \
--defsym __DRAM_SIZE=$(DRAM_SIZE) \
-T ubl.lds
# NAND flash setup
ifeq ($(FLASH_TYPE),FLASH_TYPE_NAND)
SOURCES += nandboot.c nand.c
endif
ifeq ($(FLASH_TYPE),FLASH_TYPE_NOR)
SOURCES += norboot.c nor.c
endif
OBJECTS := $(patsubst %.c,%.o,$(SOURCES))
EXECUTABLE := ubl.elf
BINARY := $(EXECUTABLE)
DEPS_DIR := .deps
# Creation of the dependencies directory
$(shell mkdir -p $(DEPS_DIR))
ifneq ($(MAKECMDGOALS),clean)
ifndef BOARD
all:
@echo "You must select a board."
@echo "List of supported boards: evmdm6446 sffsdr das minidas afeusb evmdm355"
@echo "Example:"
@echo " make BOARD=sffsdr"; exit 1
else
ifndef PLATFORM
all:
@echo "Invalid board"; exit 1
else
all: $(BINARY)
endif
endif
endif
# Including the dependency files (except during clean rules, so Make won't
# create them only to immediately remove them again). Each one of them will
# become a target in this Makefile (that is why the 'include' command must be
# placed after the 'all' target). If a dependency file is not found or is out
# of date, it is built or updated.
# If any have actually been changed, Make restarts with a clean state and
# reads all the dependency makefiles over again.
ifneq ($(MAKECMDGOALS),clean)
ifneq "$(SOURCES)" ""
ifdef BOARD
-include $(patsubst %.c,$(DEPS_DIR)/%.d,$(SOURCES))
endif
endif
endif
clean:
-@rm -f -v *.o $(EXECUTABLE)
-@rm -f -v *.map
-@rm -f -v *~
-@rm -f -v config.h
-@rm -f -r $(DEPS_DIR)
check:
-@checkpatch.pl --no-tree --file *.c *.h | more
$(EXECUTABLE): $(OBJECTS)
$(LD) $(LDFLAGS) $(OBJECTS) -o $@
# Any source files depend on automatically generated config.h.
# This is necessary to recompile everything when we change boards.
*.o: config.h $(LINKERSCRIPT)
# The preprocessor of the compiler is used to generate a string representing
# the dependencies of the input file. This is done invoking the compiler with
# the -MM option (like -M but omit system header files). The purpose of the
# sed script is to add the name of the dependency file (.d) to the string
# returned by the preprocessor, like in the following example:
# "main.o: main.c main.h" would become "main.o main.d: main.c main.h"
# The MAKE '$*' automatic variable represents the stem with which an implicit
# rule match. This would be 'main' in the above example.
#
# Use of the $(SHELL) function: Double quotes must be used to surround the
# command.
#
# In MAKE, using '$$' will produce a single dollar sign. When using only '$',
# MAKE tries to expand the variable following the dollar sign. Additionally,
# and for an obscure reason, '$1' must be preceded by a backslash on the
# command line. This is why '\$$1' is used in the command line of the shell to
# be seen as '$1' by the PERL script.
#
# The `-e' flag to the shell makes it exit immediately if the $(CC) command
# fails (exits with a nonzero status). Normally the shell exits with the
# status of the last command in the pipeline (sed in this case), so make would
# not notice a nonzero status from the compiler.
$(DEPS_DIR)/%.d: %.c
@echo "Generating dependencies for $<"
@$(SHELL) -ec '$(CC) -MM $(CPPFLAGS) $< | \
sed '\''s/\($*\)\.o[ :]*/\1.o $(DEPS_DIR)\/$*.d : /g'\'' > $@; \
[ -s $@ ] || rm -f $@'

21
README

@ -0,0 +1,21 @@
README for HVUBL
This UBL can be used for flashing itself and a 2nd stage bootloader (usually
U-boot) in flash memory.
It can also be used to flash an arbitrary data image into flash, without
a header.
It can also be used to run DDR RAM memory testing.
To compile HVUBL for the sffsdr board, for example, run:
$> make BOARD=sffsdr
The Makefile honors the CROSS_COMPILE environment variable to specify the prefix
of your ARM gcc toolchain. If it is not set, it defaults to:
CROSS_COMPILE=arm-linux-
You can override it like this, for example:
$> make CROSS_COMPILE=arm-angstrom-linux-gnueabi- BOARD=sffsdr
The output file, in ARM ELF format, will be named <ubl.elf>

7
TODO

@ -0,0 +1,7 @@
TODO
-Define DDR bus width and number of banks for each board.
-NAND write & read page: do bound checking on
block number < maximum number of blocks.
-When writing something other than UBL, use
Linux and U-Boot standard ECC layout.

76
board.h

@ -0,0 +1,76 @@
/*
* board.h - board definitions
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#include "common.h"
#include "davinci.h"
#if defined(board_dvevm)
# define PINMUX1_DEFAULT PINMUX1_UART0
#elif defined(board_sffsdr)
# define PINMUX1_DEFAULT PINMUX1_UART0 | PINMUX1_UART1 | PINMUX1_I2C | \
PINMUX1_ASP
#elif defined(board_das)
# define PINMUX0_DEFAULT PINMUX0_VLYNQEN | VLYNQ_WIDTH_4
# define PINMUX1_DEFAULT PINMUX1_UART0 | PINMUX1_UART2 | PINMUX1_I2C | \
PINMUX1_SPI
#elif defined(board_dm355evm)
# define PINMUX0_DEFAULT 0x00007F55 /* All Video Inputs */
# define PINMUX1_DEFAULT 0x00145555 /* All Video Outputs */
# define PINMUX2_DEFAULT 0x00000004 /* EMIFA */
# define PINMUX3_DEFAULT 0x1BFF55FF /* SPI0, SPI1, UART1, I2C, SD0, SD1,
* ASP0, CLKOUTs */
# define PINMUX4_DEFAULT 0x00000000 /* MMC/SD0 instead of MS, SPI0 */
#elif defined(board_minidas)
# define PINMUX0_DEFAULT 0x00005C00 /* 8-bits video input, rest is GPIOs. */
# define PINMUX1_DEFAULT 0x00430000 /* All GPIOs (temporary: no PWM1 for buzzer) */
# define PINMUX2_DEFAULT 0x00000C0A /* EMIF A3:13, CE0 & CE1. */
# define PINMUX3_DEFAULT 0x0B7BAAC0 /* SPI0, SPI1, UART1, UART2, I2C, SD0,
* CLKOUT1, CLKOUT2 */
# define PINMUX4_DEFAULT 0x00000001 /* MMC/SD0 + SPI0_SDI */
/* Optional GPIO used as a status LED. Make sure to enable the corresponding
* PINMUX bit. */
#define STATUS_LED GPIO(71)
#define DSP1_PWR_ENA GPIO(95)
#define DSP2_PWR_ENA GPIO(94)
#define HDD_ENA GPIO(96)
#define FULL_ENA GPIO(68)
#define ALCOHOL_ENA GPIO(73)
#define CAMERA_RESETn GPIO(72)
#define FAN GPIO(81)
#define BUZZER GPIO(80)
#define WIFI_RESETn GPIO(79)
#define GPS_RESETn GPIO(78)
#define CAN_RESETn GPIO(77)
#define ATA_RESETn GPIO(76)
#endif
#endif /* _BOARD_H_ */

98
common.h

@ -0,0 +1,98 @@
/*
* common.h - common definitions
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef _COMMON_H_
#define _COMMON_H_
#include <stdint.h>
#include <stdbool.h>
#include <string.h> /* For size_t */
#include "board.h"
/* Return types */
#define E_PASS 0
#define E_FAIL 1
#define E_TIMEOUT 2
/* Define this to have more verbose NAND debug messages */
/* #define NAND_DEBUG 1 */
/* Define this to write a RAMP into NAND for debugging. */
/* #define NAND_DEBUG_WRITE_RAMP 1 */
#define UBL_VERSION_STR "HV-UBL v0.2.11"
/* Define this for bypassing the ECC check when reading from the NAND.
* This is useful for debugging or during development. */
#define NAND_BYPASS_READ_PAGE_ECC_CHECK 1
#define MAGIC_NUMBER_MASK 0xFFFFFF00
#define MAGIC_NUMBER_VALID 0xA1ACED00
/* RBL magic numbers */
#define RBL_MAGIC_SAFE 0xA1ACED00 /* Describes UBL flash image type for
* RBL. */
/* UBL magic numbers */
#define UBL_MAGIC_BIN_IMG 0xA1ACED66 /* Describes binary flash image type
* for UBL. */
#define UBL_MAGIC_GZIP_IMG 0xA1ACED77 /* Describes gzipped binary flash
* image type for UBL. */
/* UBL commands */
#define UBL_CMD_FLASH_UBL_APP 0xA1ACEDCC /* Download UBL & application via
* UART and burn in flash. */
#define UBL_CMD_FLASH_DATA 0xA1ACEDCD /* Download data via UART and
* burn in flash (no header in flash). */
#define UBL_CMD_FLASH_ERASE 0xA1ACEDCE /* Erase the whole flash. */
#define UBL_CMD_RUN_APP 0xA1ACEDDD /* Load and run application via UART. */
#define UBL_CMD_DDR_TEST 0xA1ACEDEE /* Test DDR2 memory. */
/* Define maximum downloadable image size */
#define MAX_IMAGE_SIZE 0xC00000 /* 12 Mbytes */
struct nor_boot_t {
uint32_t magicNum;
uint32_t entryPoint;
uint32_t appSize;
uint32_t ldAddress; /* Starting RAM address where image is to copied - XIP Mode */
};
enum bootmode_t {
NON_SECURE_NAND = 0, /* Non-secure NAND mode */
NON_SECURE_NOR, /* Non-secure NOR mode */
UNKNOWN_MODE, /* Unknown mode */
NON_SECURE_UART /* Non-secure UART mode */
};
#define ENDIAN_SWAP(a) (((a&0xFF)<<24)|((a&0xFF0000)>>8)|((a&0xFF00)<<8)|((a&0xFF000000)>>24))
/* Log functions */
#define log_fail(_x_) uart_send_str_lf(_x_)
#define log_info(_x_) uart_send_str_lf(_x_)
#define log_debug(_x_) uart_send_str_lf(_x_)
#define host_msg(_x_) uart_send_str_lf(_x_)
#endif /* _COMMON_H_ */

78
crc.c

@ -0,0 +1,78 @@
/*
* crc.h -- CRC routines
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on dv-boot, original copyright follows:
* Copyright (c) 2007 Sergey Kubushin <ksi@koi8.net>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <stdint.h>
#include <string.h> /* For size_t */
#define CRC_TABLE_ELEMENTS 256
#define DAVINCI_CRC_POLY 0x04C11DB7
static uint32_t crc32_table[CRC_TABLE_ELEMENTS];
static uint32_t
reflect_num(uint32_t in_val, uint32_t num)
{
uint32_t i;
uint32_t out_val = 0x0;
for (i = 1; i < (num + 1); i++) {
out_val |= (uint32_t)(((in_val & 0x1)) << (num - i));
in_val >>= 1;
}
return out_val;
}
/* Build a reflected CRC-32 table (for standard CRC-32 algorithm) */
void
crc32_dv_build_table(void)
{
uint32_t i, j, crc_accum;
for (i = 0; i < CRC_TABLE_ELEMENTS; i++) {
crc_accum = reflect_num(i, 8) << (32 - 8);
for (j = 0; j < 8; j++) {
if ((crc_accum & 0x80000000) != 0x00000000)
crc_accum = (crc_accum << 1) ^ DAVINCI_CRC_POLY;
else
crc_accum = (crc_accum << 1);
crc32_table[i] = reflect_num(crc_accum, 32);
}
}
}
/* Compute CRC32 checksum */
uint32_t
crc32_dv_compute(uint8_t *data, size_t size)
{
uint32_t crc32 = 0xFFFFFFFF;
while (size-- > 0)
crc32 = crc32_table[(crc32 ^ *data++) & 0xFF] ^ (crc32 >> 8);
return crc32;
}

34
crc.h

@ -0,0 +1,34 @@
/*
* crc.h -- CRC definitions.
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef CRC_H
#define CRC_H 1
#include <stdint.h>
#include <string.h> /* For size_t, memcpy, memset */
/* Build a reflected CRC-32 table (for standard CRC-32 algorithm) */
void crc32_dv_build_table(void);
/* Compute non-standard CRC32 */
uint32_t
crc32_dv_compute(uint8_t *data, size_t size);
#endif /* CRC_H */

528
davinci.c

@ -0,0 +1,528 @@
/*
* davinci.c - common DaVinci platform initialization
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "common.h"
#include "davinci.h"
#include "ddr.h"
#include "util.h"
#include "uart.h"
#include "gpio.h"
extern enum bootmode_t bootmode;
extern const int8_t lpsc_en_list[];
extern const int8_t lpsc_emurstie_list[];
extern const size_t lpsc_en_list_len;
extern const size_t lpsc_emurstie_list_len;
/* Symbol from linker script */
extern uint32_t __DDR_START;
static void
pinmuxControl(uint32_t regOffset, uint32_t mask, uint32_t value)
{
SYSTEM->PINMUX[regOffset] &= ~mask;
SYSTEM->PINMUX[regOffset] |= (mask & value);
}
static void
lpsc_tansition(uint8_t module, uint8_t domain, uint8_t state)
{
/* Wait for any outstanding transition to complete */
while ((PSC->PTSTAT) & (0x00000001 << domain))
;
/* If we are already in that state, just return */
if (((PSC->MDSTAT[module]) & 0x1F) == state)
return;
/* Perform transition */
PSC->MDCTL[module] = ((PSC->MDCTL[module]) & (0xFFFFFFE0)) | (state);
PSC->PTCMD |= (0x00000001 << domain);
/* Wait for transition to complete */
while ((PSC->PTSTAT) & (0x00000001 << domain))
;
/* Wait and verify the state */
while (((PSC->MDSTAT[module]) & 0x1F) != state)
;
}
static void
ivt_init(void)
{
volatile uint32_t *ivect;
extern uint32_t __IVT;
if (bootmode == NON_SECURE_NOR) {
ivect = &(__IVT);
*ivect++ = 0xEAFFFFFE; /* Reset @ 0x00*/
} else
ivect = &(__IVT) + 4;
*ivect++ = 0xEAFFFFFE; /* Undefined Address @ 0x04 */
*ivect++ = 0xEAFFFFFE; /* Software Interrupt @0x08 */
*ivect++ = 0xEAFFFFFE; /* Pre-Fetch Abort @ 0x0C */
*ivect++ = 0xEAFFFFFE; /* Data Abort @ 0x10 */
*ivect++ = 0xEAFFFFFE; /* Reserved @ 0x14 */
*ivect++ = 0xEAFFFFFE; /* IRQ @ 0x18 */
*ivect = 0xEAFFFFFE; /* FIQ @ 0x1C */
}
static int
timer0_init(void)
{
TIMER0->TGCR = 0x00000000; /* Reset timer */
TIMER0->TCR = 0x00000000; /* Disable timer */
TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
/* Set timer period (5 seconds timeout) */
TIMER0->PRD12 = SYSTEM_CLK_HZ * 5;
return E_PASS;
}
void
timer0_start(void)
{
AINTC->IRQ1 |= 0x00000001; /* Clear interrupt */
TIMER0->TGCR = 0x00000000; /* Reset timer */
TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
TIMER0->TCR = 0x00000040; /* Setup for one-shot mode */
TIMER0->TGCR = 0x00000005; /* Start TIMER12 in 32-bits mode. */
}
uint32_t
timer0_status(void)
{
return AINTC->IRQ1 & 0x1;
}
static int
uart0_init(void)
{
UART0->PWREMU_MGNT = 0; /* Reset UART TX & RX components */
waitloop(100);
/* Set DLAB bit - allows setting of clock divisors */
UART0->LCR |= 0x80;
/*
* Compute divisor value. Normally, we should simply return:
* SYSTEM_CLK_HZ / (16 * baudrate)
* but we need to round that value by adding 0.5.
* Rounding is especially important at high baud rates.
*/
UART0->DLL = (SYSTEM_CLK_HZ + (UART_BAUDRATE * (UART_BCLK_RATIO / 2))) /
(UART_BCLK_RATIO * UART_BAUDRATE);
UART0->DLH = 0x00;
UART0->FCR = 0x0007; /* Clear UART TX & RX FIFOs */
UART0->MCR = 0x0000; /* RTS & CTS disabled,
* Loopback mode disabled,
* Autoflow disabled
*/
UART0->LCR = 0x0003; /* Clear DLAB bit
* 8-bit words,
* 1 STOP bit generated,
* No Parity, No Stick paritiy,
* No Break control
*/
/* Enable receiver, transmitter, set to run. */
UART0->PWREMU_MGNT |= 0x6001;
return E_PASS;
}
static int
pll_init(volatile struct pll_regs_t *pll, int pll_mult, int plldiv_ratio[5])
{
int k;
volatile uint32_t *plldiv_reg[5];
int pll_is_powered_up =
(pll->PLLCTL & DEVICE_PLLCTL_PLLPWRDN_MASK) >> 1;
plldiv_reg[0] = &pll->PLLDIV1;
plldiv_reg[1] = &pll->PLLDIV2;
plldiv_reg[2] = &pll->PLLDIV3;
plldiv_reg[3] = &pll->PLLDIV4;
plldiv_reg[4] = &pll->PLLDIV5;
/* Set PLL clock input to internal osc. */
pll->PLLCTL &= ~(DEVICE_PLLCTL_CLKMODE_MASK);
/* Set PLL to bypass, then wait for PLL to stabilize */
pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLENSRC_MASK |
DEVICE_PLLCTL_PLLEN_MASK);
waitloop(150);
/* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */
#if defined(DM644x)
pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK;
#elif defined(DM35x)
pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK;
#endif
if (pll_is_powered_up) {
/* Disable PLL */
pll->PLLCTL |= DEVICE_PLLCTL_PLLDIS_MASK;
/* Powerup PLL */
pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLPWRDN_MASK);
}
/* Enable PLL */
pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLDIS_MASK);
/* Wait for PLL to stabilize */
waitloop(150);
/* Load PLL multiplier. */
pll->PLLM = (pll_mult - 1) & 0xff;
/* Set and enable dividers as needed. */
for (k = 0; k < 5; k++) {
if (plldiv_ratio[k] > 0)
*(plldiv_reg[k]) |= DEVICE_PLLDIV_EN_MASK |
(plldiv_ratio[k] - 1);
}
#if defined(DM35x)
/* Set the processor AIM wait state and PLL1 post-divider to to 1 */
SYSTEM->MISC &= ~(DEVICE_MISC_PLL1POSTDIV_MASK |
DEVICE_MISC_AIMWAITST_MASK);
#endif
/* Initiate a new divider transition. */
pll->PLLCMD |= DEVICE_PLLCMD_GOSET_MASK;
/* Wait for completion of phase alignment. */
while ((pll->PLLSTAT & DEVICE_PLLSTAT_GOSTAT_MASK))
;
/* Wait for PLL to reset ( ~5 usec ) */
waitloop(5000);
/* Release PLL from reset */
/* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */
#if defined(DM644x)
pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK;
#elif defined(DM35x)
pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK;
#endif
/* Wait for PLL to re-lock:
* DM644z: 2000P
* DM35x: 8000P
*/
waitloop(8000);
/* Switch out of BYPASS mode */
pll->PLLCTL |= DEVICE_PLLCTL_PLLEN_MASK;
return E_PASS;
}
static int
pll1_init(void)
{
int plldiv_ratio[5];
#if defined(DM644x)
plldiv_ratio[0] = 1; /* PLLDIV1 fixed */
plldiv_ratio[1] = 2; /* PLLDIV2 fixed */
plldiv_ratio[2] = 3; /* PLLDIV3 fixed */
plldiv_ratio[3] = -1; /* PLLDIV4 not used */
plldiv_ratio[4] = 6; /* PLLDIV5 fixed */
#elif defined(DM35x)
plldiv_ratio[0] = 2; /* PLLDIV1 fixed */
plldiv_ratio[1] = 4; /* PLLDIV2 fixed */
/* Calculate PLL divider ratio for divider 3 (feeds VPBE) */
plldiv_ratio[2] = 0;
while ((plldiv_ratio[2] * VPBE_CLK_HZ) <
(SYSTEM_CLK_HZ * (PLL1_Mult >> 3)))
plldiv_ratio[2]++;
/* Check to make sure we can supply accurate VPBE clock */
if ((plldiv_ratio[2] * VPBE_CLK_HZ) !=
(SYSTEM_CLK_HZ * (PLL1_Mult >> 3)))
return E_FAIL;
/* See the device datasheet for more info (must be 2 or 4) */
plldiv_ratio[3] = 4;
plldiv_ratio[4] = -1; /* PLLDIV5 not used */
#endif
return pll_init(PLL1, PLL1_Mult, plldiv_ratio);
}
static int
pll2_init(void)
{
int plldiv_ratio[5];
plldiv_ratio[0] = PLL2_Div1;
plldiv_ratio[1] = PLL2_Div2;
plldiv_ratio[2] = -1; /* PLLDIV3 not used */
plldiv_ratio[3] = -1; /* PLLDIV4 not used */
plldiv_ratio[4] = -1; /* PLLDIV5 not used */
return pll_init(PLL2, PLL2_Mult, plldiv_ratio);
}
static void
ddr_timing_setup(void)
{
/* The configuration of DDRPHYCR is not dependent on the DDR2 device
* specification but rather on the board layout.
* Setup the read latency and clear DLLPWRDN */
DDR->DDRPHYCR = DDRPHYCR_DEFAULT |
(DDR_READ_Latency & DDRPHYCR_READLAT_MASK);
/*
* Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
* as suggested in TMS320DM6446 errata 2.1.2:
*
* On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
* low priority modules can occupy the bus and prevent high priority
* modules like the VPSS from getting the required DDR2 throughput.
*/
DDR->PBBPR = DDR_PBBPR_PR_OLD_COUNT;
/* TIMUNLOCK (unlocked), CAS Latency, number of banks and page size */
DDR->SDBCR = SDBCR_DEFAULT |
SDBCR_TIMUNLOCK |
(DDR_NM << 14) |
(DDR_CL << 9) |
(DDR_IBANK << 4) |
(DDR_PAGESIZE << 0);
/* Program timing registers */
DDR->SDTIMR = (DDR_T_RFC << 25) |
(DDR_T_RP << 22) |
(DDR_T_RCD << 19) |
(DDR_T_WR << 16) |
(DDR_T_RAS << 11) |
(DDR_T_RC << 6) |
(DDR_T_RRD << 3) |
(DDR_T_WTR << 0);
DDR->SDTIMR2 = (DDR_T_XSNR << 16) |
(DDR_T_XSRD << 8) |
(DDR_T_RTP << 5) |
(DDR_T_CKE << 0);
#if defined(DM35x)
DDR->SDTIMR2 |= (DDR_T_RASMAX << 27) |
(DDR_T_XP << 25);
#endif
/* Clear the TIMUNLOCK bit (locked) */
DDR->SDBCR &= ~SDBCR_TIMUNLOCK;
/* Set the refresh rate */
DDR->SDRCR = DDR_RR;
}
static void
ddr_reset(void)
{
/* Perform a soft reset to the DDR2 memory controller:
* Put in SYNCRESET and enable it again. */
lpsc_tansition(LPSC_DDR2, PD0, PSC_SYNCRESET);
lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE);
}
static int
ddr_init(void)
{
volatile uint32_t *ddr_start = &__DDR_START;
/* For reading/writing dummy value in order to apply timing settings */
volatile uint32_t ddr_dummy_read;
/* Enable DDR2 module. */
lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE);
#if defined(DM35x)
ddr_vtp_calibration();
ddr_reset();
#endif
ddr_timing_setup();
/* Dummy read to apply timing settings */
ddr_dummy_read = ddr_start[0];
#if defined(DM644x)
ddr_reset();
ddr_vtp_calibration();
#endif
/* Verify correct initialization. */
ddr_start[0] = DDR_TEST_PATTERN;
if (ddr_start[0] != DDR_TEST_PATTERN) {
log_fail("DDR init failed");
return E_FAIL;
}
return E_PASS;
}
static void
psc_init(void)
{
uint32_t i;
#if defined(DM35x)
/* Do always on power domain transitions */
while ((PSC->PTSTAT) & 0x00000001);
#elif defined(DM644x)
/*
* Workaround for TMS320DM6446 errata 1.3.22
* (Revision(s) Affected: 1.3 and earlier):
* PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset.
* Clear the reserved location at address 0x01C41A20
*/
PSC_PTSTAT_WORKAROUND_REG = 0;
/* Put the C64x+ Core into reset (if it's on) */
PSC->MDCTL[LPSC_DSP] &= (~0x00000100);
PSC->PTCMD |= 0x00000002;
while ((PSC->PTSTAT) & (0x00000002));
while ((PSC->MDSTAT[LPSC_DSP]) & (0x00000100));
#endif
/* Enable selected modules */
for (i = 0; i < lpsc_en_list_len; i++) {
int8_t k = lpsc_en_list[i];
PSC->MDCTL[k] = (PSC->MDCTL[k] & 0xFFFFFFE0) | PSC_ENABLE;
}
/* Set EMURSTIE on selected modules */
for (i = 0; i < lpsc_emurstie_list_len; i++) {
int8_t k = lpsc_emurstie_list[i];
PSC->MDCTL[k] |= EMURSTIE_MASK;
}
/* Do Always-On Power Domain Transitions */
PSC->PTCMD |= 0x00000001;
while ((PSC->PTSTAT) & 0x00000001);
#if defined(DM644x)
/* DO DSP Power Domain Transitions */
PSC->PTCMD |= 0x00000002;
while ((PSC->PTSTAT) & (0x00000002));
#endif
/* Clear EMURSTIE on selected modules */
for (i = 0; i < lpsc_emurstie_list_len; i++) {
int8_t k = lpsc_emurstie_list[i];
PSC->MDCTL[k] &= (~EMURSTIE_MASK);
}
}
int
davinci_platform_init(char *version)
{
int status = E_PASS;
psc_init();
/* Disable ARM interrupts */
AINTC->INTCTL = 0x4;
AINTC->EABASE = 0x0;
AINTC->EINT0 = 0x0;
AINTC->EINT1 = 0x0;
AINTC->FIQ0 = 0xFFFFFFFF;
AINTC->FIQ1 = 0xFFFFFFFF;
AINTC->IRQ0 = 0xFFFFFFFF;
AINTC->IRQ1 = 0xFFFFFFFF;
#ifdef PINMUX0_DEFAULT
pinmuxControl(0, 0xFFFFFFFF, PINMUX0_DEFAULT);
#endif
#ifdef PINMUX1_DEFAULT
pinmuxControl(1, 0xFFFFFFFF, PINMUX1_DEFAULT);
#endif
/* The folowing are only available on DM35x */
#ifdef PINMUX2_DEFAULT
pinmuxControl(2, 0xFFFFFFFF, PINMUX2_DEFAULT);
#endif
#ifdef PINMUX3_DEFAULT
pinmuxControl(3, 0xFFFFFFFF, PINMUX3_DEFAULT);
#endif
#ifdef PINMUX4_DEFAULT
pinmuxControl(4, 0xFFFFFFFF, PINMUX4_DEFAULT);
#endif
if (status == E_PASS)
status |= pll1_init();
if (status == E_PASS)
status |= uart0_init();
if (status == E_PASS)
status |= timer0_init();
uart_send_lf();
log_info(version);
if (status == E_PASS)
status |= pll2_init();
if (status == E_PASS)
status |= ddr_init();
#ifdef STATUS_LED
gpio_direction_out(STATUS_LED, 1);
#endif /* STATUS_LED */
#ifdef board_minidas
gpio_direction_out(FAN, 0);
gpio_direction_out(BUZZER, 0);
/* Put all peripherals in RESET state */
gpio_direction_out(DSP1_PWR_ENA, 0);
gpio_direction_out(DSP2_PWR_ENA, 0);
gpio_direction_out(WIFI_RESETn, 0);
gpio_direction_out(GPS_RESETn, 0);
gpio_direction_out(CAN_RESETn, 0);
gpio_direction_out(ATA_RESETn, 0);
gpio_direction_out(CAMERA_RESETn, 0);
/* Enable power for hard disk */
gpio_direction_out(HDD_ENA, 1);
#endif
/* IRQ Vector Table Setup */
ivt_init();
return status;
}

463
davinci.h

@ -0,0 +1,463 @@
/*
* davinci.h - common DaVinci platform definitions
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef _DAVINCI_H_
#define _DAVINCI_H_
#include "common.h"
#if defined(DM644x)
#include "dm644x.h"
#elif defined(DM35x)
#include "dm35x.h"
#endif
/* -------------------------------------------------------------------------- *
* System Control Module register structure - See sprue14.pdf, Chapter 10 *
* for more details. *
* -------------------------------------------------------------------------- */
struct sys_module_regs_t {
#if defined(DM644x)
uint32_t PINMUX[2]; //0x00
uint32_t DSPBOOTADDR; //0x08
uint32_t SUSPSRC; //0x0C
uint32_t INTGEN; //0x10
#elif defined(DM35x)
uint32_t PINMUX[5]; //0x00
#endif
uint32_t BOOTCFG; //0x14
uint32_t ARM_INTMUX; //0x18 - ONLY ON DM35x
uint32_t EDMA_EVTMUX; //0x1C - ONLY ON DM35x
uint32_t DDR_SLEW; //0x20 - ONLY ON DM35x
uint32_t CLKOUT; //0x24 - ONLY ON DM35x
uint32_t DEVICE_ID; //0x28
uint32_t VDAC_CONFIG; //0x2C - ONLY ON DM35x
uint32_t TIMER64_CTL; //0x30 - ONLY ON DM35x
uint32_t USBPHY_CTL; //0x34
#if defined(DM644x)
uint32_t CHP_SHRTSW; //0x38
#elif defined(DM35x)
uint32_t MISC; //0x38
#endif
uint32_t MSTPRI[2]; //0x3C
uint32_t VPSS_CLKCTL; //0x44
#if defined(DM644x)
uint32_t VDD3P3V_PWDN; //0x48
uint32_t DDRVTPER; //0x4C
uint32_t RSVD2[8]; //0x50
#elif defined(DM35x)
uint32_t DEEPSLEEP; //0x48
uint32_t RSVD0; //0x4C
uint32_t DEBOUNCE[8]; //0x50
uint32_t VTPIOCR; //0x70
#endif
};
#define SYSTEM ((volatile struct sys_module_regs_t *) 0x01C40000)
/* -------------------------------------------------------------------------- *
* ARM Interrupt Controller register structure - See sprue26.pdf for more *
* details. *
* -------------------------------------------------------------------------- */
struct aintc_regs_t {
uint32_t FIQ0;
uint32_t FIQ1;
uint32_t IRQ0;
uint32_t IRQ1;
uint32_t FIQENTRY;
uint32_t IRQENTRY;
uint32_t EINT0;
uint32_t EINT1;
uint32_t INTCTL;
uint32_t EABASE;
uint32_t RSVD0[2];
uint32_t INTPRI0;
uint32_t INTPRI1;
uint32_t INTPRI2;
uint32_t INTPRI3;
uint32_t INTPRI4;
uint32_t INTPRI5;
uint32_t INTPRI6;
uint32_t INTPRI7;
};
#define AINTC ((volatile struct aintc_regs_t *) 0x01C48000)
/* -------------------------------------------------------------------------- *
* PLL Register structure - See sprue14.pdf, Chapter 6 for more details. *
* -------------------------------------------------------------------------- */
struct pll_regs_t {
uint32_t PID;
uint32_t RSVD0[56];
uint32_t RSTYPE; /* 0x0E4 */
uint32_t RSVD1[6];
uint32_t PLLCTL; /* 0x100 */
uint32_t RSVD2[3];
uint32_t PLLM; /* 0x110 */
uint32_t RSVD3;
uint32_t PLLDIV1; /* 0x118 */
uint32_t PLLDIV2;
uint32_t PLLDIV3;
uint32_t RSVD4;
uint32_t POSTDIV; /* 0x128 */
uint32_t BPDIV;
uint32_t RSVD5[2];
uint32_t PLLCMD; /* 0x138 */
uint32_t PLLSTAT;
uint32_t ALNCTL;
uint32_t DCHANGE;
uint32_t CKEN;
uint32_t CKSTAT;
uint32_t SYSTAT;
uint32_t RSVD6[3];
uint32_t PLLDIV4; /* 0x160 - Only on DM35x */
uint32_t PLLDIV5; /* 0x164 - Only on DM644x */
};
#define PLL1 ((volatile struct pll_regs_t *) 0x01C40800)
#define PLL2 ((volatile struct pll_regs_t *) 0x01C40C00)
#define DEVICE_PLLCTL_CLKMODE_MASK 0x00000100
#define DEVICE_PLLCTL_PLLEN_MASK 0x00000001
#define DEVICE_PLLCTL_PLLPWRDN_MASK 0x00000002
#define DEVICE_PLLCTL_PLLRST_MASK 0x00000008
#define DEVICE_PLLCTL_PLLDIS_MASK 0x00000010
#define DEVICE_PLLCTL_PLLENSRC_MASK 0x00000020
#define DEVICE_PLLCMD_GOSET_MASK 0x00000001
#define DEVICE_PLLSTAT_GOSTAT_MASK 0x00000001
#define DEVICE_PLLDIV_EN_MASK 0x00008000
#define DEVICE_PLLSTAT_LOCK_MASK 0x00000002
/* -------------------------------------------------------------------------- *
* Power/Sleep Ctrl Register structure - See sprue14.pdf, Chapter 7 *
* for more details. *
* -------------------------------------------------------------------------- */
struct psc_regs_t {
uint32_t PID; // 0x000
uint32_t RSVD0[3]; // 0x004
uint32_t GBLCTL; // 0x010 - NOT ON DM35x
uint32_t RSVD1; // 0x014
uint32_t INTEVAL; // 0x018
uint32_t RSVD2[9]; // 0x01C
uint32_t MERRPR0; // 0x040
uint32_t MERRPR1; // 0x044
uint32_t RSVD3[2]; // 0x048
uint32_t MERRCR0; // 0x050
uint32_t MERRCR1; // 0x054
uint32_t RSVD4[2]; // 0x058
uint32_t PERRPR; // 0x060
uint32_t RSVD5; // 0x064
uint32_t PERRCR; // 0x068
uint32_t RSVD6; // 0x06C
uint32_t EPCPR; // 0x070
uint32_t RSVD7; // 0x074
uint32_t EPCCR; // 0x078
uint32_t RSVD8[33]; // 0x07C
uint32_t RAILSTAT; // 0x100 - NOT ON DM35x
uint32_t RAILCTL; // 0x104 - NOT ON DM35x
uint32_t RAILSEL; // 0x108 - NOT ON DM35x
uint32_t RSVD9[5]; // 0x10C
uint32_t PTCMD; // 0x120
uint32_t RSVD10; // 0x124
uint32_t PTSTAT; // 0x128
uint32_t RSVD11[53]; // 0x12C
uint32_t PDSTAT0; // 0x200
uint32_t PDSTAT1; // 0x204
uint32_t RSVD12[62]; // 0x208
uint32_t PDCTL0; // 0x300
uint32_t PDCTL1; // 0x304
uint32_t RSVD13[134]; // 0x308
uint32_t MCKOUT0; // 0x520
uint32_t MCKOUT1; // 0x524
uint32_t RSVD14[182]; // 0x528
uint32_t MDSTAT[41]; // 0x800
uint32_t RSVD15[87]; // 0x8A4
uint32_t MDCTL[41]; // 0xA00
};
#define PSC ((volatile struct psc_regs_t*) 0x01C41000)
#if defined(DM644x)
/* See TMS320DM6446 errata 1.3.22 */
#define PSC_PTSTAT_WORKAROUND_REG (*((volatile uint32_t*) 0x01C41A20))
#endif
#define PD0 0
/* PSC constants */
#define LPSC_VPSS_MAST 0
#define LPSC_VPSS_SLV 1
#define LPSC_EDMACC 2
#define LPSC_EDMATC0 3
#define LPSC_EDMATC1 4
#if defined(DM644x)
#define LPSC_EMAC 5
#define LPSC_EMAC_MEM_CTL 6
#define LPSC_MDIO 7
#define LPSC_RESERVED0 8
#elif defined(DM35x)
#define LPSC_TIMER3 5
#define LPSC_SPI1 6
#define LPSC_MMC_SD1 7
#define LPSC_ASP1 8
#endif
#define LPSC_USB 9
#if defined(DM644x)
#define LPSC_ATA 10
#define LPSC_VLYNQ 11
#define LPSC_HPI 12
#elif defined(DM35x)
#define LPSC_PWM3 10
#define LPSC_SPI2 11
#define LPSC_RTO 12
#endif
#define LPSC_DDR2 13
#define LPSC_AEMIF 14
#define LPSC_MMC_SD0 15
#if defined(DM644x)
#define LPSC_RESERVED1 16
#elif defined(DM35x)
#define LPSC_MEMSTK 16
#endif
#define LPSC_ASP0 17
#define LPSC_I2C 18
#define LPSC_UART0 19
#if defined(DM35x)
#define LPSC_UART1 20
#define LPSC_UART2 21
#define LPSC_SPIO 22
#define LPSC_PWM0 23
#define LPSC_PWM1 24
#define LPSC_PWM2 25
#endif
#define LPSC_GPIO 26
#define LPSC_TIMER0 27
#define LPSC_TIMER1 28
#if defined(DM35x)
#define LPSC_TIMER2 29
#define LPSC_SYSMOD 30
#endif
#define LPSC_ARM 31
#if defined(DM644x)
#define LPSC_DSP 39
#define LPSC_IMCOP 40
#elif defined(DM35x)
#define LPSC_VPSS_DAC 40
#endif
#define EMURSTIE_MASK 0x00000200
#define PSC_ENABLE 0x3
#define PSC_DISABLE 0x2
#define PSC_SYNCRESET 0x1
#define PSC_SWRSTDISABLE 0x0
/* -------------------------------------------------------------------------- *
* DDR2 Memory Ctrl Register structure - See sprue22b.pdf for more details.*
* -------------------------------------------------------------------------- */
struct ddr_mem_ctl_regs_t {
uint32_t RSVD0;
uint32_t SDRSTAT;
uint32_t SDBCR;
uint32_t SDRCR;
uint32_t SDTIMR;
uint32_t SDTIMR2;
#if defined(DM644x)
uint32_t RSVD1[2];
#elif defined(DM35x)
uint32_t RSVD1;
uint32_t SDBCR2;
#endif
uint32_t PBBPR; /* 0x20 */
uint32_t RSVD2[39];
uint32_t IRR; /* 0xC0 */
uint32_t IMR;
uint32_t IMSR;
uint32_t IMCR;
uint32_t RSVD3[5];
uint32_t DDRPHYCR;
uint32_t RSVD4[2];
#if defined(DM644x)
uint32_t VTPIOCR; /* 0xF0 - In system control module for DM35x */
#endif
};
#define DDR ((volatile struct ddr_mem_ctl_regs_t *) 0x20000000)
#define DDR_TEST_PATTERN 0xA55AA55A
#define SDBCR_TIMUNLOCK (1 << 15)
#if defined(DM644x)
#define DDRVTPR (*((volatile uint32_t*) 0x01C42030))
#define DDRPHYCR_DEFAULT 0x50006400 /* Default value with reserved fields */
#define DDRPHYCR_READLAT_MASK (0x7 << 0)
#define SDBCR_DEFAULT 0x00130000 /* Default value with reserved fields */
#elif defined(DM35x)
#define DDRPHYCR_DEFAULT 0x28006400 /* Default value with reserved fields */
#define DDRPHYCR_READLAT_MASK (0xF << 0)
#define SDBCR_DEFAULT 0x00170000 /* Default value with reserved fields */
#endif
/* -------------------------------------------------------------------------- *
* AEMIF Register structure - See sprue20a.pdf for more details. *
* -------------------------------------------------------------------------- */
struct emif_regs_t {
uint32_t ERCSR; // 0x00
uint32_t AWCCR; // 0x04
uint32_t SDBCR; // 0x08 - NOT ON DM35x
uint32_t SDRCR; // 0x0C - NOT ON DM35x
uint32_t A1CR; // 0x10
uint32_t A2CR; // 0x14
uint32_t A3CR; // 0x18 - NOT ON DM35x
uint32_t A4CR; // 0x1C - NOT ON DM35x
uint32_t SDTIMR; // 0x20 - NOT ON DM35x
uint32_t DDRSR; // 0x24 - NOT ON DM35x
uint32_t DDRPHYCR; // 0x28 - NOT ON DM35x
uint32_t DDRPHYSR; // 0x2C - NOT ON DM35x
uint32_t TOTAR; // 0x30 - NOT ON DM35x
uint32_t TOTACTR; // 0x34 - NOT ON DM35x
uint32_t DDRPHYID_REV; // 0x38 - NOT ON DM35x
uint32_t SDSRETR; // 0x3C - NOT ON DM35x
uint32_t EIRR; // 0x40
uint32_t EIMR;
uint32_t EIMSR;
uint32_t EIMCR;
uint32_t IOCTRLR; // 0x50 - NOT ON DM35x
uint32_t IOSTATR; // 0x54 - NOT ON DM35x
uint32_t RSVD0;
uint32_t ONENANDCTL; // 0x5C - ONLY ON DM35x
uint32_t NANDFCR; // 0x60
uint32_t NANDFSR; // 0x64
uint32_t RSVD1[2];
uint32_t NANDF1ECC; // 0x70
uint32_t NANDF2ECC; // 0x74
uint32_t NANDF3ECC; // 0x78 - NOT ON DM35x
uint32_t NANDF4ECC; // 0x7C - NOT ON DM35x
uint32_t RSVD2; // 0x80
uint32_t IODFTECR;
uint32_t IODFTGCR;
uint32_t RSVD3;
uint32_t IODFTMRLR; // 0x90
uint32_t IODFTMRMR; // 0x94
uint32_t IODFTMRMSBR; // 0x98
uint32_t RSVD4[5];
uint32_t MODRNR; // 0xB0
uint32_t RSVD5[2];
uint32_t NAND4BITECCLOAD; // 0xBC - ONLY ON DM35x
uint32_t NAND4BITECC1; // 0xC0 - ONLY ON DM35x
uint32_t NAND4BITECC2; // 0xC4 - ONLY ON DM35x
uint32_t NAND4BITECC3; // 0xC8 - ONLY ON DM35x
uint32_t NAND4BITECC4; // 0xCC - ONLY ON DM35x
uint32_t NANDERRADD1; // 0xD0 - ONLY ON DM35x
uint32_t NANDERRADD2; // 0xD4 - ONLY ON DM35x
uint32_t NANDERRVAL1; // 0xD8 - ONLY ON DM35x
uint32_t NANDERRVAL2; // 0xDC - ONLY ON DM35x
};
#if defined(DM644x)
#define AEMIF ((volatile struct emif_regs_t *) 0x01E00000)
#elif defined(DM35x)
#define AEMIF ((volatile struct emif_regs_t *) 0x01E10000)
#endif
/* -------------------------------------------------------------------------- *
* UART Register structure - See sprue33.pdf for more details. *
* -------------------------------------------------------------------------- */
struct uart_regs_t {
uint32_t RBR;
uint32_t IER;
uint32_t IIR;
uint32_t LCR;
uint32_t MCR;
uint32_t LSR;
uint32_t MSR; /* NOT ON DM35x */
uint32_t SCR; /* NOT ON DM35x */
uint32_t DLL;
uint32_t DLH;
uint32_t PID1;
uint32_t PID2;
uint32_t PWREMU_MGNT;
};
#define THR RBR
#define FCR IIR
#define UART0 ((volatile struct uart_regs_t *) 0x01C20000)
#define UART_BCLK_RATIO 16 /* BCLK is 16 times the baudrate */
#define UART_BAUDRATE 115200
/* -------------------------------------------------------------------------- *
* Timer Register structure - See sprue26.pdf for more details. *
* -------------------------------------------------------------------------- */
struct timer_regs_t {
uint32_t PID12;
uint32_t EMUMGT_CLKSPD;
uint32_t GPINT_GPEN; // NOT ON DM35x
uint32_t GPTDAT_GPDIR; // NOT ON DM35x
uint32_t TIM12;
uint32_t TIM34;
uint32_t PRD12;
uint32_t PRD34;
uint32_t TCR;
uint32_t TGCR;
uint32_t WDTCR;
uint32_t RSVD1[3]; // 0x2C - ONLY ON DM35x
uint32_t REL12; // 0x34 - ONLY ON DM35x
uint32_t REL34; // 0x38 - ONLY ON DM35x
uint32_t CAP12; // 0x3C - ONLY ON DM35x
uint32_t CAP34; // 0x40 - ONLY ON DM35x
uint32_t INTCTL_STAT; // 0x44 - ONLY ON DM35x
};
#define TIMER0 ((volatile struct timer_regs_t *) 0x01C21400)
struct gpio_controller {
uint32_t dir;
uint32_t out_data;
uint32_t set_data;
uint32_t clr_data;
uint32_t in_data;
uint32_t set_rising;
uint32_t clr_rising;
uint32_t set_falling;
uint32_t clr_falling;
uint32_t intstat;
};
#define DAVINCI_GPIO_BASE 0x01C67000
#define GPIOC ((volatile struct gpio_controller *) DAVINCI_GPIO_BASE)
int davinci_platform_init(char *version);
void ddr_vtp_calibration(void);
void timer0_start(void);
uint32_t timer0_status(void);
#endif /* _DAVINCI_H_ */

364
ddr.h

@ -0,0 +1,364 @@
/*
* ddr.h - DDR devices parameters
*
* Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
*
* Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
* Copyright 2008 Texas Instruments, Inc. <www.ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef _DDDR_H_
#define _DDDR_H_
#include <stdint.h>
#if defined(MICRON_MT47H32M16BN_3_171MHZ)
/* Micron MT47H32M16BN-3 @ 171 MHz settings:
* TCK = 5.85 nS -> 1 / 171MHz
* T_REF = 7.8 uS (varies with commercial vs industrial)
* T_RFC = 105 nS (varies with capacity)
* T_RP = 15 nS
* T_RCD = 15 nS
* T_WR = 15 nS
* T_RAS = 40 nS
* T_RASMAX = 70 uS
* T_RTP = 7.5 nS
* T_RC = 55 nS
* T_RRD = 10 nS
* T_WTR = 7.5 nS
* T_XSRD = 200 nS
* T_XSNR = 115 nS -> T_RFC(MIN) + 10
* T_CKE = 3 TCK
* T_XP = 2 TCK
*/
static const uint8_t DDR_IBANK = 2; /* 4 banks. */
static const uint16_t DDR_RR = 1336; /* DDRCLK * T_REF */
static const uint8_t DDR_CL = 3;
static const uint8_t DDR_T_RFC = 17; /* (T_RFC * DDRCLK) - 1 */
static const uint8_t DDR_T_RP = 2; /* (T_RP * DDRCLK) - 1 */
static const uint8_t DDR_T_RCD = 2; /* (T_RCD * DDRCLK) - 1 */
static const uint8_t DDR_T_WR = 2; /* (T_WR * DDRCLK) - 1 */
static const uint8_t DDR_T_RAS = 6; /* (T_RAS * DDRCLK) - 1 */
static const uint8_t DDR_T_RC = 9; /* (T_RC * DDRCLK) - 1 */
static const uint8_t DDR_T_RRD = 1; /* [((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1 */
/*
* Only for 8 bank DDR2/mDDR memories. When interfacing to DDR2/mDDR memories
* with less than 8 banks the T_RRD field should be calculated using:
* (T_RRD * DDRCLK) - 1.
*/
static const uint8_t DDR_T_WTR = 1; /* (T_WTR * DDRCLK) - 1 */
static const uint8_t DDR_T_RASMAX = 8; /*
* (T_RASMAX(uS) / T_REF) - 1
* Should be 17 but max. value
* is 15 (4 bits)
*/
static const uint8_t DDR_T_XP = 2; /*
* If T_XP > T_CKE then
* T_XP = T_XP - 1
* else