Primary Bootloader (before u-boot) in sysmoBTSv2
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  1. /*
  2. * nand.c - NAND flash functions
  3. *
  4. * Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
  5. *
  6. * Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
  7. * Copyright 2008 Texas Instruments, Inc. <www.ti.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  22. */
  23. #include "common.h"
  24. #include "davinci.h"
  25. #include "util.h"
  26. #include "uart.h"
  27. #include "nand.h"
  28. /* BUS width defines */
  29. #define BUS_8BIT 0x01
  30. #define BUS_16BIT 0x02
  31. #define BUS_32BIT 0x04
  32. /* NAND flash addresses */
  33. #define NAND_DATA_OFFSET 0x00
  34. #define NAND_ALE_OFFSET 0x08
  35. #define NAND_CLE_OFFSET 0x10
  36. #define NAND_TIMEOUT 5000 /*us*/
  37. /* NAND flash commands */
  38. #define NAND_LO_PAGE 0x00
  39. #define NAND_HI_PAGE 0x01
  40. #define NAND_LOCK 0x2A
  41. #define NAND_UNLOCK_START 0x23
  42. #define NAND_UNLOCK_END 0x24
  43. #define NAND_READ_30H 0x30
  44. #define NAND_EXTRA_PAGE 0x50
  45. #define NAND_RDID 0x90
  46. #define NAND_RDIDADD 0x00
  47. #define NAND_RESET 0xFF
  48. #define NAND_PGRM_START 0x80
  49. #define NAND_PGRM_END 0x10
  50. #define NAND_RDY 0x40
  51. #define NAND_PGM_FAIL 0x01
  52. #define NAND_BERASEC1 0x60
  53. #define NAND_BERASEC2 0xD0
  54. #define NAND_STATUS 0x70
  55. /* Status output */
  56. #define NAND_NANDFSR_READY 0x01
  57. #define NAND_STATUS_WRITEREADY 0xC0
  58. #define NAND_STATUS_ERROR 0x01
  59. #define NAND_STATUS_BUSY 0x40
  60. #define UNKNOWN_NAND 0xFF /* Unknown device id */
  61. /* Gives the page size in bytes without the spare bytes */
  62. #define NANDFLASH_PAGESIZE(x) ((x >> 8) << 8)
  63. union flash_data {
  64. uint8_t c;
  65. uint16_t w;
  66. uint32_t l;
  67. };
  68. union flash_ptr {
  69. volatile uint8_t *cp;
  70. volatile uint16_t *wp;
  71. volatile uint32_t *lp;
  72. };
  73. struct nand_dev_infos_t {
  74. uint8_t id; /* Device ID */
  75. uint16_t num_blocks; /* Number of blocks */
  76. uint8_t pages_per_block; /* Number of pages per block */
  77. uint16_t bytes_per_page; /* Number of bytes per page (with spare) */
  78. };
  79. struct nand_info_t {
  80. uint32_t base_addr; /* Base address of NAND CS memory space. */
  81. int bus_width; /* Bus width: 0 = 8 bits, 1 = 16 bits */
  82. int id; /* Index into nand_dev_infos_t array. */
  83. int num_blocks; /* Number of blocks */
  84. int pages_per_block; /* Number of pages per block */
  85. int bytes_per_page; /* Number of bytes per page (with spare) */
  86. int num_cab; /* Number of Column address cycles */
  87. int num_rab; /* Number of Row address cycles */
  88. uint32_t ecc_mask; /* Mask for ECC register */
  89. int large_page; /* True if page size >= 2048 bytes */
  90. int ecc_index; /* ECC position is different for small and
  91. * large page devices. */
  92. int chunk_size; /* Always read/write in 512 bytes chunk max.
  93. * This will be set based on page size. */
  94. int spare_bytes; /* Number of spare area bytes per page. */
  95. int blk_addr_shift; /* Number of bits by which to shift block address */
  96. int page_addr_shift; /* Number of bits by which to shift page address */
  97. int cs_offset; /*
  98. * Chip-select offset:
  99. * 0 = CS2 space
  100. * 1 = CS3 space
  101. * 2 = CS4 space
  102. * 3 = CS5 space
  103. */
  104. };
  105. /* Buffer for storing data read from NAND flash */
  106. static uint8_t read_buf[MAX_PAGE_SIZE] __attribute__((section(".ddrram")));
  107. /* Symbol from linker script */
  108. extern uint32_t __NANDFlash;
  109. /* structure for holding details about the NAND device itself */
  110. static volatile struct nand_info_t nand_info;
  111. /* Table of ROM supported NAND devices */
  112. static const struct nand_dev_infos_t nand_dev_infos[] = {
  113. /* id, num_blocks, pages_per_block, bytes_per_page */
  114. {0x6E, 256, 16, 256+8}, /* 1 MB */
  115. {0x68, 256, 16, 256+8}, /* 1 MB */
  116. {0xEC, 256, 16, 256+8}, /* 1 MB */
  117. {0xE8, 256, 16, 256+8}, /* 1 MB */
  118. {0xEA, 512, 16, 256+8}, /* 2 MB */
  119. {0xE3, 512, 16, 512+16}, /* 4 MB */
  120. {0xE5, 512, 16, 512+16}, /* 4 MB */
  121. {0xE6, 1024, 16, 512+16}, /* 8 MB */
  122. {0x39, 1024, 16, 512+16}, /* 8 MB */
  123. {0x6B, 1024, 16, 512+16}, /* 8 MB */
  124. {0x73, 1024, 32, 512+16}, /* 16 MB */
  125. {0x33, 1024, 32, 512+16}, /* 16 MB */
  126. {0x75, 2048, 32, 512+16}, /* 32 MB */
  127. {0x35, 2048, 32, 512+16}, /* 32 MB */
  128. {0x43, 1024, 32, 512+16}, /* 16 MB 0x1243 */
  129. {0x45, 2048, 32, 512+16}, /* 32 MB 0x1245 */
  130. {0x53, 1024, 32, 512+16}, /* 16 MB 0x1253 */
  131. {0x55, 2048, 32, 512+16}, /* 32 MB 0x1255 */
  132. {0x36, 4096, 32, 512+16}, /* 64 MB */
  133. {0x46, 4096, 32, 512+16}, /* 64 MB 0x1346 */
  134. {0x56, 4096, 32, 512+16}, /* 64 MB 0x1356 */
  135. {0x76, 4096, 32, 512+16}, /* 64 MB */
  136. {0x74, 8192, 32, 512+16}, /* 128 MB 0x1374 */
  137. {0x79, 8192, 32, 512+16}, /* 128 MB */
  138. {0x71, 16384, 32, 512+16}, /* 256 MB */
  139. {0xF1, 1024, 64, 2048+64}, /* 128 MB - Big Block */
  140. {0xA1, 1024, 64, 2048+64}, /* 128 MB - Big Block */
  141. {0xAA, 2048, 64, 2048+64}, /* 256 MB - Big Block */
  142. {0xDA, 2048, 64, 2048+64}, /* 256 MB - Big Block */
  143. {0xDC, 4096, 64, 2048+64}, /* 512 MB - Big Block */
  144. {0xAC, 4096, 64, 2048+64}, /* 512 MB - Big Block */
  145. {0xB1, 1024, 64, 2048+64}, /* 128 MB - Big Block */
  146. {0xC1, 1024, 64, 2048+64}, /* 128 MB - Big Block */
  147. {0xD3, 4096, 64, 2048+64}, /* 512 MB - Big Block */
  148. {0x00, 0, 0, 0} /* Indicate end of table */
  149. };
  150. static volatile uint8_t *
  151. flash_make_addr(uint32_t baseAddr, uint32_t offset)
  152. {
  153. return (volatile uint8_t *) (baseAddr + offset);
  154. }
  155. static void
  156. flash_write_data(uint32_t offset, uint32_t data)
  157. {
  158. volatile union flash_ptr addr;
  159. union flash_data dataword;
  160. dataword.l = data;
  161. addr.cp = flash_make_addr(nand_info.base_addr, offset);
  162. switch (nand_info.bus_width) {
  163. case BUS_8BIT:
  164. *addr.cp = dataword.c;
  165. break;
  166. case BUS_16BIT:
  167. *addr.wp = dataword.w;
  168. break;
  169. }
  170. }
  171. static void
  172. flash_write_cmd(uint32_t cmd)
  173. {
  174. flash_write_data(NAND_CLE_OFFSET, cmd);
  175. }
  176. static void
  177. flash_write_addr(uint32_t addr)
  178. {
  179. flash_write_data(NAND_ALE_OFFSET, addr);
  180. }
  181. static void
  182. flash_write_bytes(const uint8_t *src, uint32_t numBytes)
  183. {
  184. volatile union flash_ptr destAddr, srcAddr;
  185. uint32_t i;
  186. srcAddr.cp = (volatile uint8_t *) src;
  187. destAddr.cp = flash_make_addr(nand_info.base_addr, NAND_DATA_OFFSET);
  188. switch (nand_info.bus_width) {
  189. case BUS_8BIT:
  190. for (i = 0; i < numBytes; i++)
  191. *destAddr.cp = *srcAddr.cp++;
  192. break;
  193. case BUS_16BIT:
  194. for (i = 0; i < (numBytes >> 1); i++)
  195. *destAddr.wp = *srcAddr.wp++;
  196. break;
  197. }
  198. }
  199. static void
  200. flash_write_addr_bytes(uint32_t numAddrBytes, uint32_t addr)
  201. {
  202. uint32_t i;
  203. for (i = 0; i < numAddrBytes; i++)
  204. flash_write_addr((addr >> (8*i)) & 0xff);
  205. }
  206. static void
  207. flash_write_row_addr_bytes(uint32_t block, uint32_t page)
  208. {
  209. uint32_t row_addr;
  210. row_addr =
  211. (block << (nand_info.blk_addr_shift - nand_info.page_addr_shift)) | page;
  212. flash_write_addr_bytes(nand_info.num_rab, row_addr);
  213. }
  214. static void
  215. flash_write_addr_cycles(uint32_t block, uint32_t page)
  216. {
  217. flash_write_addr_bytes(nand_info.num_cab, 0x00000000);
  218. flash_write_row_addr_bytes(block, page);
  219. }
  220. static uint32_t
  221. flash_read_data(void)
  222. {
  223. volatile union flash_ptr addr;
  224. union flash_data cmdword;
  225. cmdword.l = 0x0;
  226. addr.cp = flash_make_addr(nand_info.base_addr, NAND_DATA_OFFSET);
  227. switch (nand_info.bus_width) {
  228. case BUS_8BIT:
  229. cmdword.c = *addr.cp;
  230. break;
  231. case BUS_16BIT:
  232. cmdword.w = *addr.wp;
  233. break;
  234. }
  235. return cmdword.l;
  236. }
  237. static void
  238. flash_read_bytes(uint8_t *dest, uint32_t numBytes)
  239. {
  240. volatile union flash_ptr destAddr, srcAddr;
  241. uint32_t i;
  242. destAddr.cp = (volatile uint8_t *) dest;
  243. srcAddr.cp = flash_make_addr(nand_info.base_addr, NAND_DATA_OFFSET);
  244. switch (nand_info.bus_width) {
  245. case BUS_8BIT:
  246. for (i = 0; i < numBytes; i++)
  247. *destAddr.cp++ = *srcAddr.cp;
  248. break;
  249. case BUS_16BIT:
  250. for (i = 0; i < (numBytes >> 1); i++)
  251. *destAddr.wp++ = *srcAddr.wp;
  252. break;
  253. }
  254. }
  255. /* Poll bit of NANDFSR to indicate ready */
  256. static int
  257. nand_wait_for_ready(uint32_t timeout_us)
  258. {
  259. uint32_t ready;
  260. uint32_t timerStatus;
  261. waitloop(200);
  262. timer0_start(SYSTEM_CLK_MHZ * timeout_us);
  263. do {
  264. ready = AEMIF->NANDFSR & NAND_NANDFSR_READY;
  265. timerStatus = timer0_status();
  266. } while (!ready && timerStatus);
  267. if (timerStatus == 0) {
  268. log_info("NAND busy timeout");
  269. return E_FAIL;
  270. }
  271. return E_PASS;
  272. }
  273. /* Wait for the status to be ready in NAND register
  274. * There were some problems reported in DM320 with Ready/Busy pin
  275. * not working with all NANDs. So this check has also been added.
  276. */
  277. static int
  278. nand_wait_for_status(uint32_t timeout)
  279. {
  280. volatile uint32_t cnt;
  281. uint32_t status;
  282. cnt = timeout;
  283. do {
  284. flash_write_cmd(NAND_STATUS);
  285. status = flash_read_data() &
  286. (NAND_STATUS_ERROR | NAND_STATUS_BUSY);
  287. cnt--;
  288. } while ((cnt > 0) && !status);
  289. if (cnt == 0) {
  290. log_info("NAND status timeout");
  291. return E_FAIL;
  292. }
  293. return E_PASS;
  294. }
  295. /* Read the current ECC calculation and restart process */
  296. static uint32_t
  297. nand_read_ecc(void)
  298. {
  299. uint32_t retval;
  300. /* Read and mask appropriate (based on CSn space flash is in)
  301. * ECC register */
  302. retval = ((uint32_t *)(&(AEMIF->NANDF1ECC)))[nand_info.cs_offset] &
  303. nand_info.ecc_mask;
  304. waitloop(5);
  305. #ifdef NAND_DEBUG
  306. uart_send_str("Value read from ECC register: ");
  307. uart_send_hexnum(retval, 8);
  308. uart_send_lf();
  309. #endif
  310. /* Write appropriate bit to start ECC calculations */
  311. AEMIF->NANDFCR |= (1<<(8 + (nand_info.cs_offset)));
  312. return retval;
  313. }
  314. /* Get details of the NAND flash used from the id and the table of NAND
  315. * devices. */
  316. static int
  317. nand_get_details(uint8_t *out_manID, uint8_t *out_deviceID)
  318. {
  319. uint32_t manID, deviceID, i, j;
  320. /* Issue device read ID command. */
  321. flash_write_cmd(NAND_RDID);
  322. flash_write_addr(NAND_RDIDADD);
  323. /* Read ID bytes */
  324. manID = flash_read_data() & 0xFF;
  325. deviceID = flash_read_data() & 0xFF;
  326. j = flash_read_data() & 0xFF;
  327. j = flash_read_data() & 0xFF;
  328. *out_manID = manID;
  329. *out_deviceID = deviceID;
  330. uart_send_str(" ID:");
  331. uart_send_hexnum(deviceID, 2);
  332. if (nand_info.bus_width == BUS_16BIT)
  333. uart_send_str(", 16");
  334. else
  335. uart_send_str(", 8");
  336. log_info("-bit bus");
  337. i = 0;
  338. while (nand_dev_infos[i].id != 0x00) {
  339. if (deviceID == nand_dev_infos[i].id) {
  340. nand_info.id = (uint8_t) nand_dev_infos[i].id;
  341. nand_info.pages_per_block =
  342. nand_dev_infos[i].pages_per_block;
  343. nand_info.num_blocks = nand_dev_infos[i].num_blocks;
  344. nand_info.bytes_per_page = NANDFLASH_PAGESIZE(
  345. nand_dev_infos[i].bytes_per_page);
  346. nand_info.spare_bytes = nand_dev_infos[i].bytes_per_page -
  347. nand_info.bytes_per_page;
  348. /* Configure small or large page device. */
  349. if (nand_info.bytes_per_page >= 2048) {
  350. /* Set the large page flag */
  351. nand_info.large_page = true;
  352. nand_info.ecc_index = 2;
  353. nand_info.chunk_size = 512; /* Limit to 512 bytes */
  354. } else {
  355. /* Clear the large page flag */
  356. nand_info.large_page = false;
  357. nand_info.ecc_index = 0;
  358. nand_info.chunk_size = nand_info.bytes_per_page;
  359. }
  360. /* Setup address shift values */
  361. j = 0;
  362. while ((nand_info.pages_per_block >> j) > 1)
  363. j++;
  364. nand_info.blk_addr_shift = j;
  365. nand_info.page_addr_shift = (nand_info.large_page) ? 16 : 8;
  366. nand_info.blk_addr_shift += nand_info.page_addr_shift;
  367. /* Set number of column address bytes needed */
  368. nand_info.num_cab = nand_info.page_addr_shift >> 3;
  369. j = 0;
  370. while ((nand_info.num_blocks >> j) > 1)
  371. j++;
  372. /* Set number of row address bytes needed */
  373. if ((nand_info.blk_addr_shift + j) <= 24)
  374. nand_info.num_rab = 3 -
  375. nand_info.num_cab;
  376. else if ((nand_info.blk_addr_shift + j) <= 32)
  377. nand_info.num_rab = 4 -
  378. nand_info.num_cab;
  379. else
  380. nand_info.num_rab = 5 -
  381. nand_info.num_cab;
  382. /* Set the ECC bit mask */
  383. if (nand_info.bytes_per_page < 512)
  384. nand_info.ecc_mask = 0x07FF07FF;
  385. else
  386. nand_info.ecc_mask = 0x0FFF0FFF;
  387. /* Report informations */
  388. uart_send_str(" Blocks: ");
  389. uart_send_hexnum(nand_info.num_blocks, 5);
  390. uart_send_str(", Pages/block: ");
  391. uart_send_hexnum(nand_info.pages_per_block, 3);
  392. uart_send_str(", Bytes per page: ");
  393. uart_send_hexnum(nand_info.bytes_per_page, 4);
  394. uart_send_lf();
  395. /* Report additional debug informations */
  396. #ifdef NAND_DEBUG
  397. uart_send_str(" Page shift: ");
  398. uart_send_hexnum(nand_info.page_addr_shift, 2);
  399. uart_send_lf();
  400. uart_send_str(" Block shift: ");
  401. uart_send_hexnum(nand_info.blk_addr_shift, 2);
  402. uart_send_lf();
  403. uart_send_str(" Column address bytes: ");
  404. uart_send_hexnum(nand_info.num_cab, 2);
  405. uart_send_lf();
  406. uart_send_str(" Row address bytes: ");
  407. uart_send_hexnum(nand_info.num_rab, 2);
  408. uart_send_lf();
  409. uart_send_str(" ECC mask: ");
  410. uart_send_hexnum(nand_info.ecc_mask, 8);
  411. uart_send_lf();
  412. #endif
  413. return E_PASS;
  414. }
  415. i++;
  416. }
  417. /* No match was found for the device ID */
  418. return E_FAIL;
  419. }
  420. static int
  421. nand_set_a1cr(uint8_t manID, uint8_t deviceID)
  422. {
  423. if (deviceID != 0xA1) {
  424. log_info( "Unsupported NAND device" );
  425. return E_FAIL;
  426. }
  427. switch (manID) {
  428. /* ST/Numonyx */
  429. case 0x20:
  430. AEMIF->A1CR = 0x1844431C;
  431. break;
  432. /* Micron */
  433. case 0x2C:
  434. AEMIF->A1CR = 0x102442EC;
  435. break;
  436. /* Spansion */
  437. case 0x01:
  438. AEMIF->A1CR = 0x1844437C;
  439. break;
  440. /* Toshiba */
  441. case 0x98:
  442. AEMIF->A1CR = 0x102442DC;
  443. break;
  444. default:
  445. log_info( "Unsupported NAND device" );
  446. return E_FAIL;
  447. }
  448. return E_PASS;
  449. }
  450. static void
  451. nand_write_spare(uint32_t eccvalue)
  452. {
  453. uint32_t spare_data[4] = {
  454. 0xFFFFFFFF,
  455. 0xFFFFFFFF,
  456. 0xFFFFFFFF,
  457. 0xFFFFFFFF
  458. };
  459. /* Place the ECC values where the RBL expects them */
  460. spare_data[nand_info.ecc_index] = eccvalue;
  461. /* Write spare bytes infos */
  462. if (nand_info.bytes_per_page == 256)
  463. flash_write_bytes((uint8_t *) spare_data, 8);
  464. else
  465. flash_write_bytes((uint8_t *) spare_data, 16);
  466. }
  467. /*
  468. * RBL-expected layout for large page NAND (ex: 2048 bytes/page):
  469. *
  470. * DM35x DM644x
  471. * -----------------------------
  472. * 512 DATA 2048 DATA
  473. * 16 SPARE 64 SPARE
  474. * 512 DATA
  475. * 16 SPARE
  476. * 512 DATA
  477. * 16 SPARE
  478. * 512 DATA
  479. * 16 SPARE
  480. *
  481. * So for big block NAND devices (bytes per page > 512) on the DM35x, we must
  482. * write 512 bytes and write the ECC immediately after that data, and repeat
  483. * until all the page is written.
  484. */
  485. /* Generic routine to write a page of data to NAND */
  486. static int
  487. nand_write_page(uint32_t block, uint32_t page, const uint8_t *src)
  488. {
  489. uint32_t hw_ecc[4]; /* Maximum of 2048 bytes/page (4 * 512 = 2048) */
  490. uint8_t numWrites, i;
  491. numWrites = (nand_info.bytes_per_page >> 9); /* Divide by 512 */
  492. if (numWrites == 0)
  493. numWrites++;
  494. /* Write program command */
  495. flash_write_cmd(NAND_PGRM_START);
  496. /* Write address bytes */
  497. flash_write_addr_cycles(block, page);
  498. /* Starting the ECC in the NANDFCR register for CS2 (bit no.8) */
  499. nand_read_ecc();
  500. /* Write data */
  501. for (i = 0; i < numWrites; i++) {
  502. /* Write data to page */
  503. flash_write_bytes(src, nand_info.chunk_size);
  504. /* Read the ECC value */
  505. hw_ecc[i] = nand_read_ecc();
  506. /* Format ECC */
  507. endian_data(&(hw_ecc[i]));
  508. #if defined(DM35x)
  509. /* Write spare area */
  510. nand_write_spare(hw_ecc[i]);
  511. #endif
  512. /* Increment the pointer */
  513. src += nand_info.chunk_size;
  514. }
  515. #if defined(DM644x)
  516. for (i = 0; i < numWrites; i++) {
  517. nand_write_spare(hw_ecc[i]);
  518. }
  519. #endif
  520. /* Write program end command */
  521. flash_write_cmd(NAND_PGRM_END);
  522. /* Wait for the device to be ready */
  523. if (nand_wait_for_ready(NAND_TIMEOUT) != E_PASS)
  524. return E_FAIL;
  525. /* Return status check result */
  526. return nand_wait_for_status(NAND_TIMEOUT);
  527. }
  528. static uint32_t
  529. nand_read_spare(void)
  530. {
  531. uint32_t spare_ecc[4], spare_ecc_temp;
  532. /* Read the stored ECC value(s) */
  533. if (nand_info.bytes_per_page == 256)
  534. flash_read_bytes((uint8_t *) spare_ecc, 8);
  535. else
  536. flash_read_bytes((uint8_t *) spare_ecc, 16);
  537. spare_ecc_temp = spare_ecc[nand_info.ecc_index];
  538. /* Format ECC */
  539. endian_data(&spare_ecc_temp);
  540. return spare_ecc_temp;
  541. }
  542. /*
  543. * GPLv2 code taken from the kernel to correct the bit error.
  544. * The content of the ECC register is in the sprue20c.pdf. For
  545. * the odd/even there are four bits spare each. The kernel is
  546. * shifting this around and it is the easiest just to do the
  547. * same.
  548. */
  549. static uint32_t squeeze_ecc_bits(uint32_t tmp)
  550. {
  551. /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
  552. * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
  553. tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
  554. /* Invert so that erased block ECC is correct */
  555. return ~tmp;
  556. }
  557. static int nand_check_fix(
  558. const uint32_t _calc_ecc,
  559. const uint32_t _ecc_nand, uint8_t *dat, int size)
  560. {
  561. uint32_t ecc_nand, ecc_calc;
  562. ecc_calc = squeeze_ecc_bits(_calc_ecc);
  563. ecc_nand = squeeze_ecc_bits(_ecc_nand);
  564. uint32_t diff = ecc_calc ^ ecc_nand;
  565. if (diff) {
  566. if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
  567. /* Correctable error */
  568. if ((diff >> (12 + 3)) < size) {
  569. uint8_t find_bit = 1 << ((diff >> 12) & 7);
  570. uint32_t find_byte = diff >> (12 + 3);
  571. dat[find_byte] ^= find_bit;
  572. log_info("Correcting single bit error.");
  573. uart_send_str("BYTE=");
  574. uart_send_hexnum(find_byte, 8);
  575. uart_send_str(" BIT=");
  576. uart_send_hexnum(find_bit, 8);
  577. uart_send_lf();
  578. return 1;
  579. } else {
  580. log_info("Too many bit errors:");
  581. uart_send_hexnum(diff >> (12+3), 8);
  582. uart_send_lf();
  583. return -1;
  584. }
  585. } else if (!(diff & (diff - 1))) {
  586. /* Single bit ECC error in the ECC itself,
  587. nothing to fix */
  588. log_info("Bit error in the spare data. Ignoring");
  589. return 1;
  590. } else {
  591. /* Uncorrectable error */
  592. log_info("Uncorrectable error");
  593. return -1;
  594. }
  595. }
  596. return 0;
  597. }
  598. /* Read a page from NAND */
  599. int
  600. nand_read_page(uint32_t block, uint32_t page, uint8_t *orig_dest)
  601. {
  602. uint32_t hw_ecc[4];
  603. uint32_t spare_ecc[4];
  604. uint8_t numReads, i;
  605. uint8_t *dest = orig_dest;
  606. numReads = (nand_info.bytes_per_page >> 9); /* Divide by 512 */
  607. if (numReads == 0)
  608. numReads++;
  609. /* Write read command */
  610. flash_write_cmd(NAND_LO_PAGE);
  611. /* Write address bytes */
  612. flash_write_addr_cycles(block, page);
  613. /* Additional confirm command for big_block devices */
  614. if (nand_info.large_page)
  615. flash_write_cmd(NAND_READ_30H);
  616. /* Wait for data to be available */
  617. if (nand_wait_for_ready(NAND_TIMEOUT) != E_PASS)
  618. return E_FAIL;
  619. /* Starting the ECC in the NANDFCR register for CS2(bit no.8) */
  620. nand_read_ecc();
  621. /* Read the page data */
  622. for (i = 0; i < numReads; i++) {
  623. /* Read data bytes */
  624. flash_read_bytes(dest, nand_info.chunk_size);
  625. /* Read hardware computed ECC */
  626. hw_ecc[i] = nand_read_ecc();
  627. #if defined(DM35x)
  628. /* Read spare area ECC */
  629. spare_ecc[i] = nand_read_spare();
  630. #endif
  631. /* Increment the pointer */
  632. dest += nand_info.chunk_size;
  633. }
  634. #if defined(DM644x)
  635. for (i = 0; i < numReads; i++) {
  636. spare_ecc[i] = nand_read_spare();
  637. }
  638. #endif
  639. #ifndef NAND_BYPASS_READ_PAGE_ECC_CHECK
  640. for (i = 0; i < numReads; i++) {
  641. /* Verify ECC values */
  642. if (nand_check_fix(hw_ecc[i], spare_ecc[i], &orig_dest[i * nand_info.chunk_size], nand_info.chunk_size) < 0) {
  643. log_info("NAND ECC failure:");
  644. uart_send_str("HW = ");
  645. uart_send_hexnum(hw_ecc[i], 8);
  646. uart_send_lf();
  647. uart_send_str("SPARE =");
  648. uart_send_hexnum(spare_ecc[i], 8);
  649. uart_send_lf();
  650. return E_FAIL;
  651. }
  652. }
  653. #endif /* NAND_BYPASS_READ_PAGE_ECC_CHECK */
  654. /* Return status check result */
  655. return nand_wait_for_status(NAND_TIMEOUT);
  656. }
  657. /* Verify data written by reading and comparing byte for byte */
  658. static int
  659. nand_verify_page(int block, int page, const uint8_t *src)
  660. {
  661. int i;
  662. if (nand_read_page(block, page, read_buf) != E_PASS)
  663. return E_FAIL;
  664. for (i = 0; i < nand_info.bytes_per_page; i++) {
  665. /* Check for data read errors */
  666. if (src[i] != read_buf[i]) {
  667. int k = i;
  668. uart_send_str("NAND verify page failed at block ");
  669. uart_send_hexnum(block, 4);
  670. uart_send_str(", page ");
  671. uart_send_hexnum(page, 4);
  672. uart_send_str(", offset ");
  673. uart_send_hexnum(i, 4);
  674. uart_send_lf();
  675. for (k = i - 8; k < (i + 20); k += 4) {
  676. uart_send_str("offset ");
  677. uart_send_hexnum(k, 4);
  678. uart_send_str(", ram=");
  679. uart_send_hexnum(*((uint32_t *) &src[k]), 8);
  680. uart_send_str(", nand=");
  681. uart_send_hexnum(*((uint32_t *) &read_buf[k]), 8);
  682. uart_send_lf();
  683. }
  684. return E_FAIL;
  685. }
  686. }
  687. return E_PASS;
  688. }
  689. /* NAND Flash unprotect command */
  690. static uint32_t
  691. nand_unprotect_blocks(uint32_t startBlkNum, uint32_t blkCnt)
  692. {
  693. uint32_t endBlkNum;
  694. endBlkNum = startBlkNum + blkCnt - 1;
  695. uart_send_str("Unprotecting blocks ");
  696. uart_send_hexnum(startBlkNum, 4);
  697. uart_send_str(" to ");
  698. uart_send_hexnum(endBlkNum, 4);
  699. uart_send_lf();
  700. /* Do bounds checking */
  701. if (endBlkNum >= nand_info.num_blocks) {
  702. log_fail("Invalid last block");
  703. return E_FAIL;
  704. }
  705. flash_write_cmd(NAND_UNLOCK_START);
  706. flash_write_row_addr_bytes(startBlkNum, 0);
  707. flash_write_cmd(NAND_UNLOCK_END);
  708. flash_write_row_addr_bytes(endBlkNum, 0);
  709. return E_PASS;
  710. }
  711. /* NAND Flash protect command */
  712. static void
  713. nand_protect_blocks(void)
  714. {
  715. log_info("Protecting the entire NAND flash");
  716. flash_write_cmd(NAND_LOCK);
  717. }
  718. /* NAND Flash erase block function */
  719. static uint32_t
  720. nand_erase_blocks(uint32_t startBlkNum, uint32_t blkCnt)
  721. {
  722. uint32_t i;
  723. /* Do bounds checking */
  724. if ((startBlkNum + blkCnt - 1) >= nand_info.num_blocks)
  725. return E_FAIL;
  726. /* Output info about what we are doing */
  727. uart_send_str("Erasing blocks ");
  728. uart_send_hexnum(startBlkNum, 4);
  729. uart_send_str(" to ");
  730. uart_send_hexnum(startBlkNum + blkCnt - 1, 4);
  731. uart_send_lf();
  732. for (i = 0; i < blkCnt; i++) {
  733. /* Start erase command */
  734. flash_write_cmd(NAND_BERASEC1);
  735. /* Write the row addr bytes only */
  736. flash_write_row_addr_bytes(startBlkNum + i, 0);
  737. /* Confirm erase command */
  738. flash_write_cmd(NAND_BERASEC2);
  739. /* Wait for the device to be ready */
  740. if (nand_wait_for_ready(NAND_TIMEOUT) != E_PASS)
  741. return E_FAIL;
  742. /* Verify the op succeeded by reading status from flash */
  743. if (nand_wait_for_status(NAND_TIMEOUT) != E_PASS)
  744. return E_FAIL;
  745. }
  746. return E_PASS;
  747. }
  748. /* Initialize NAND interface and find the details of the NAND used */
  749. int
  750. nand_init(void)
  751. {
  752. uint32_t width;
  753. uint32_t *CSRegs;
  754. uint8_t manID, deviceID;
  755. log_info("Initializing NAND flash:");
  756. #ifdef NAND_BYPASS_READ_PAGE_ECC_CHECK
  757. log_info(" Bypassing ECC checks");
  758. #endif /* NAND_BYPASS_READ_PAGE_ECC_CHECK */
  759. /* Set NAND flash base address */
  760. nand_info.base_addr = (uint32_t) &__NANDFlash;
  761. /* Get the cs_offset (can be 0 through 3 - corresponds with CS2 through
  762. * CS5) */
  763. nand_info.cs_offset = (nand_info.base_addr >> 25) - 1;
  764. /* Setting the nand_width = 0(8 bit NAND) or 1(16 bit NAND). AEMIF CS2
  765. * bus Width is given by the BOOTCFG(bit no.5). */
  766. width = (((SYSTEM->BOOTCFG) & 0x20) >> 5);
  767. nand_info.bus_width = (width)?BUS_16BIT:BUS_8BIT;
  768. /* Setup AEMIF registers for NAND */
  769. CSRegs = (uint32_t *) &(AEMIF->A1CR);
  770. /* Set correct AxCR reg */
  771. CSRegs[nand_info.cs_offset] = 0x3FFFFFFC | width;
  772. /* NAND enable for CSx. */
  773. AEMIF->NANDFCR |= (0x1 << (nand_info.cs_offset));
  774. nand_read_ecc();
  775. /* Send reset command to NAND */
  776. flash_write_cmd(NAND_RESET);
  777. if (nand_wait_for_ready(NAND_TIMEOUT) != E_PASS)
  778. return E_FAIL;
  779. if (nand_get_details(&manID, &deviceID) != E_PASS)
  780. return E_FAIL;
  781. return nand_set_a1cr(manID, deviceID);
  782. }
  783. static int
  784. nand_write_verify_page(int block, int page, const uint8_t *src)
  785. {
  786. int status;
  787. status = nand_write_page(block, page, src);
  788. if (status != E_PASS)
  789. return E_FAIL;
  790. waitloop(200);
  791. /* Verify the page just written */
  792. return nand_verify_page(block, page, src);
  793. }
  794. int
  795. nand_write_prog(struct nand_image_descriptor_t *im_desc, const uint8_t *src,
  796. size_t size)
  797. {
  798. int num_blocks;
  799. int max_block_num;
  800. int page_num;
  801. uint32_t count_mask;
  802. im_desc->page_num = 1; /* Always start data in page 1 */
  803. /* Do some rounding based on data buffer size */
  804. im_desc->size_in_pages = 0;
  805. while ((im_desc->size_in_pages * nand_info.bytes_per_page) < size)
  806. im_desc->size_in_pages++;
  807. /* Get total number of blocks needed */
  808. num_blocks = 0;
  809. while ((num_blocks * nand_info.pages_per_block) <
  810. (im_desc->size_in_pages + 1))
  811. num_blocks++;
  812. uart_send_str("Needed blocks: ");
  813. uart_send_hexnum(num_blocks, 4);
  814. uart_send_lf();
  815. uart_send_str("Needed pages: ");
  816. uart_send_hexnum(im_desc->size_in_pages, 4);
  817. uart_send_lf();
  818. /* Check whether writing UBL or APP (based on destination block) */
  819. if (im_desc->block_num <= END_UBL_BLOCK_NUM)
  820. max_block_num = END_UBL_BLOCK_NUM;
  821. else
  822. max_block_num = im_desc->block_num + MAX_BLOCK_PER_UBOOT - 1;
  823. NAND_WRITE_RETRY:
  824. if (im_desc->block_num > max_block_num) {
  825. log_fail("Block > last block");
  826. return E_FAIL;
  827. }
  828. uart_send_str("Trying block ");
  829. uart_send_hexnum(im_desc->block_num, 4);
  830. uart_send_lf();
  831. /* Unprotect all needed blocks of the Flash */
  832. if (nand_unprotect_blocks(im_desc->block_num, num_blocks) != E_PASS) {
  833. im_desc->block_num++;
  834. log_info("Unprotect failed");
  835. goto NAND_WRITE_RETRY;
  836. }
  837. /* Erase the block where the header goes and the data starts */
  838. if (nand_erase_blocks(im_desc->block_num, num_blocks) != E_PASS) {
  839. im_desc->block_num++;
  840. log_info("Erase failed");
  841. goto NAND_WRITE_RETRY;
  842. }
  843. #ifdef NAND_DEBUG_WRITE_RAMP
  844. {
  845. int k;
  846. /* Usefull for debugging NAND ECC and spare bytes errors. */
  847. for (k = 0; k < 512; k++)
  848. ptr[k] = 0xCAFE0000 | k;
  849. }
  850. #endif
  851. page_num = 0; /* Start in page 0. */
  852. if (im_desc->magic != UBL_CMD_FLASH_DATA) {
  853. /* Write the header to page 0. */
  854. log_info("Writing header");
  855. if (nand_write_verify_page(im_desc->block_num, page_num,
  856. (uint8_t *) im_desc) != E_PASS)
  857. return E_FAIL;
  858. /* Set starting page number for next data portion. */
  859. page_num = 1;
  860. }
  861. /* The following assumes power of 2 page_cnt - *should* always be
  862. * valid. */
  863. count_mask = nand_info.pages_per_block - 1;
  864. log_info("Writing data");
  865. do {
  866. /* Write data on a per page basis */
  867. if (nand_write_verify_page(im_desc->block_num,
  868. page_num & count_mask, src)
  869. != E_PASS)
  870. return E_FAIL;
  871. page_num++;
  872. src += nand_info.bytes_per_page;
  873. if (!(page_num & count_mask))
  874. im_desc->block_num++;
  875. } while (page_num <= im_desc->size_in_pages);
  876. nand_protect_blocks();
  877. return E_PASS;
  878. }
  879. int
  880. nand_erase_all(void)
  881. {
  882. /* Unprotect the NAND Flash */
  883. nand_unprotect_blocks(0, nand_info.num_blocks - 1);
  884. /* Erase all the pages */
  885. if (nand_erase_blocks(0, nand_info.num_blocks - 1) != E_PASS)
  886. return E_FAIL;
  887. /* Protect the device */
  888. nand_protect_blocks();
  889. return E_PASS;
  890. }
  891. int
  892. nand_get_pages_per_block(void)
  893. {
  894. return nand_info.pages_per_block;
  895. }
  896. int
  897. nand_get_bytes_per_page(void)
  898. {
  899. return nand_info.bytes_per_page;
  900. }
  901. int
  902. nand_get_bytes_per_block(void)
  903. {
  904. return nand_info.pages_per_block * nand_info.bytes_per_page;
  905. }