Primary Bootloader (before u-boot) in sysmoBTSv2
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  1. /*
  2. * davinci.h - common DaVinci platform definitions
  3. *
  4. * Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
  5. *
  6. * Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
  7. * Copyright 2008 Texas Instruments, Inc. <www.ti.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  22. */
  23. #ifndef _DAVINCI_H_
  24. #define _DAVINCI_H_
  25. #include "common.h"
  26. #if defined(DM644x)
  27. #include "dm644x.h"
  28. #elif defined(DM35x)
  29. #include "dm35x.h"
  30. #endif
  31. /* -------------------------------------------------------------------------- *
  32. * System Control Module register structure - See sprue14.pdf, Chapter 10 *
  33. * for more details. *
  34. * -------------------------------------------------------------------------- */
  35. struct sys_module_regs_t {
  36. #if defined(DM644x)
  37. uint32_t PINMUX[2]; //0x00
  38. uint32_t DSPBOOTADDR; //0x08
  39. uint32_t SUSPSRC; //0x0C
  40. uint32_t INTGEN; //0x10
  41. #elif defined(DM35x)
  42. uint32_t PINMUX[5]; //0x00
  43. #endif
  44. uint32_t BOOTCFG; //0x14
  45. uint32_t ARM_INTMUX; //0x18 - ONLY ON DM35x
  46. uint32_t EDMA_EVTMUX; //0x1C - ONLY ON DM35x
  47. uint32_t DDR_SLEW; //0x20 - ONLY ON DM35x
  48. uint32_t CLKOUT; //0x24 - ONLY ON DM35x
  49. uint32_t DEVICE_ID; //0x28
  50. uint32_t VDAC_CONFIG; //0x2C - ONLY ON DM35x
  51. uint32_t TIMER64_CTL; //0x30 - ONLY ON DM35x
  52. uint32_t USBPHY_CTL; //0x34
  53. #if defined(DM644x)
  54. uint32_t CHP_SHRTSW; //0x38
  55. #elif defined(DM35x)
  56. uint32_t MISC; //0x38
  57. #endif
  58. uint32_t MSTPRI[2]; //0x3C
  59. uint32_t VPSS_CLKCTL; //0x44
  60. #if defined(DM644x)
  61. uint32_t VDD3P3V_PWDN; //0x48
  62. uint32_t DDRVTPER; //0x4C
  63. uint32_t RSVD2[8]; //0x50
  64. #elif defined(DM35x)
  65. uint32_t DEEPSLEEP; //0x48
  66. uint32_t RSVD0; //0x4C
  67. uint32_t DEBOUNCE[8]; //0x50
  68. uint32_t VTPIOCR; //0x70
  69. #endif
  70. };
  71. #define SYSTEM ((volatile struct sys_module_regs_t *) 0x01C40000)
  72. /* -------------------------------------------------------------------------- *
  73. * ARM Interrupt Controller register structure - See sprue26.pdf for more *
  74. * details. *
  75. * -------------------------------------------------------------------------- */
  76. struct aintc_regs_t {
  77. uint32_t FIQ0;
  78. uint32_t FIQ1;
  79. uint32_t IRQ0;
  80. uint32_t IRQ1;
  81. uint32_t FIQENTRY;
  82. uint32_t IRQENTRY;
  83. uint32_t EINT0;
  84. uint32_t EINT1;
  85. uint32_t INTCTL;
  86. uint32_t EABASE;
  87. uint32_t RSVD0[2];
  88. uint32_t INTPRI0;
  89. uint32_t INTPRI1;
  90. uint32_t INTPRI2;
  91. uint32_t INTPRI3;
  92. uint32_t INTPRI4;
  93. uint32_t INTPRI5;
  94. uint32_t INTPRI6;
  95. uint32_t INTPRI7;
  96. };
  97. #define AINTC ((volatile struct aintc_regs_t *) 0x01C48000)
  98. /* -------------------------------------------------------------------------- *
  99. * PLL Register structure - See sprue14.pdf, Chapter 6 for more details. *
  100. * -------------------------------------------------------------------------- */
  101. struct pll_regs_t {
  102. uint32_t PID;
  103. uint32_t RSVD0[56];
  104. uint32_t RSTYPE; /* 0x0E4 */
  105. uint32_t RSVD1[6];
  106. uint32_t PLLCTL; /* 0x100 */
  107. uint32_t RSVD2[3];
  108. uint32_t PLLM; /* 0x110 */
  109. uint32_t RSVD3;
  110. uint32_t PLLDIV1; /* 0x118 */
  111. uint32_t PLLDIV2;
  112. uint32_t PLLDIV3;
  113. uint32_t RSVD4;
  114. uint32_t POSTDIV; /* 0x128 */
  115. uint32_t BPDIV;
  116. uint32_t RSVD5[2];
  117. uint32_t PLLCMD; /* 0x138 */
  118. uint32_t PLLSTAT;
  119. uint32_t ALNCTL;
  120. uint32_t DCHANGE;
  121. uint32_t CKEN;
  122. uint32_t CKSTAT;
  123. uint32_t SYSTAT;
  124. uint32_t RSVD6[3];
  125. uint32_t PLLDIV4; /* 0x160 - Only on DM35x */
  126. uint32_t PLLDIV5; /* 0x164 - Only on DM644x */
  127. };
  128. #define PLL1 ((volatile struct pll_regs_t *) 0x01C40800)
  129. #define PLL2 ((volatile struct pll_regs_t *) 0x01C40C00)
  130. #define DEVICE_PLLCTL_CLKMODE_MASK 0x00000100
  131. #define DEVICE_PLLCTL_PLLEN_MASK 0x00000001
  132. #define DEVICE_PLLCTL_PLLPWRDN_MASK 0x00000002
  133. #define DEVICE_PLLCTL_PLLRST_MASK 0x00000008
  134. #define DEVICE_PLLCTL_PLLDIS_MASK 0x00000010
  135. #define DEVICE_PLLCTL_PLLENSRC_MASK 0x00000020
  136. #define DEVICE_PLLCMD_GOSET_MASK 0x00000001
  137. #define DEVICE_PLLSTAT_GOSTAT_MASK 0x00000001
  138. #define DEVICE_PLLDIV_EN_MASK 0x00008000
  139. #define DEVICE_PLLSTAT_LOCK_MASK 0x00000002
  140. /* -------------------------------------------------------------------------- *
  141. * Power/Sleep Ctrl Register structure - See sprue14.pdf, Chapter 7 *
  142. * for more details. *
  143. * -------------------------------------------------------------------------- */
  144. struct psc_regs_t {
  145. uint32_t PID; // 0x000
  146. uint32_t RSVD0[3]; // 0x004
  147. uint32_t GBLCTL; // 0x010 - NOT ON DM35x
  148. uint32_t RSVD1; // 0x014
  149. uint32_t INTEVAL; // 0x018
  150. uint32_t RSVD2[9]; // 0x01C
  151. uint32_t MERRPR0; // 0x040
  152. uint32_t MERRPR1; // 0x044
  153. uint32_t RSVD3[2]; // 0x048
  154. uint32_t MERRCR0; // 0x050
  155. uint32_t MERRCR1; // 0x054
  156. uint32_t RSVD4[2]; // 0x058
  157. uint32_t PERRPR; // 0x060
  158. uint32_t RSVD5; // 0x064
  159. uint32_t PERRCR; // 0x068
  160. uint32_t RSVD6; // 0x06C
  161. uint32_t EPCPR; // 0x070
  162. uint32_t RSVD7; // 0x074
  163. uint32_t EPCCR; // 0x078
  164. uint32_t RSVD8[33]; // 0x07C
  165. uint32_t RAILSTAT; // 0x100 - NOT ON DM35x
  166. uint32_t RAILCTL; // 0x104 - NOT ON DM35x
  167. uint32_t RAILSEL; // 0x108 - NOT ON DM35x
  168. uint32_t RSVD9[5]; // 0x10C
  169. uint32_t PTCMD; // 0x120
  170. uint32_t RSVD10; // 0x124
  171. uint32_t PTSTAT; // 0x128
  172. uint32_t RSVD11[53]; // 0x12C
  173. uint32_t PDSTAT0; // 0x200
  174. uint32_t PDSTAT1; // 0x204
  175. uint32_t RSVD12[62]; // 0x208
  176. uint32_t PDCTL0; // 0x300
  177. uint32_t PDCTL1; // 0x304
  178. uint32_t RSVD13[134]; // 0x308
  179. uint32_t MCKOUT0; // 0x520
  180. uint32_t MCKOUT1; // 0x524
  181. uint32_t RSVD14[182]; // 0x528
  182. uint32_t MDSTAT[41]; // 0x800
  183. uint32_t RSVD15[87]; // 0x8A4
  184. uint32_t MDCTL[41]; // 0xA00
  185. };
  186. #define PSC ((volatile struct psc_regs_t*) 0x01C41000)
  187. #if defined(DM644x)
  188. /* See TMS320DM6446 errata 1.3.22 */
  189. #define PSC_PTSTAT_WORKAROUND_REG (*((volatile uint32_t*) 0x01C41A20))
  190. #endif
  191. #define PD0 0
  192. /* PSC constants */
  193. #define LPSC_VPSS_MAST 0
  194. #define LPSC_VPSS_SLV 1
  195. #define LPSC_EDMACC 2
  196. #define LPSC_EDMATC0 3
  197. #define LPSC_EDMATC1 4
  198. #if defined(DM644x)
  199. #define LPSC_EMAC 5
  200. #define LPSC_EMAC_MEM_CTL 6
  201. #define LPSC_MDIO 7
  202. #define LPSC_RESERVED0 8
  203. #elif defined(DM35x)
  204. #define LPSC_TIMER3 5
  205. #define LPSC_SPI1 6
  206. #define LPSC_MMC_SD1 7
  207. #define LPSC_ASP1 8
  208. #endif
  209. #define LPSC_USB 9
  210. #if defined(DM644x)
  211. #define LPSC_ATA 10
  212. #define LPSC_VLYNQ 11
  213. #define LPSC_HPI 12
  214. #elif defined(DM35x)
  215. #define LPSC_PWM3 10
  216. #define LPSC_SPI2 11
  217. #define LPSC_RTO 12
  218. #endif
  219. #define LPSC_DDR2 13
  220. #define LPSC_AEMIF 14
  221. #define LPSC_MMC_SD0 15
  222. #if defined(DM644x)
  223. #define LPSC_RESERVED1 16
  224. #elif defined(DM35x)
  225. #define LPSC_MEMSTK 16
  226. #endif
  227. #define LPSC_ASP0 17
  228. #define LPSC_I2C 18
  229. #define LPSC_UART0 19
  230. #if defined(DM35x)
  231. #define LPSC_UART1 20
  232. #define LPSC_UART2 21
  233. #define LPSC_SPIO 22
  234. #define LPSC_PWM0 23
  235. #define LPSC_PWM1 24
  236. #define LPSC_PWM2 25
  237. #endif
  238. #define LPSC_GPIO 26
  239. #define LPSC_TIMER0 27
  240. #define LPSC_TIMER1 28
  241. #if defined(DM35x)
  242. #define LPSC_TIMER2 29
  243. #define LPSC_SYSMOD 30
  244. #endif
  245. #define LPSC_ARM 31
  246. #if defined(DM644x)
  247. #define LPSC_DSP 39
  248. #define LPSC_IMCOP 40
  249. #elif defined(DM35x)
  250. #define LPSC_VPSS_DAC 40
  251. #endif
  252. #define EMURSTIE_MASK 0x00000200
  253. #define PSC_ENABLE 0x3
  254. #define PSC_DISABLE 0x2
  255. #define PSC_SYNCRESET 0x1
  256. #define PSC_SWRSTDISABLE 0x0
  257. /* -------------------------------------------------------------------------- *
  258. * DDR2 Memory Ctrl Register structure - See sprue22b.pdf for more details.*
  259. * -------------------------------------------------------------------------- */
  260. struct ddr_mem_ctl_regs_t {
  261. uint32_t RSVD0;
  262. uint32_t SDRSTAT;
  263. uint32_t SDBCR;
  264. uint32_t SDRCR;
  265. uint32_t SDTIMR;
  266. uint32_t SDTIMR2;
  267. #if defined(DM644x)
  268. uint32_t RSVD1[2];
  269. #elif defined(DM35x)
  270. uint32_t RSVD1;
  271. uint32_t SDBCR2;
  272. #endif
  273. uint32_t PBBPR; /* 0x20 */
  274. uint32_t RSVD2[39];
  275. uint32_t IRR; /* 0xC0 */
  276. uint32_t IMR;
  277. uint32_t IMSR;
  278. uint32_t IMCR;
  279. uint32_t RSVD3[5];
  280. uint32_t DDRPHYCR;
  281. uint32_t RSVD4[2];
  282. #if defined(DM644x)
  283. uint32_t VTPIOCR; /* 0xF0 - In system control module for DM35x */
  284. #endif
  285. };
  286. #define DDR ((volatile struct ddr_mem_ctl_regs_t *) 0x20000000)
  287. #define DDR_TEST_PATTERN 0xA55AA55A
  288. #define SDBCR_TIMUNLOCK (1 << 15)
  289. #if defined(DM644x)
  290. #define DDRVTPR (*((volatile uint32_t*) 0x01C42030))
  291. #define DDRPHYCR_DEFAULT 0x50006400 /* Default value with reserved fields */
  292. #define DDRPHYCR_READLAT_MASK (0x7 << 0)
  293. #define SDBCR_DEFAULT 0x00130000 /* Default value with reserved fields */
  294. #elif defined(DM35x)
  295. #define DDRPHYCR_DEFAULT 0x28006400 /* Default value with reserved fields */
  296. #define DDRPHYCR_READLAT_MASK (0xF << 0)
  297. #define SDBCR_DEFAULT 0x00170000 /* Default value with reserved fields */
  298. #endif
  299. /* -------------------------------------------------------------------------- *
  300. * AEMIF Register structure - See sprue20a.pdf for more details. *
  301. * -------------------------------------------------------------------------- */
  302. struct emif_regs_t {
  303. uint32_t ERCSR; // 0x00
  304. uint32_t AWCCR; // 0x04
  305. uint32_t SDBCR; // 0x08 - NOT ON DM35x
  306. uint32_t SDRCR; // 0x0C - NOT ON DM35x
  307. uint32_t A1CR; // 0x10
  308. uint32_t A2CR; // 0x14
  309. uint32_t A3CR; // 0x18 - NOT ON DM35x
  310. uint32_t A4CR; // 0x1C - NOT ON DM35x
  311. uint32_t SDTIMR; // 0x20 - NOT ON DM35x
  312. uint32_t DDRSR; // 0x24 - NOT ON DM35x
  313. uint32_t DDRPHYCR; // 0x28 - NOT ON DM35x
  314. uint32_t DDRPHYSR; // 0x2C - NOT ON DM35x
  315. uint32_t TOTAR; // 0x30 - NOT ON DM35x
  316. uint32_t TOTACTR; // 0x34 - NOT ON DM35x
  317. uint32_t DDRPHYID_REV; // 0x38 - NOT ON DM35x
  318. uint32_t SDSRETR; // 0x3C - NOT ON DM35x
  319. uint32_t EIRR; // 0x40
  320. uint32_t EIMR;
  321. uint32_t EIMSR;
  322. uint32_t EIMCR;
  323. uint32_t IOCTRLR; // 0x50 - NOT ON DM35x
  324. uint32_t IOSTATR; // 0x54 - NOT ON DM35x
  325. uint32_t RSVD0;
  326. uint32_t ONENANDCTL; // 0x5C - ONLY ON DM35x
  327. uint32_t NANDFCR; // 0x60
  328. uint32_t NANDFSR; // 0x64
  329. uint32_t RSVD1[2];
  330. uint32_t NANDF1ECC; // 0x70
  331. uint32_t NANDF2ECC; // 0x74
  332. uint32_t NANDF3ECC; // 0x78 - NOT ON DM35x
  333. uint32_t NANDF4ECC; // 0x7C - NOT ON DM35x
  334. uint32_t RSVD2; // 0x80
  335. uint32_t IODFTECR;
  336. uint32_t IODFTGCR;
  337. uint32_t RSVD3;
  338. uint32_t IODFTMRLR; // 0x90
  339. uint32_t IODFTMRMR; // 0x94
  340. uint32_t IODFTMRMSBR; // 0x98
  341. uint32_t RSVD4[5];
  342. uint32_t MODRNR; // 0xB0
  343. uint32_t RSVD5[2];
  344. uint32_t NAND4BITECCLOAD; // 0xBC - ONLY ON DM35x
  345. uint32_t NAND4BITECC1; // 0xC0 - ONLY ON DM35x
  346. uint32_t NAND4BITECC2; // 0xC4 - ONLY ON DM35x
  347. uint32_t NAND4BITECC3; // 0xC8 - ONLY ON DM35x
  348. uint32_t NAND4BITECC4; // 0xCC - ONLY ON DM35x
  349. uint32_t NANDERRADD1; // 0xD0 - ONLY ON DM35x
  350. uint32_t NANDERRADD2; // 0xD4 - ONLY ON DM35x
  351. uint32_t NANDERRVAL1; // 0xD8 - ONLY ON DM35x
  352. uint32_t NANDERRVAL2; // 0xDC - ONLY ON DM35x
  353. };
  354. #if defined(DM644x)
  355. #define AEMIF ((volatile struct emif_regs_t *) 0x01E00000)
  356. #elif defined(DM35x)
  357. #define AEMIF ((volatile struct emif_regs_t *) 0x01E10000)
  358. #endif
  359. /* -------------------------------------------------------------------------- *
  360. * UART Register structure - See sprue33.pdf for more details. *
  361. * -------------------------------------------------------------------------- */
  362. struct uart_regs_t {
  363. uint32_t RBR;
  364. uint32_t IER;
  365. uint32_t IIR;
  366. uint32_t LCR;
  367. uint32_t MCR;
  368. uint32_t LSR;
  369. uint32_t MSR; /* NOT ON DM35x */
  370. uint32_t SCR; /* NOT ON DM35x */
  371. uint32_t DLL;
  372. uint32_t DLH;
  373. uint32_t PID1;
  374. uint32_t PID2;
  375. uint32_t PWREMU_MGNT;
  376. };
  377. #define THR RBR
  378. #define FCR IIR
  379. #define UART0 ((volatile struct uart_regs_t *) 0x01C20000)
  380. #define UART_BCLK_RATIO 16 /* BCLK is 16 times the baudrate */
  381. #define UART_BAUDRATE 115200
  382. /* -------------------------------------------------------------------------- *
  383. * Timer Register structure - See sprue26.pdf for more details. *
  384. * -------------------------------------------------------------------------- */
  385. struct timer_regs_t {
  386. uint32_t PID12;
  387. uint32_t EMUMGT_CLKSPD;
  388. uint32_t GPINT_GPEN; // NOT ON DM35x
  389. uint32_t GPTDAT_GPDIR; // NOT ON DM35x
  390. uint32_t TIM12;
  391. uint32_t TIM34;
  392. uint32_t PRD12;
  393. uint32_t PRD34;
  394. uint32_t TCR;
  395. uint32_t TGCR;
  396. uint32_t WDTCR;
  397. uint32_t RSVD1[3]; // 0x2C - ONLY ON DM35x
  398. uint32_t REL12; // 0x34 - ONLY ON DM35x
  399. uint32_t REL34; // 0x38 - ONLY ON DM35x
  400. uint32_t CAP12; // 0x3C - ONLY ON DM35x
  401. uint32_t CAP34; // 0x40 - ONLY ON DM35x
  402. uint32_t INTCTL_STAT; // 0x44 - ONLY ON DM35x
  403. };
  404. #define TIMER0 ((volatile struct timer_regs_t *) 0x01C21400)
  405. struct gpio_controller {
  406. uint32_t dir;
  407. uint32_t out_data;
  408. uint32_t set_data;
  409. uint32_t clr_data;
  410. uint32_t in_data;
  411. uint32_t set_rising;
  412. uint32_t clr_rising;
  413. uint32_t set_falling;
  414. uint32_t clr_falling;
  415. uint32_t intstat;
  416. };
  417. #define DAVINCI_GPIO_BASE 0x01C67000
  418. #define GPIOC ((volatile struct gpio_controller *) DAVINCI_GPIO_BASE)
  419. int davinci_platform_init(char *version);
  420. void ddr_vtp_calibration(void);
  421. void timer0_start(uint32_t period);
  422. uint32_t timer0_status(void);
  423. void timer0_settimeout(uint8_t timeout);
  424. int timer0_setdefault_timeout(void);
  425. #endif /* _DAVINCI_H_ */