Primary Bootloader (before u-boot) in sysmoBTSv2
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  1. /*
  2. * davinci.c - common DaVinci platform initialization
  3. *
  4. * Copyright (C) 2008 Hugo Villeneuve <hugo@hugovil.com>
  5. *
  6. * Based on TI DaVinci Flash and Boot Utilities, original copyright follows:
  7. * Copyright 2008 Texas Instruments, Inc. <www.ti.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  22. */
  23. #include "common.h"
  24. #include "davinci.h"
  25. #include "ddr.h"
  26. #include "util.h"
  27. #include "uart.h"
  28. #include "gpio.h"
  29. extern enum bootmode_t bootmode;
  30. extern const int8_t lpsc_en_list[];
  31. extern const int8_t lpsc_emurstie_list[];
  32. extern const size_t lpsc_en_list_len;
  33. extern const size_t lpsc_emurstie_list_len;
  34. /* Table of supported PLL settings */
  35. #define PLL_DAVINCI_594_CFG 0
  36. #define PLL_DAVINCI_810_CFG 1
  37. static const struct pll_settings_t pll1_settings[] = {
  38. { 22 }, /* DSP=594 MHz ARM=297 MHz */
  39. { 30 }, /* DSP=810 MHz ARM=405 MHz */
  40. };
  41. static const struct pll_settings_t pll2_settings[] = {
  42. { 24 }, /* DDRPHY=324 MHz DDRCLK=162 MHz */
  43. { 28 }, /* DDRPHY=378 MHz DDRCLK=189 MHz */
  44. };
  45. /* Table of supported DDR devices */
  46. #define DDR_MT47H32M16BN_3_162MHz_CFG 0
  47. #define DDR_MT47H64M16HR_3IT_162MHz_CFG 1
  48. #define DDR_MT47H64M16HR_3IT_189MHz_CFG 2
  49. static const struct ddr_timing_infos_t ddr_timing_infos[] = {
  50. {
  51. /* Micron MT47H32M16BN-3 @ 162 MHz settings:
  52. * TCK = 6.17 nS -> 1 / 162 MHz
  53. * T_REF = 7.8 uS (varies with commercial vs industrial)
  54. * T_RFC = 105 nS (varies with capacity)
  55. * T_RP = 15 nS
  56. * T_RCD = 15 nS
  57. * T_WR = 15 nS
  58. * T_RAS = 40 nS
  59. * T_RASMAX = 70 uS
  60. * T_RTP = 7.5 nS
  61. * T_RC = 55 nS
  62. * T_RRD = 10 nS
  63. * T_WTR = 7.5 nS
  64. * T_XSRD = 200 nS
  65. * T_XSNR = 115 nS -> T_RFC(MIN) + 10
  66. * T_CKE = 3 TCK
  67. * T_XP = 2 TCK
  68. */
  69. .SDBCR = SDBCR_DEFAULT
  70. | (0 << 14) /* NM = 0; {32-bit bus with} */
  71. | (3 << 9) /* CL = 3; */
  72. | (2 << 4) /* IBANK = 2; {4 banks} */
  73. | (2 << 0), /* PAGESIZE = 2; {1024-word} */
  74. .SDTIMR = (16 << 25) /* T_RFC = 16; {(T_RFC * DDRCLK) - 1} */
  75. | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */
  76. | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */
  77. | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */
  78. | ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */
  79. | ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */
  80. | ( 1 << 3) /* T_RRD = 1; {(T_RRD * DDRCLK) - 1} */
  81. | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */
  82. .SDTIMR2 = ( 18 << 16) /* T_XSNR = 18; {(T_XSNR * DDRCLK) - 1} */
  83. | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */
  84. | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */
  85. | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */
  86. .SDRCR = 1265, /* RR = 1265; {DDRCLK * T_REF} */
  87. .READ_Latency = 4,
  88. },
  89. {
  90. /* Micron MT47H64M16HR-3IT @ 162 MHz settings:
  91. * TCK = 6.17 nS -> 1 / 162 MHz
  92. * T_REF = 3.9 uS (varies with commercial vs industrial)
  93. * T_RFC = 127.5 nS (varies with capacity)
  94. * T_RP = 15 nS
  95. * T_RCD = 15 nS
  96. * T_WR = 15 nS
  97. * T_RAS = 40 nS
  98. * T_RASMAX = 70 uS
  99. * T_RTP = 7.5 nS
  100. * T_RC = 55 nS
  101. * T_RRD = 10 nS
  102. * T_WTR = 7.5 nS
  103. * T_XSRD = 200 nS
  104. * T_XSNR = 138 nS -> T_RFC(MIN) + 10
  105. * T_CKE = 3 TCK
  106. * T_XP = 2 TCK
  107. */
  108. .SDBCR = SDBCR_DEFAULT
  109. | (0 << 14) /* NM = 0; {32-bit bus with} */
  110. | (3 << 9) /* CL = 3; */
  111. | (3 << 4) /* IBANK = 3; {8 banks} */
  112. | (2 << 0), /* PAGESIZE = 2; {1024-word} */
  113. .SDTIMR = (20 << 25) /* T_RFC = 20; {(T_RFC * DDRCLK) - 1} */
  114. | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */
  115. | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */
  116. | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */
  117. | ( 6 << 11) /* T_RAS = 6; {(T_RAS * DDRCLK) - 1} */
  118. | ( 8 << 6) /* T_RC = 8; {(T_RC * DDRCLK) - 1} */
  119. | ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */
  120. | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */
  121. .SDTIMR2 = ( 32 << 16) /* T_XSNR = 32; {(T_XSNR * DDRCLK) - 1} */
  122. | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */
  123. | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */
  124. | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */
  125. .SDRCR = 632, /* RR = 632; {DDRCLK * T_REF} */
  126. .READ_Latency = 4,
  127. },
  128. {
  129. /* Micron MT47H64M16HR-3IT @ 189 MHz settings:
  130. * TCK = 5.291 nS -> 1 / 189 MHz
  131. * T_REF = 3.9 uS (varies with commercial vs industrial)
  132. * T_RFC = 127.5 nS (varies with capacity)
  133. * T_RP = 15 nS
  134. * T_RCD = 15 nS
  135. * T_WR = 15 nS
  136. * T_RAS = 40 nS
  137. * T_RASMAX = 70 uS
  138. * T_RTP = 7.5 nS
  139. * T_RC = 55 nS
  140. * T_RRD = 10 nS
  141. * T_WTR = 7.5 nS
  142. * T_XSRD = 200 nS
  143. * T_XSNR = 138 nS -> T_RFC(MIN) + 10
  144. * T_CKE = 3 TCK
  145. * T_XP = 2 TCK
  146. */
  147. .SDBCR = SDBCR_DEFAULT
  148. | (0 << 14) /* NM = 0; {32-bit bus with} */
  149. | (3 << 9) /* CL = 3; */
  150. | (3 << 4) /* IBANK = 3; {8 banks} */
  151. | (2 << 0), /* PAGESIZE = 2; {1024-word} */
  152. .SDTIMR = (24 << 25) /* T_RFC = 24; {(T_RFC * DDRCLK) - 1} */
  153. | ( 2 << 22) /* T_RP = 2; {(T_RP * DDRCLK) - 1} */
  154. | ( 2 << 19) /* T_RCD = 2; {(T_RCD * DDRCLK) - 1} */
  155. | ( 2 << 16) /* T_WR = 2; {(T_WR * DDRCLK) - 1} */
  156. | ( 7 << 11) /* T_RAS = 7; {(T_RAS * DDRCLK) - 1} */
  157. | (10 << 6) /* T_RC = 10; {(T_RC * DDRCLK) - 1} */
  158. | ( 2 << 3) /* T_RRD = 2; {[((4 * T_RRD) + (2 * TCK)) / (4 * TCK)] - 1} */
  159. | ( 1 << 0), /* T_WTR = 1; {(T_WTR * DDRCLK) - 1} */
  160. .SDTIMR2 = ( 26 << 16) /* T_XSNR = 26; {(T_XSNR * DDRCLK) - 1} */
  161. | (199 << 8) /* T_XSRD = 199; {T_XSRD - 1} */
  162. | ( 1 << 5) /* T_RTP = 1; {(T_RTP * DDRCLK) - 1} */
  163. | ( 2 << 0), /* T_CKE = 2; {T_CKE - 1} */
  164. .SDRCR = 738, /* RR = 738; {DDRCLK * T_REF} */
  165. .READ_Latency = 4,
  166. }
  167. };
  168. /* Symbol from linker script */
  169. extern uint32_t __DDR_START;
  170. uint32_t DDR_SIZE = (128 << 20);
  171. static void
  172. pinmuxControl(uint32_t regOffset, uint32_t mask, uint32_t value)
  173. {
  174. SYSTEM->PINMUX[regOffset] &= ~mask;
  175. SYSTEM->PINMUX[regOffset] |= (mask & value);
  176. }
  177. static void
  178. lpsc_tansition(uint8_t module, uint8_t domain, uint8_t state)
  179. {
  180. /* Wait for any outstanding transition to complete */
  181. while ((PSC->PTSTAT) & (0x00000001 << domain))
  182. ;
  183. /* If we are already in that state, just return */
  184. if (((PSC->MDSTAT[module]) & 0x1F) == state)
  185. return;
  186. /* Perform transition */
  187. PSC->MDCTL[module] = ((PSC->MDCTL[module]) & (0xFFFFFFE0)) | (state);
  188. PSC->PTCMD |= (0x00000001 << domain);
  189. /* Wait for transition to complete */
  190. while ((PSC->PTSTAT) & (0x00000001 << domain))
  191. ;
  192. /* Wait and verify the state */
  193. while (((PSC->MDSTAT[module]) & 0x1F) != state)
  194. ;
  195. }
  196. static void
  197. ivt_init(void)
  198. {
  199. volatile uint32_t *ivect;
  200. extern uint32_t __IVT;
  201. if (bootmode == NON_SECURE_NOR) {
  202. ivect = &(__IVT);
  203. *ivect++ = 0xEAFFFFFE; /* Reset @ 0x00*/
  204. } else
  205. ivect = &(__IVT) + 4;
  206. *ivect++ = 0xEAFFFFFE; /* Undefined Address @ 0x04 */
  207. *ivect++ = 0xEAFFFFFE; /* Software Interrupt @0x08 */
  208. *ivect++ = 0xEAFFFFFE; /* Pre-Fetch Abort @ 0x0C */
  209. *ivect++ = 0xEAFFFFFE; /* Data Abort @ 0x10 */
  210. *ivect++ = 0xEAFFFFFE; /* Reserved @ 0x14 */
  211. *ivect++ = 0xEAFFFFFE; /* IRQ @ 0x18 */
  212. *ivect = 0xEAFFFFFE; /* FIQ @ 0x1C */
  213. }
  214. static int
  215. timer0_init(uint8_t timeout)
  216. {
  217. TIMER0->TGCR = 0x00000000; /* Reset timer */
  218. TIMER0->TCR = 0x00000000; /* Disable timer */
  219. TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
  220. /* Set timer period (5 seconds timeout) */
  221. TIMER0->PRD12 = SYSTEM_CLK_HZ * timeout;
  222. return E_PASS;
  223. }
  224. void
  225. timer0_start(uint32_t period)
  226. {
  227. TIMER0->TGCR = 0x00000000; /* Reset timer */
  228. TIMER0->TCR = 0x00000000; /* Disable timer */
  229. TIMER0->PRD12 = period;
  230. AINTC->IRQ1 |= 0x00000001; /* Clear interrupt */
  231. TIMER0->TIM12 = 0x00000000; /* Reset timer count to zero */
  232. TIMER0->TCR = 0x00000040; /* Setup for one-shot mode */
  233. TIMER0->TGCR = 0x00000005; /* Start TIMER12 in 32-bits mode. */
  234. }
  235. void
  236. timer0_settimeout(uint8_t timeout)
  237. {
  238. timer0_init(timeout);
  239. }
  240. int
  241. timer0_setdefault_timeout()
  242. {
  243. return timer0_init(5);
  244. }
  245. uint32_t
  246. timer0_status(void)
  247. {
  248. return AINTC->IRQ1 & 0x1;
  249. }
  250. static int
  251. uart0_init(void)
  252. {
  253. UART0->PWREMU_MGNT = 0; /* Reset UART TX & RX components */
  254. waitloop(100);
  255. /* Set DLAB bit - allows setting of clock divisors */
  256. UART0->LCR |= 0x80;
  257. /*
  258. * Compute divisor value. Normally, we should simply return:
  259. * SYSTEM_CLK_HZ / (16 * baudrate)
  260. * but we need to round that value by adding 0.5.
  261. * Rounding is especially important at high baud rates.
  262. */
  263. UART0->DLL = (SYSTEM_CLK_HZ + (UART_BAUDRATE * (UART_BCLK_RATIO / 2))) /
  264. (UART_BCLK_RATIO * UART_BAUDRATE);
  265. UART0->DLH = 0x00;
  266. UART0->FCR = 0x0007; /* Clear UART TX & RX FIFOs */
  267. UART0->MCR = 0x0000; /* RTS & CTS disabled,
  268. * Loopback mode disabled,
  269. * Autoflow disabled
  270. */
  271. UART0->LCR = 0x0003; /* Clear DLAB bit
  272. * 8-bit words,
  273. * 1 STOP bit generated,
  274. * No Parity, No Stick paritiy,
  275. * No Break control
  276. */
  277. /* Enable receiver, transmitter, set to run. */
  278. UART0->PWREMU_MGNT |= 0x6001;
  279. return E_PASS;
  280. }
  281. static int
  282. pll_init(volatile struct pll_regs_t *pll, int pll_mult, int plldiv_ratio[5])
  283. {
  284. int k;
  285. volatile uint32_t *plldiv_reg[5];
  286. int pll_is_powered_up =
  287. (pll->PLLCTL & DEVICE_PLLCTL_PLLPWRDN_MASK) >> 1;
  288. plldiv_reg[0] = &pll->PLLDIV1;
  289. plldiv_reg[1] = &pll->PLLDIV2;
  290. plldiv_reg[2] = &pll->PLLDIV3;
  291. plldiv_reg[3] = &pll->PLLDIV4;
  292. plldiv_reg[4] = &pll->PLLDIV5;
  293. /* Set PLL clock input to internal osc. */
  294. pll->PLLCTL &= ~(DEVICE_PLLCTL_CLKMODE_MASK);
  295. /* Set PLL to bypass, then wait for PLL to stabilize */
  296. pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLENSRC_MASK |
  297. DEVICE_PLLCTL_PLLEN_MASK);
  298. waitloop(150);
  299. /* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */
  300. #if defined(DM644x)
  301. pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK;
  302. #elif defined(DM35x)
  303. pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK;
  304. #endif
  305. if (pll_is_powered_up) {
  306. /* Disable PLL */
  307. pll->PLLCTL |= DEVICE_PLLCTL_PLLDIS_MASK;
  308. /* Powerup PLL */
  309. pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLPWRDN_MASK);
  310. }
  311. /* Enable PLL */
  312. pll->PLLCTL &= ~(DEVICE_PLLCTL_PLLDIS_MASK);
  313. /* Wait for PLL to stabilize */
  314. waitloop(150);
  315. /* Load PLL multiplier. */
  316. pll->PLLM = (pll_mult - 1) & 0xff;
  317. /* Set and enable dividers as needed. */
  318. for (k = 0; k < 5; k++) {
  319. if (plldiv_ratio[k] > 0)
  320. *(plldiv_reg[k]) |= DEVICE_PLLDIV_EN_MASK |
  321. (plldiv_ratio[k] - 1);
  322. }
  323. #if defined(DM35x)
  324. /* Set the processor AIM wait state and PLL1 post-divider to to 1 */
  325. SYSTEM->MISC &= ~(DEVICE_MISC_PLL1POSTDIV_MASK |
  326. DEVICE_MISC_AIMWAITST_MASK);
  327. #endif
  328. /* Initiate a new divider transition. */
  329. pll->PLLCMD |= DEVICE_PLLCMD_GOSET_MASK;
  330. /* Wait for completion of phase alignment. */
  331. while ((pll->PLLSTAT & DEVICE_PLLSTAT_GOSTAT_MASK))
  332. ;
  333. /* Wait for PLL to reset ( ~5 usec ) */
  334. waitloop(5000);
  335. /* Release PLL from reset */
  336. /* Reset PLL: Warning, bit state is inverted for DM644x vs DM35x. */
  337. #if defined(DM644x)
  338. pll->PLLCTL |= DEVICE_PLLCTL_PLLRST_MASK;
  339. #elif defined(DM35x)
  340. pll->PLLCTL &= ~DEVICE_PLLCTL_PLLRST_MASK;
  341. #endif
  342. /* Wait for PLL to re-lock:
  343. * DM644z: 2000P
  344. * DM35x: 8000P
  345. */
  346. waitloop(8000);
  347. /* Switch out of BYPASS mode */
  348. pll->PLLCTL |= DEVICE_PLLCTL_PLLEN_MASK;
  349. return E_PASS;
  350. }
  351. static int
  352. pll1_init(int cfg)
  353. {
  354. int plldiv_ratio[5];
  355. #if defined(DM644x)
  356. plldiv_ratio[0] = 1; /* PLLDIV1 fixed */
  357. plldiv_ratio[1] = 2; /* PLLDIV2 fixed */
  358. plldiv_ratio[2] = 3; /* PLLDIV3 fixed */
  359. plldiv_ratio[3] = -1; /* PLLDIV4 not used */
  360. plldiv_ratio[4] = 6; /* PLLDIV5 fixed */
  361. #elif defined(DM35x)
  362. plldiv_ratio[0] = 2; /* PLLDIV1 fixed */
  363. plldiv_ratio[1] = 4; /* PLLDIV2 fixed */
  364. /* Calculate PLL divider ratio for divider 3 (feeds VPBE) */
  365. plldiv_ratio[2] = 0;
  366. while ((plldiv_ratio[2] * VPBE_CLK_HZ) <
  367. (SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3)))
  368. plldiv_ratio[2]++;
  369. /* Check to make sure we can supply accurate VPBE clock */
  370. if ((plldiv_ratio[2] * VPBE_CLK_HZ) !=
  371. (SYSTEM_CLK_HZ * (pll1_settings[cfg].mult >> 3)))
  372. return E_FAIL;
  373. /* See the device datasheet for more info (must be 2 or 4) */
  374. plldiv_ratio[3] = 4;
  375. plldiv_ratio[4] = -1; /* PLLDIV5 not used */
  376. #endif
  377. return pll_init(PLL1, pll1_settings[cfg].mult, plldiv_ratio);
  378. }
  379. static int
  380. pll2_init(int cfg)
  381. {
  382. int plldiv_ratio[5];
  383. plldiv_ratio[0] = PLL2_Div1;
  384. plldiv_ratio[1] = PLL2_Div2;
  385. plldiv_ratio[2] = -1; /* PLLDIV3 not used */
  386. plldiv_ratio[3] = -1; /* PLLDIV4 not used */
  387. plldiv_ratio[4] = -1; /* PLLDIV5 not used */
  388. return pll_init(PLL2, pll2_settings[cfg].mult, plldiv_ratio);
  389. }
  390. static void
  391. ddr_timing_setup(int cfg)
  392. {
  393. /* The configuration of DDRPHYCR is not dependent on the DDR2 device
  394. * specification but rather on the board layout.
  395. * Setup the read latency and clear DLLPWRDN */
  396. DDR->DDRPHYCR = DDRPHYCR_DEFAULT |
  397. (ddr_timing_infos[cfg].READ_Latency & DDRPHYCR_READLAT_MASK);
  398. /*
  399. * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
  400. * as suggested in TMS320DM6446 errata 2.1.2:
  401. *
  402. * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
  403. * low priority modules can occupy the bus and prevent high priority
  404. * modules like the VPSS from getting the required DDR2 throughput.
  405. */
  406. DDR->PBBPR = DDR_PBBPR_PR_OLD_COUNT;
  407. /* TIMUNLOCK (unlocked), CAS Latency, number of banks and page size */
  408. DDR->SDBCR = SDBCR_TIMUNLOCK | ddr_timing_infos[cfg].SDBCR;
  409. /* Program timing registers */
  410. DDR->SDTIMR = ddr_timing_infos[cfg].SDTIMR;
  411. DDR->SDTIMR2 = ddr_timing_infos[cfg].SDTIMR2;
  412. /* Clear the TIMUNLOCK bit (locked) */
  413. DDR->SDBCR &= ~SDBCR_TIMUNLOCK;
  414. /* Set the refresh rate */
  415. DDR->SDRCR = ddr_timing_infos[cfg].SDRCR;
  416. }
  417. static void
  418. ddr_reset(void)
  419. {
  420. /* Perform a soft reset to the DDR2 memory controller:
  421. * Put in SYNCRESET and enable it again. */
  422. lpsc_tansition(LPSC_DDR2, PD0, PSC_SYNCRESET);
  423. lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE);
  424. }
  425. static int
  426. ddr_init(int cfg)
  427. {
  428. volatile uint32_t *ddr_start = &__DDR_START;
  429. /* For reading/writing dummy value in order to apply timing settings */
  430. volatile uint32_t ddr_dummy_read;
  431. /* Enable DDR2 module. */
  432. lpsc_tansition(LPSC_DDR2, PD0, PSC_ENABLE);
  433. #if defined(DM35x)
  434. ddr_vtp_calibration();
  435. ddr_reset();
  436. #endif
  437. ddr_timing_setup(cfg);
  438. /* Dummy read to apply timing settings */
  439. ddr_dummy_read = ddr_start[0];
  440. #if defined(DM644x)
  441. ddr_reset();
  442. ddr_vtp_calibration();
  443. #endif
  444. /* Verify correct initialization. */
  445. ddr_start[0] = DDR_TEST_PATTERN;
  446. if (ddr_start[0] != DDR_TEST_PATTERN) {
  447. log_fail("DDR init failed");
  448. return E_FAIL;
  449. }
  450. return E_PASS;
  451. }
  452. static void
  453. psc_init(void)
  454. {
  455. uint32_t i;
  456. #if defined(DM35x)
  457. /* Do always on power domain transitions */
  458. while ((PSC->PTSTAT) & 0x00000001);
  459. #elif defined(DM644x)
  460. /*
  461. * Workaround for TMS320DM6446 errata 1.3.22
  462. * (Revision(s) Affected: 1.3 and earlier):
  463. * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset.
  464. * Clear the reserved location at address 0x01C41A20
  465. */
  466. PSC_PTSTAT_WORKAROUND_REG = 0;
  467. /* Put the C64x+ Core into reset (if it's on) */
  468. PSC->MDCTL[LPSC_DSP] &= (~0x00000100);
  469. PSC->PTCMD |= 0x00000002;
  470. while ((PSC->PTSTAT) & (0x00000002));
  471. while ((PSC->MDSTAT[LPSC_DSP]) & (0x00000100));
  472. #endif
  473. /* Enable selected modules */
  474. for (i = 0; i < lpsc_en_list_len; i++) {
  475. int8_t k = lpsc_en_list[i];
  476. PSC->MDCTL[k] = (PSC->MDCTL[k] & 0xFFFFFFE0) | PSC_ENABLE;
  477. }
  478. /* Set EMURSTIE on selected modules */
  479. for (i = 0; i < lpsc_emurstie_list_len; i++) {
  480. int8_t k = lpsc_emurstie_list[i];
  481. PSC->MDCTL[k] |= EMURSTIE_MASK;
  482. }
  483. /* Do Always-On Power Domain Transitions */
  484. PSC->PTCMD |= 0x00000001;
  485. while ((PSC->PTSTAT) & 0x00000001);
  486. #if defined(DM644x)
  487. /* DO DSP Power Domain Transitions */
  488. PSC->PTCMD |= 0x00000002;
  489. while ((PSC->PTSTAT) & (0x00000002));
  490. #endif
  491. /* Clear EMURSTIE on selected modules */
  492. for (i = 0; i < lpsc_emurstie_list_len; i++) {
  493. int8_t k = lpsc_emurstie_list[i];
  494. PSC->MDCTL[k] &= (~EMURSTIE_MASK);
  495. }
  496. }
  497. int
  498. davinci_platform_init(char *version)
  499. {
  500. int pllCfg;
  501. int ddrCfg;
  502. int status = E_PASS;
  503. unsigned *gpio01 = (unsigned *)(DAVINCI_GPIO_BASE + 0x20);
  504. psc_init();
  505. /* Disable ARM interrupts */
  506. AINTC->INTCTL = 0x0;
  507. AINTC->EABASE = 0x0;
  508. AINTC->EINT0 = 0x0;
  509. AINTC->EINT1 = 0x0;
  510. AINTC->FIQ0 = 0xFFFFFFFF;
  511. AINTC->FIQ1 = 0xFFFFFFFF;
  512. AINTC->IRQ0 = 0xFFFFFFFF;
  513. AINTC->IRQ1 = 0xFFFFFFFF;
  514. #ifdef PINMUX0_DEFAULT
  515. pinmuxControl(0, 0xFFFFFFFF, PINMUX0_DEFAULT);
  516. #endif
  517. #ifdef PINMUX1_DEFAULT
  518. pinmuxControl(1, 0xFFFFFFFF, PINMUX1_DEFAULT);
  519. #endif
  520. /* The folowing are only available on DM35x */
  521. #ifdef PINMUX2_DEFAULT
  522. pinmuxControl(2, 0xFFFFFFFF, PINMUX2_DEFAULT);
  523. #endif
  524. #ifdef PINMUX3_DEFAULT
  525. pinmuxControl(3, 0xFFFFFFFF, PINMUX3_DEFAULT);
  526. #endif
  527. #ifdef PINMUX4_DEFAULT
  528. pinmuxControl(4, 0xFFFFFFFF, PINMUX4_DEFAULT);
  529. #endif
  530. /* Init board configuration */
  531. #if defined(board_sysmobts_v2)
  532. char boardVer;
  533. char boardCfg;
  534. boardCfg = (*gpio01 >> 10) & 0x001F;
  535. boardVer = (*gpio01 >> 15) & 0x0007;
  536. if ( boardVer > 1 )
  537. {
  538. /* Davinci @ 405/810 MHz */
  539. pllCfg = PLL_DAVINCI_810_CFG;
  540. /* Micron MT47H64M16HR-3IT @ 189 MHz */
  541. ddrCfg = DDR_MT47H64M16HR_3IT_189MHz_CFG;
  542. uart_send_str_lf("CPU: Davinci @ 405/810 MHz");
  543. uart_send_str_lf("DDR: Micron MT47H64M16HR-3IT @ 189 MHz");
  544. } else if ( (boardVer == 1) && ((boardCfg == 0x02) || (boardCfg == 0x04) || (boardCfg == 0x05)) )
  545. {
  546. /* Davinci @ 405/810 MHz */
  547. pllCfg = PLL_DAVINCI_810_CFG;
  548. /* Micron MT47H64M16HR-3IT @ 189 MHz */
  549. ddrCfg = DDR_MT47H64M16HR_3IT_189MHz_CFG;
  550. uart_send_str_lf("CPU: Davinci @ 405/810 MHz");
  551. uart_send_str_lf("DDR: Micron MT47H64M16HR-3IT @ 189 MHz");
  552. }
  553. else if ( (boardVer == 0) && (boardCfg != 0x00) )
  554. {
  555. DDR_SIZE = (256 << 20);
  556. /* Davinci @ 297/594 MHz */
  557. pllCfg = PLL_DAVINCI_594_CFG;
  558. /* Micron MT47H32M16BN-3 @ 162 MHz */
  559. ddrCfg = DDR_MT47H64M16HR_3IT_162MHz_CFG;
  560. uart_send_str_lf("CPU: Davinci @ 297/594 MHz");
  561. uart_send_str_lf("DDR: Micron MT47H32M16BN-3 @ 162 MHz");
  562. }
  563. else
  564. #endif
  565. {
  566. #if defined(board_sysmobts_v2)
  567. DDR_SIZE = (256 << 20);
  568. #else
  569. DDR_SIZE = (128 << 20);
  570. #endif
  571. /* Davinci @ 297/594 MHz */
  572. pllCfg = PLL_DAVINCI_594_CFG;
  573. /* Micron MT47H32M16BN-3 @ 162 MHz */
  574. ddrCfg = DDR_MT47H32M16BN_3_162MHz_CFG;
  575. uart_send_str_lf("CPU: Davinci @ 297/594 MHz");
  576. uart_send_str_lf("DDR: Micron MT47H32M16BN-3 @ 162 MHz");
  577. }
  578. if (status == E_PASS)
  579. status |= pll1_init(pllCfg);
  580. if (status == E_PASS)
  581. status |= uart0_init();
  582. if (status == E_PASS)
  583. status |= timer0_setdefault_timeout();
  584. uart_send_lf();
  585. log_info(version);
  586. #if defined(board_sysmobts_v2)
  587. char str[4];
  588. uart_send_str("Board revision: ");
  589. str[0] = 'A' + boardVer;
  590. str[1] = '.';
  591. str[2] = '0' + boardCfg;
  592. str[3] = '\0';
  593. uart_send_str_lf(str);
  594. #endif
  595. if (status == E_PASS)
  596. status |= pll2_init(pllCfg);
  597. if (status == E_PASS)
  598. status |= ddr_init(ddrCfg);
  599. #ifdef STATUS_LED
  600. gpio_direction_out(STATUS_LED, 1);
  601. #endif /* STATUS_LED */
  602. #ifdef board_minidas
  603. gpio_direction_out(FAN, 0);
  604. gpio_direction_out(BUZZER, 0);
  605. /* Put all peripherals in RESET state */
  606. gpio_direction_out(DSP1_PWR_ENA, 0);
  607. gpio_direction_out(DSP2_PWR_ENA, 0);
  608. gpio_direction_out(WIFI_RESETn, 0);
  609. gpio_direction_out(GPS_RESETn, 0);
  610. gpio_direction_out(CAN_RESETn, 0);
  611. gpio_direction_out(ATA_RESETn, 0);
  612. gpio_direction_out(CAMERA_RESETn, 0);
  613. /* Enable power for hard disk */
  614. gpio_direction_out(HDD_ENA, 1);
  615. #endif
  616. /* IRQ Vector Table Setup */
  617. ivt_init();
  618. return status;
  619. }