112 lines
3.7 KiB
C
112 lines
3.7 KiB
C
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#undef CFG_HZ
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/*
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* MIPS32 24K Processor Core Family Software User's Manual
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*
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* 6.2.9 Count Register (CP0 Register 9, Select 0)
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* The Count register acts as a timer, incrementing at a constant
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* rate, whether or not an instruction is executed, retired, or
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* any forward progress is made through the pipeline. The counter
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* increments every other clock, if the DC bit in the Cause register
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* is 0.
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*/
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/* Since the count is incremented every other tick, divide by 2 */
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/* XXX derive this from CFG_PLL_FREQ */
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#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8
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#define CPU_CLK_CONTROL_VAL2 0x00008000
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#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
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# define CFG_HZ (200000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
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# define CFG_HZ (300000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_CONFIG_VAL1 0x40813C00
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#define CPU_PLL_CONFIG_VAL2 0x00813C00
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40816000
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#define CPU_PLL_CONFIG_VAL2 0x00816000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
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# define CFG_HZ (350000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#undef CPU_PLL_DITHER_FRAC_VAL
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#define CPU_PLL_DITHER_FRAC_VAL 0x001803E8
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#define CPU_PLL_CONFIG_VAL1 0x40814600
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#define CPU_PLL_CONFIG_VAL2 0x00814600
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40817000
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#define CPU_PLL_CONFIG_VAL2 0x00817000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166)
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# define CFG_HZ (333000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133)
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# define CFG_HZ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66)
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# define CFG_HZ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100)
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# define CFG_HZ (400000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_CONFIG_VAL1 0x40815000
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#define CPU_PLL_CONFIG_VAL2 0x00815000
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40818000
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#define CPU_PLL_CONFIG_VAL2 0x00818000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160)
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# define CFG_HZ (320000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200)
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# define CFG_HZ (410000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200)
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# define CFG_HZ (420000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_362_362_181)
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# define CFG_HZ (326500000/2)
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#define CPU_PLL_CONFIG_VAL1 0x40817400
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#define CPU_PLL_CONFIG_VAL2 0x00817400
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#elif (CFG_PLL_FREQ == CFG_PLL_80_80_40)
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# define CFG_HZ (80000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_64_64_32)
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# define CFG_HZ (64000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_48_48_24)
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# define CFG_HZ (48000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_32_32_16)
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# define CFG_HZ (32000000/2)
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#endif
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_SETTLE_TIME_VAL 0x00000550
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#else
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#define CPU_PLL_SETTLE_TIME_VAL 0x00000352
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#endif
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/* DDR init values */
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#define CONFIG_NR_DRAM_BANKS 2
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CFG_DDR_REFRESH_VAL 0x4270
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#else
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#define CFG_DDR_REFRESH_VAL 0x4186
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#endif
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#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
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#define CFG_DDR_MODE_VAL_INIT 0x133
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#ifdef LOW_DRIVE_STRENGTH
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# define CFG_DDR_EXT_MODE_VAL 0x2
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#else
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# define CFG_DDR_EXT_MODE_VAL 0x0
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#endif
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#define CFG_DDR_MODE_VAL 0x33
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#define CFG_DDR_TRTW_VAL 0x1f
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#define CFG_DDR_TWTR_VAL 0x1e
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//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0
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#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1
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#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff
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#define CFG_DDR_TAP0_VAL 0x8
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#define CFG_DDR_TAP1_VAL 0x9
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/* DDR2 Init values */
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#define CFG_DDR2_EXT_MODE_VAL 0x402
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