122 lines
4.4 KiB
C
122 lines
4.4 KiB
C
#ifndef _ATHRS26_PHY_H
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#define _ATHRS26_PHY_H
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/*****************/
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/* PHY Registers */
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/*****************/
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#define ATHR_PHY_CONTROL 0
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#define ATHR_PHY_STATUS 1
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#define ATHR_PHY_ID1 2
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#define ATHR_PHY_ID2 3
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#define ATHR_AUTONEG_ADVERT 4
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#define ATHR_LINK_PARTNER_ABILITY 5
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#define ATHR_AUTONEG_EXPANSION 6
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#define ATHR_NEXT_PAGE_TRANSMIT 7
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#define ATHR_LINK_PARTNER_NEXT_PAGE 8
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#define ATHR_1000BASET_CONTROL 9
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#define ATHR_1000BASET_STATUS 10
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#define ATHR_PHY_FUNC_CONTROL 16
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#define ATHR_PHY_SPEC_STATUS 17
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#define ATHR_DEBUG_PORT_ADDRESS 29
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#define ATHR_DEBUG_PORT_DATA 30
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/* ATHR_PHY_CONTROL fields */
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#define ATHR_CTRL_SOFTWARE_RESET 0x8000
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#define ATHR_CTRL_SPEED_LSB 0x2000
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#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
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#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
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#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
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#define ATHR_CTRL_SPEED_MSB 0x0040
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#define ATHR_RESET_DONE(phy_control) \
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(((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
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/* Phy status fields */
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#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
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#define ATHR_AUTONEG_DONE(ip_phy_status) \
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(((ip_phy_status) & \
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(ATHR_STATUS_AUTO_NEG_DONE)) == \
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(ATHR_STATUS_AUTO_NEG_DONE))
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/* Link Partner ability */
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#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
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#define ATHR_LINK_100BASETX 0x0080
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#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
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#define ATHR_LINK_10BASETX 0x0020
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/* Advertisement register. */
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#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
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#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
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#define ATHR_ADVERTISE_PAUSE 0x0400
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#define ATHR_ADVERTISE_100FULL 0x0100
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#define ATHR_ADVERTISE_100HALF 0x0080
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#define ATHR_ADVERTISE_10FULL 0x0040
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#define ATHR_ADVERTISE_10HALF 0x0020
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#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
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ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
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ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
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/* 1000BASET_CONTROL */
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#define ATHR_ADVERTISE_1000FULL 0x0200
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/* Phy Specific status fields */
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#define ATHER_STATUS_LINK_MASK 0xC000
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#define ATHER_STATUS_LINK_SHIFT 14
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#define ATHER_STATUS_FULL_DEPLEX 0x2000
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#define ATHR_STATUS_LINK_PASS 0x0400
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#define ATHR_LATCH_LINK_PASS 0x0004
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#define ATHR_STATUS_RESOVLED 0x0800
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/*phy debug port register */
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#define ATHER_DEBUG_SERDES_REG 5
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/* Serdes debug fields */
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#define ATHER_SERDES_BEACON 0x0100
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/* S26 CSR Registers */
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#define PORT_STATUS_REGISTER0 0x0100
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#define PORT_STATUS_REGISTER1 0x0200
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#define PORT_STATUS_REGISTER2 0x0300
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#define PORT_STATUS_REGISTER3 0x0400
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#define PORT_STATUS_REGISTER4 0x0500
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#define PORT_STATUS_REGISTER5 0x0600
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#define RATE_LIMIT_REGISTER0 0x010C
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#define RATE_LIMIT_REGISTER1 0x020C
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#define RATE_LIMIT_REGISTER2 0x030C
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#define RATE_LIMIT_REGISTER3 0x040C
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#define RATE_LIMIT_REGISTER4 0x050C
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#define RATE_LIMIT_REGISTER5 0x060C
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#define PORT_CONTROL_REGISTER0 0x0104
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#define PORT_CONTROL_REGISTER1 0x0204
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#define PORT_CONTROL_REGISTER2 0x0204
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#define PORT_CONTROL_REGISTER3 0x0204
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#define PORT_CONTROL_REGISTER4 0x0204
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#define PORT_CONTROL_REGISTER5 0x0204
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#define CPU_PORT_REGISTER 0x0078
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#define MDIO_CTRL_REGISTER 0x0098
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#define S26_ARL_TBL_FUNC_REG0 0x0050
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#define S26_ARL_TBL_FUNC_REG1 0x0054
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#define S26_ARL_TBL_FUNC_REG2 0x0058
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#define S26_ARL_TBL_CTRL_REG 0x005c
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#ifndef BOOL
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#define BOOL int
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#endif
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#define sysMsDelay(_x) udelay((_x) * 1000)
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#define mdelay(_x) sysMsDelay(_x)
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#define S26_FORCE_100M 1
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#endif
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