d94c2dbd0a
A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| config.mk | ||
| cpu.c | ||