87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/*
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* (C) Copyright 2010-2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/types.h>
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/* Stabilization delays, in usec */
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#if defined(CONFIG_TEGRA20)
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#define NVBL_PLLP_KHZ (216000)
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#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
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#define NVBL_PLLP_KHZ (408000)
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#else
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#error "Unknown Tegra chip!"
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#endif
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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#define SUPER_CCLK_DIVIDER 0x80000000
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/* Calculate clock fractional divider value from ref and target frequencies */
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#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
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/* Calculate clock frequency value from reference and clock divider value */
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#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
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/* AVP/CPU ID */
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#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
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#define PG_UP_TAG_0 0x0
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#define CORESIGHT_UNLOCK 0xC5ACCE55;
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
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#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
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#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
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#define FLOW_MODE_STOP 2
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#define HALT_COP_EVENT_JTAG (1 << 28)
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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#define FLOW_MODE_NONE 0
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#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
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struct clk_pll_table {
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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void clock_enable_coresight(int enable);
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void enable_cpu_clock(int enable);
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void halt_avp(void) __attribute__ ((noreturn));
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void init_pllx(void);
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void powerup_cpu(void);
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void reset_A9_cpu(int reset);
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void start_cpu(u32 reset_vector);
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int tegra_get_chip(void);
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int tegra_get_sku_info(void);
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int tegra_get_chip_sku(void);
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void adjust_pllp_out_freqs(void);
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