342 lines
8.8 KiB
C
342 lines
8.8 KiB
C
/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/scu.h>
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#include "cpu.h"
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int get_num_cpus(void)
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{
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struct apb_misc_gp_ctlr *gp;
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uint rev;
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gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
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rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
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switch (rev) {
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case CHIPID_TEGRA20:
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return 2;
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break;
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case CHIPID_TEGRA30:
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case CHIPID_TEGRA114:
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default:
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return 4;
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break;
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}
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}
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/*
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* Timing tables for each SOC for all four oscillator options.
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*/
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struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
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/* T20: 1 GHz */
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/* n, m, p, cpcon */
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{{ 1000, 13, 0, 12}, /* OSC 13M */
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{ 625, 12, 0, 8}, /* OSC 19.2M */
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{ 1000, 12, 0, 12}, /* OSC 12M */
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{ 1000, 26, 0, 12}, /* OSC 26M */
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},
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/* T25: 1.2 GHz */
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{{ 923, 10, 0, 12},
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{ 750, 12, 0, 8},
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{ 600, 6, 0, 12},
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{ 600, 13, 0, 12},
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},
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/* T30: 1.4 GHz */
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{{ 862, 8, 0, 8},
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{ 583, 8, 0, 4},
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{ 700, 6, 0, 8},
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{ 700, 13, 0, 8},
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},
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/* T114: 1.4 GHz */
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{{ 862, 8, 0, 8},
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{ 583, 8, 0, 4},
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{ 696, 12, 0, 8},
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{ 700, 13, 0, 8},
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},
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};
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void adjust_pllp_out_freqs(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
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u32 reg;
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/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
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reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
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reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
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| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
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writel(reg, &pll->pll_out[0]);
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reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
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reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
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| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
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writel(reg, &pll->pll_out[1]);
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}
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int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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u32 reg;
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/* If PLLX is already enabled, just return */
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
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debug("pllx_set_rate: PLLX already enabled, returning\n");
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return 0;
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}
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debug(" pllx_set_rate entry\n");
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
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reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
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writel(reg, &pll->pll_base);
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/* Set cpcon to PLLX_MISC */
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reg = (cpcon << PLL_CPCON_SHIFT);
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/* Set dccon to PLLX_MISC if freq > 600MHz */
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if (divn > 600)
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reg |= (1 << PLL_DCCON_SHIFT);
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writel(reg, &pll->pll_misc);
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/* Enable PLLX */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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/* Disable BYPASS */
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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/* Set lock_enable to PLLX_MISC */
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reg = readl(&pll->pll_misc);
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reg |= PLL_LOCK_ENABLE_MASK;
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writel(reg, &pll->pll_misc);
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return 0;
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}
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void init_pllx(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
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int soc_type, sku_info, chip_sku;
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enum clock_osc_freq osc;
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struct clk_pll_table *sel;
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debug("init_pllx entry\n");
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/* get SOC (chip) type */
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soc_type = tegra_get_chip();
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debug(" init_pllx: SoC = 0x%02X\n", soc_type);
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/* get SKU info */
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sku_info = tegra_get_sku_info();
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debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
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/* get chip SKU, combo of the above info */
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chip_sku = tegra_get_chip_sku();
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debug(" init_pllx: Chip SKU = %d\n", chip_sku);
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/* get osc freq */
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osc = clock_get_osc_freq();
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debug(" init_pllx: osc = %d\n", osc);
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/* set pllx */
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sel = &tegra_pll_x_table[chip_sku][osc];
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pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
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/* adjust PLLP_out1-4 on T3x/T114 */
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if (soc_type >= CHIPID_TEGRA30) {
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debug(" init_pllx: adjusting PLLP out freqs\n");
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adjust_pllp_out_freqs();
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}
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}
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void enable_cpu_clock(int enable)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 clk;
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/*
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* NOTE:
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* Regardless of whether the request is to enable or disable the CPU
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* clock, every processor in the CPU complex except the master (CPU 0)
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* will have it's clock stopped because the AVP only talks to the
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* master.
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*/
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if (enable) {
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/* Initialize PLLX */
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init_pllx();
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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}
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/*
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* Read the register containing the individual CPU clock enables and
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* always stop the clocks to CPUs > 0.
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*/
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clk = readl(&clkrst->crc_clk_cpu_cmplx);
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clk |= 1 << CPU1_CLK_STP_SHIFT;
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if (get_num_cpus() == 4)
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clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
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/* Stop/Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP_MASK;
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clk |= !enable << CPU0_CLK_STP_SHIFT;
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writel(clk, &clkrst->crc_clk_cpu_cmplx);
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clock_enable(PERIPH_ID_CPU);
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}
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static int is_cpu_powered(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
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}
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static void remove_cpu_io_clamps(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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/* Remove the clamps on the CPU I/O signals */
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reg = readl(&pmc->pmc_remove_clamping);
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reg |= CPU_CLMP;
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writel(reg, &pmc->pmc_remove_clamping);
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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void powerup_cpu(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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int timeout = IO_STABILIZATION_DELAY;
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if (!is_cpu_powered()) {
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/* Toggle the CPU power state (OFF -> ON) */
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reg = readl(&pmc->pmc_pwrgate_toggle);
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reg &= PARTID_CP;
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reg |= START_CP;
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writel(reg, &pmc->pmc_pwrgate_toggle);
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/* Wait for the power to come up */
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while (!is_cpu_powered()) {
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if (timeout-- == 0)
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printf("CPU failed to power up!\n");
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else
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udelay(10);
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}
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/*
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* Remove the I/O clamps from CPU power partition.
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* Recommended only on a Warm boot, if the CPU partition gets
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* power gated. Shouldn't cause any harm when called after a
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* cold boot according to HW, probably just redundant.
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*/
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remove_cpu_io_clamps();
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}
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}
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void reset_A9_cpu(int reset)
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{
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset
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* or take it out of reset, every processor in the CPU complex
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* except the master (CPU 0) will be held in reset because the
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* AVP only talks to the master. The AVP does not know that there
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* are multiple processors in the CPU complex.
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*/
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int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
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int num_cpus = get_num_cpus();
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int cpu;
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debug("reset_a9_cpu entry\n");
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/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
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for (cpu = 1; cpu < num_cpus; cpu++)
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reset_cmplx_set_enable(cpu, mask, 1);
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reset_cmplx_set_enable(0, mask, reset);
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/* Enable/Disable master CPU reset */
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reset_set_enable(PERIPH_ID_CPU, reset);
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}
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void clock_enable_coresight(int enable)
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{
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u32 rst, src = 2;
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int soc_type;
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debug("clock_enable_coresight entry\n");
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clock_set_enable(PERIPH_ID_CORESIGHT, enable);
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reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
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if (enable) {
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/*
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* Put CoreSight on PLLP_OUT0 and divide it down as per
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* PLLP base frequency based on SoC type (T20/T30/T114).
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* Clock divider request would setup CSITE clock as 144MHz
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* for PLLP base 216MHz and 204MHz for PLLP base 408MHz
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*/
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soc_type = tegra_get_chip();
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if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
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else if (soc_type == CHIPID_TEGRA20)
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
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else
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printf("%s: Unknown SoC type %X!\n",
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__func__, soc_type);
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clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
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/* Unlock the CPU CoreSight interfaces */
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rst = CORESIGHT_UNLOCK;
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writel(rst, CSITE_CPU_DBG0_LAR);
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writel(rst, CSITE_CPU_DBG1_LAR);
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if (get_num_cpus() == 4) {
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writel(rst, CSITE_CPU_DBG2_LAR);
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writel(rst, CSITE_CPU_DBG3_LAR);
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}
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}
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}
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void halt_avp(void)
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{
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for (;;) {
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
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FLOW_CTLR_HALT_COP_EVENTS);
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}
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}
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