376 lines
7.6 KiB
ArmAsm
Executable File
376 lines
7.6 KiB
ArmAsm
Executable File
#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <ar7240_soc.h>
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.globl hornet_pll_init
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.text
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.align 4
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/*
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* Helper macros.
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* These Clobber t7, t8 and t9
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*/
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/* or t8, t8, t9; \ */
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#define set_reg(_reg, _val) \
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li t7, KSEG1ADDR(_reg); \
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lw t8, 0(t7); \
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li t9, _val; \
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sw t9, 0(t7);
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hornet_pll_init:
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#if 1
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/* These three wlan reset will avoid original issue,
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so full chip reset isn't needed here. */
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set_reg(0xb806001c, 0x00c06b30)
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nop
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set_reg(0xb806001c, 0x00c06330)
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nop
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set_reg(0xb806001c, 0x00c06b30)
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nop
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set_reg(0xb806001c, 0x00c06330)
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nop
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reset_wlan:
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set_reg(0xb806001c, 0x00c06b30)
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nop
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set_reg(0xb806001c, 0x00c06330)
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nop
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li t5, 0x20
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check_val:
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beq zero, t5, reset_wlan
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addi t5, t5, -1
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li t6, 0xb80600ac
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lw t7, 0(t6)
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li t8, 0x10
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and t7, t7, t8
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bne zero, t7, check_val
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set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e)
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nop
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#else
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/* clear wlan reset bit in RESET_Register 0x1c */
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set_reg(AR7240_RESET, 0x00c06b30)
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nop
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set_reg(AR7240_RESET, 0x00c06330)
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nop
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/* cleck bootstrap status, wait for bit4 on, then clear bit16 */
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wait_loop0:
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li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS)
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lw t7, 0(t6)
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li t8, 0x10
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and t7, t7, t8
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bne zero, t7, wait_loop0
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nop
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set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e)
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nop
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#endif
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/* RTC reset */
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set_reg(0x1810704c, 0x00000003)
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nop
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nop
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set_reg(0x18107040, 0x00000000)
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nop
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nop
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set_reg(0x18107040, 0x00000001)
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nop
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wait_loop1:
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li t6, KSEG1ADDR(0x18107044)
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lw t7, 0(t6)
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li t8, 0x2
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and t7, t7, t8
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bne t8, t7, wait_loop1
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nop
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/* AHB/APH reset */
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set_reg(0x18104000, 0x00000003)
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nop
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set_reg(0x18104000, 0x00000000)
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nop
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/* MAC reset */
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set_reg(0x18107000, 0x0000000F)
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nop
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set_reg(0x18107000, 0x00000000)
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nop
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#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */
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li t1, KSEG1ADDR(0x18114014)
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lw t2, 0(t1)
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otp_loop0:
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li t3, KSEG1ADDR(0x18115f18)
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lw t4, 0(t3)
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nop
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li t5, 0x7
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and t4, t4, t5
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li t5, 0x4
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bne t4, t5, otp_loop0
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nop
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li t6, KSEG1ADDR(0x18115f1c)
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lw t7, 0(t6)
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nop
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li t8, 0x80000080
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and t9, t7, t8
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beq t8, t9, fetch_otp
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otp_loop0_end:
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li t1, KSEG1ADDR(0x18114004)
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lw t2, 0(t1)
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otp_loop1:
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li t3, KSEG1ADDR(0x18115f18)
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lw t4, 0(t3)
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nop
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li t5, 0x7
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and t4, t4, t5
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li t5, 0x4
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bne t4, t5, otp_loop1
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nop
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li t6, KSEG1ADDR(0x18115f1c)
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lw t7, 0(t6)
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nop
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li t8, 0x80000080
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and t9, t7, t8
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default_pmu:
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li t5, 0x80 /* default 0x031c4386 */
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bne t8, t9, otp_end
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otp_loop1_end:
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fetch_otp:
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srl t8, t7, 0x18
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li t1, 0xf
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and t2, t1 , t7 /* USB */
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and t5, t1 , t8 /* PMU */
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check_pmu:
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li t0, 0x4 /* PMU range should be 0x4~0xa */
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bgt t0, t5, default_pmu
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nop
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li t0, 0xa /* PMU range should be 0x4~0xa */
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blt t0, t5, default_pmu
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nop
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li t0, 0x4
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sll t5, t5, t0
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otp_end:
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#endif
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#if 1 /* Program PMU */
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#define PMU_TEST_NO 1000
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li t6, KSEG1ADDR(0x18116c40)
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li t9, 0xbd000010
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li t0, 0
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li t1, 0
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li t2, 0
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li t3, PMU_TEST_NO
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sw t3, 12(t9)
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pmu_loop0:
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beq zero, t3, pmu_loop0_end
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nop
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addi t3, t3, -1
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#li t7, 0x10000000 /* ldo_tune 0x0 */
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#li t7, 0x10080000 /* ldo_tune 0x1 */
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#li t7, 0x10100000 /* ldo_tune 0x2 */
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li t7, 0x10180000 /* ldo_tune 0x3 */
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nop
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sw t7, 4(t6)
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nop
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lw t8, 4(t6)
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nop
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beq t8, t7, pmu_loop0_end
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nop
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addiu t0, t0, 1
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b pmu_loop0
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nop
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pmu_loop0_end:
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li t3, PMU_TEST_NO
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pmu_loop1:
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beq zero, t3, pmu_loop1_end
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nop
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addi t3, t3, -1
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//li t7, 0x031c4326 /* 1.100V */
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//li t7, 0x031c4336 /* 1.125V */
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//li t7, 0x031c4346 /* 1.150V */
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//li t7, 0x031c4356 /* 1.175V */
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//li t7, 0x031c4366 /* 1.200V */
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//li t7, 0x031c4376 /* 1.225V */
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li t7, 0x031c4386 /* 1.250V */
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//li t7, 0x031c4396 /* 1.275V */
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//li t7, 0x031c43a6 /* 1.300V */
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nop
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#if 1 /* from OTP */
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li t8, 0xffffff0f
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and t7, t7, t8
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or t7, t7, t5
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#endif
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sw t7, 0(t6)
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nop
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lw t8, 0(t6)
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nop
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beq t8, t7, pmu_loop1_end
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nop
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addiu t1, t1, 1
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b pmu_loop1
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nop
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pmu_loop1_end:
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li t3, PMU_TEST_NO
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pmu_loop2:
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beq zero, t3, pmu_loop2_end
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nop
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addi t3, t3, -1
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#li t7, 0x10200000 /* ldo_tune 0x0 */
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#li t7, 0x10280000 /* ldo_tune 0x1 */
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#li t7, 0x10300000 /* ldo_tune 0x2 */
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li t7, 0x10380000 /* ldo_tune 0x3 */
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nop
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sw t7, 4(t6)
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nop
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lw t8, 4(t6)
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nop
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beq t8, t7, pmu_loop2_end
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nop
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addiu t2, t2, 1
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b pmu_loop2
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nop
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pmu_loop2_end:
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sw t0, 0(t9)
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nop
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sw t1, 4(t9)
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nop
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sw t2, 8(t9)
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nop
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#endif
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#if 1 /* Program ki, kd */
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/* Program ki/kd */
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#if CONFIG_40MHZ_XTAL_SUPPORT
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set_reg(0x18116244, 0x19e82f01)
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#else
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set_reg(0x18116244, 0x18e82f01)
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#endif
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nop
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/* Program phase shift */
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li t6, KSEG1ADDR(0x18116248)
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lw t7, 0(t6)
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li t8, 0xc07fffff
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and t7, t7, t8
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li t8, 0x800000
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or t7, t7, t8
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sw t7, 0(t6)
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nop
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#endif
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/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
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set_reg(AR7240_CPU_CLOCK_CONTROL, 0x00018004)
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nop
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/* set SETTLE_TIME in CPU PLL */
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set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL)
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nop
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pll_unlock_handler:
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/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */
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set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1)
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nop
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wait_loop2:
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li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
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lw t7, 0(t6)
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li t8, 0x80000000
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and t7, t7, t8
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bne zero, t7, wait_loop2
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nop
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/* put frac bit19:10 configuration */
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set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL)
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nop
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/* clear PLL power down bit in CPU PLLl configuration */
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set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2)
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nop
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wait_loop3:
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li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG)
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lw t7, 0(t6)
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li t8, 0x80000000
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and t7, t7, t8
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bne zero, t7, wait_loop3
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nop
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/* confirm DDR PLL lock */
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li t3, 100
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li t4, 0
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start_meas0:
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addi t4, t4, 1
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bgt t4, t3, pll_unlock_handler
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nop
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li t5, 5
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start_meas:
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li t6, KSEG1ADDR(0x18116248)
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lw t7, 0(t6)
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li t8, 0xbfffffff
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and t7, t7, t8
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sw t7, 0(t6)
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nop
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/* delay */
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li t9, 10
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delayloop0:
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subu t9, t9, 1
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bne t9, zero, delayloop0
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nop
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li t8, 0x40000000
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or t7, t7, t8
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sw t7, 0(t6)
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nop
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meas_done_statue:
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li t6, KSEG1ADDR(0x1811624c)
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lw t7, 0(t6)
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li t8, 0x8
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and t7, t7, t8
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beq zero, t7, meas_done_statue
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nop
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meas_result:
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li t6, KSEG1ADDR(0x18116248)
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lw t7, 0(t6)
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li t8, 0x007ffff8
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and t7, t7, t8
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srl t7, t7, 3
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li t8, 0x4000
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bgt t7, t8, start_meas0
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nop
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addi t5, t5, -1
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bne zero, t5, start_meas
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nop
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/* clear PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */
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set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL2)
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nop
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/* Sync mode , Set Bit 8 of DDR Tap Conrtol 3 register */
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set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105);
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nop
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jr ra
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nop
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