469 lines
11 KiB
C
469 lines
11 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <asm/imx-common/hab.h>
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#include <asm/imx-common/rdc-sema.h>
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#include <asm/arch/imx-rdc.h>
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#include <asm/arch/crm_regs.h>
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#include <dm.h>
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#include <imx_thermal.h>
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#if defined(CONFIG_IMX_THERMAL)
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static const struct imx_thermal_plat imx7_thermal_plat = {
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.regs = (void *)ANATOP_BASE_ADDR,
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.fuse_bank = 3,
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.fuse_word = 3,
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};
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U_BOOT_DEVICE(imx7_thermal) = {
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.name = "imx_thermal",
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.platdata = &imx7_thermal_plat,
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};
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#endif
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#ifdef CONFIG_IMX_RDC
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/*
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* In current design, if any peripheral was assigned to both A7 and M4,
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* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
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* low power mode. So M4 sleep will cause some peripherals fail to work
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* at A7 core side. At default, all resources are in domain 0 - 3.
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*
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* There are 26 peripherals impacted by this IC issue:
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* SIM2(sim2/emvsim2)
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* SIM1(sim1/emvsim1)
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* UART1/UART2/UART3/UART4/UART5/UART6/UART7
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* SAI1/SAI2/SAI3
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* WDOG1/WDOG2/WDOG3/WDOG4
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* GPT1/GPT2/GPT3/GPT4
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* PWM1/PWM2/PWM3/PWM4
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* ENET1/ENET2
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* Software Workaround:
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* Here we setup some resources to domain 0 where M4 codes will move
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* the M4 out of this domain. Then M4 is not able to access them any longer.
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* This is a workaround for ic issue. So the peripherals are not shared
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* by them. This way requires the uboot implemented the RDC driver and
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* set the 26 IPs above to domain 0 only. M4 code will assign resource
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* to its own domain, if it want to use the resource.
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*/
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static rdc_peri_cfg_t const resources[] = {
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(RDC_PER_SIM1 | RDC_DOMAIN(0)),
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(RDC_PER_SIM2 | RDC_DOMAIN(0)),
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(RDC_PER_UART1 | RDC_DOMAIN(0)),
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(RDC_PER_UART2 | RDC_DOMAIN(0)),
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(RDC_PER_UART3 | RDC_DOMAIN(0)),
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(RDC_PER_UART4 | RDC_DOMAIN(0)),
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(RDC_PER_UART5 | RDC_DOMAIN(0)),
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(RDC_PER_UART6 | RDC_DOMAIN(0)),
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(RDC_PER_UART7 | RDC_DOMAIN(0)),
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(RDC_PER_SAI1 | RDC_DOMAIN(0)),
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(RDC_PER_SAI2 | RDC_DOMAIN(0)),
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(RDC_PER_SAI3 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
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(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
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(RDC_PER_GPT1 | RDC_DOMAIN(0)),
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(RDC_PER_GPT2 | RDC_DOMAIN(0)),
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(RDC_PER_GPT3 | RDC_DOMAIN(0)),
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(RDC_PER_GPT4 | RDC_DOMAIN(0)),
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(RDC_PER_PWM1 | RDC_DOMAIN(0)),
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(RDC_PER_PWM2 | RDC_DOMAIN(0)),
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(RDC_PER_PWM3 | RDC_DOMAIN(0)),
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(RDC_PER_PWM4 | RDC_DOMAIN(0)),
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(RDC_PER_ENET1 | RDC_DOMAIN(0)),
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(RDC_PER_ENET2 | RDC_DOMAIN(0)),
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};
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static void isolate_resource(void)
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{
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imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
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}
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#endif
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#if defined(CONFIG_SECURE_BOOT)
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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.bank = 1,
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.word = 3,
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};
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#endif
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/*
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* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_SPEED_SHIFT 8
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#define OCOTP_TESTER3_SPEED_800MHZ 0
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#define OCOTP_TESTER3_SPEED_500MHZ 1
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#define OCOTP_TESTER3_SPEED_1GHZ 2
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#define OCOTP_TESTER3_SPEED_1P2GHZ 3
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u32 get_cpu_speed_grade_hz(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_SPEED_SHIFT;
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val &= 0x3;
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switch(val) {
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case OCOTP_TESTER3_SPEED_800MHZ:
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return 800000000;
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case OCOTP_TESTER3_SPEED_500MHZ:
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return 500000000;
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case OCOTP_TESTER3_SPEED_1GHZ:
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return 1000000000;
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case OCOTP_TESTER3_SPEED_1P2GHZ:
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return 1200000000;
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}
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return 0;
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}
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/*
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* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
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* defines a 2-bit SPEED_GRADING
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*/
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#define OCOTP_TESTER3_TEMP_SHIFT 6
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u32 get_cpu_temp_grade(int *minc, int *maxc)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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uint32_t val;
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val = readl(&fuse->tester3);
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val >>= OCOTP_TESTER3_TEMP_SHIFT;
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val &= 0x3;
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if (minc && maxc) {
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if (val == TEMP_AUTOMOTIVE) {
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*minc = -40;
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*maxc = 125;
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} else if (val == TEMP_INDUSTRIAL) {
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*minc = -40;
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*maxc = 105;
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} else if (val == TEMP_EXTCOMMERCIAL) {
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*minc = -20;
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*maxc = 105;
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} else {
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*minc = 0;
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*maxc = 95;
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}
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}
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return val;
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}
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static bool is_mx7d(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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int val;
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val = readl(&fuse->tester4);
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if (val & 1)
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return false;
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else
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return true;
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}
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u32 get_cpu_rev(void)
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{
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struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
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ANATOP_BASE_ADDR;
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u32 reg = readl(&ccm_anatop->digprog);
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u32 type = (reg >> 16) & 0xff;
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if (!is_mx7d())
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type = MXC_CPU_MX7S;
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reg &= 0xff;
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return (type << 12) | reg;
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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return get_cpu_rev();
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}
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#endif
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/* enable all periherial can be accessed in nosec mode */
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static void init_csu(void)
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{
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int i = 0;
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for (i = 0; i < CSU_NUM_REGS; i++)
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writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
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}
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static void imx_enet_mdio_fixup(void)
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{
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struct iomuxc_gpr_base_regs *gpr_regs =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/*
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* The management data input/output (MDIO) requires open-drain,
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* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
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* this feature. So to TO1.1, need to enable open drain by setting
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* bits GPR0[8:7].
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*/
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if (soc_rev() >= CHIP_REV_1_1) {
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setbits_le32(&gpr_regs->gpr[0],
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IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
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}
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}
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int arch_cpu_init(void)
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{
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init_aips();
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init_csu();
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/* Disable PDE bit of WMCR register */
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imx_set_wdog_powerdown(false);
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imx_enet_mdio_fixup();
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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if (IS_ENABLED(CONFIG_IMX_RDC))
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isolate_resource();
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return 0;
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}
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (is_mx7d())
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setenv("soc", "imx7d");
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else
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setenv("soc", "imx7s");
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_SERIAL_TAG
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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serialnr->low = fuse->tester0;
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serialnr->high = fuse->tester1;
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[9];
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struct fuse_bank9_regs *fuse =
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(struct fuse_bank9_regs *)bank->fuse_regs;
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if (0 == dev_id) {
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u32 value = readl(&fuse->mac_addr1);
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mac[0] = (value >> 8);
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mac[1] = value;
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value = readl(&fuse->mac_addr0);
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mac[2] = value >> 24;
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mac[3] = value >> 16;
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mac[4] = value >> 8;
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mac[5] = value;
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} else {
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u32 value = readl(&fuse->mac_addr2);
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mac[0] = value >> 24;
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mac[1] = value >> 16;
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mac[2] = value >> 8;
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mac[3] = value;
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value = readl(&fuse->mac_addr1);
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mac[4] = value >> 24;
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mac[5] = value >> 16;
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}
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}
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#endif
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#ifdef CONFIG_IMX_BOOTAUX
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int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
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{
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u32 stack, pc;
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struct src *src_reg = (struct src *)SRC_BASE_ADDR;
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if (!boot_private_data)
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return 1;
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stack = *(u32 *)boot_private_data;
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pc = *(u32 *)(boot_private_data + 4);
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/* Set the stack and pc to M4 bootROM */
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writel(stack, M4_BOOTROM_BASE_ADDR);
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writel(pc, M4_BOOTROM_BASE_ADDR + 4);
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/* Enable M4 */
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clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
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SRC_M4RCR_ENABLE_M4_MASK);
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return 0;
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}
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int arch_auxiliary_core_check_up(u32 core_id)
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{
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uint32_t val;
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struct src *src_reg = (struct src *)SRC_BASE_ADDR;
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val = readl(&src_reg->m4rcr);
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if (val & 0x00000001)
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return 0; /* assert in reset */
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return 1;
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}
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#endif
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void set_wdog_reset(struct wdog_regs *wdog)
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{
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u32 reg = readw(&wdog->wcr);
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/*
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* Output WDOG_B signal to reset external pmic or POR_B decided by
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* the board desgin. Without external reset, the peripherals/DDR/
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* PMIC are not reset, that may cause system working abnormal.
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*/
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reg = readw(&wdog->wcr);
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reg |= 1 << 3;
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/*
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* WDZST bit is write-once only bit. Align this bit in kernel,
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* otherwise kernel code will have no chance to set this bit.
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*/
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reg |= 1 << 0;
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writew(reg, &wdog->wcr);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
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{"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
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{"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
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{"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
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{"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
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{"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
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/* 4 bit bus width */
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{"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
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{"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
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{"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
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{"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
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{"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
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{"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
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{NULL, 0},
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};
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enum boot_device get_boot_device(void)
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{
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struct bootrom_sw_info **p =
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
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enum boot_device boot_dev = SD1_BOOT;
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u8 boot_type = (*p)->boot_dev_type;
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u8 boot_instance = (*p)->boot_dev_instance;
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switch (boot_type) {
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case BOOT_TYPE_SD:
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boot_dev = boot_instance + SD1_BOOT;
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break;
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case BOOT_TYPE_MMC:
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boot_dev = boot_instance + MMC1_BOOT;
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break;
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case BOOT_TYPE_NAND:
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boot_dev = NAND_BOOT;
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break;
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case BOOT_TYPE_QSPI:
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boot_dev = QSPI_BOOT;
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break;
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case BOOT_TYPE_WEIM:
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boot_dev = WEIM_NOR_BOOT;
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break;
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case BOOT_TYPE_SPINOR:
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boot_dev = SPI_NOR_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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#ifdef CONFIG_ENV_IS_IN_MMC
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__weak int board_mmc_get_env_dev(int devno)
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{
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return CONFIG_SYS_MMC_ENV_DEV;
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}
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int mmc_get_env_dev(void)
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{
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struct bootrom_sw_info **p =
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
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int devno = (*p)->boot_dev_instance;
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u8 boot_type = (*p)->boot_dev_type;
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/* If not boot from sd/mmc, use default value */
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if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
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return CONFIG_SYS_MMC_ENV_DEV;
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return board_mmc_get_env_dev(devno);
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}
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#endif
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void s_init(void)
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{
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#if !defined CONFIG_SPL_BUILD
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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#endif
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/* clock configuration. */
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clock_init();
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return;
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}
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void reset_misc(void)
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{
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#ifdef CONFIG_VIDEO_MXS
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lcdif_power_down();
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#endif
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}
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