The sdram controller blocks are very similar to the rk3288 in utilizing
memory scheduler, Designware uPCTL and Designware PUBL blocks, only
limited to one bank instead of two.
There are some minimal differences when setting up the ram, so it gets
a separate driver for the rk3188 but reuses the driver structs, as there
is no need to define the same again.
More optimization can happen when the modelling of the controller parts
in the dts actually follow the hardware layout hopefully at some point
in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART:
Signed-off-by: Simon Glass <sjg@chromium.org>
Heiko Stübner